OV - exec - Loop 2097

	Loop Id: 2097	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.03%

0x525c70 CMP	%RAX,%RSI

0x525c73 JLE	525fd2

0x525c79 LEA	(%R12,%RAX,8),%R15

0x525c7d LEA	(%R12,%RSI,8),%RAX

0x525c81 VXORPD	%XMM0,%XMM0,%XMM0

0x525c85 MOV	%RAX,%RSI

0x525c88 SUB	%R15,%RSI

0x525c8b SUB	$0x8,%RSI

0x525c8f SHR	$0x3,%RSI

0x525c93 INC	%RSI

0x525c96 AND	$0x7,%ESI

0x525c99 JE	525d6e

0x525c9f CMP	$0x1,%RSI

0x525ca3 JE	525d4e

0x525ca9 CMP	$0x2,%RSI

0x525cad JE	525d38

0x525cb3 CMP	$0x3,%RSI

0x525cb7 JE	525d22

0x525cb9 CMP	$0x4,%RSI

0x525cbd JE	525d0b

0x525cbf CMP	$0x5,%RSI

0x525cc3 JE	525cf4

0x525cc5 CMP	$0x6,%RSI

0x525cc9 JE	525cdd

0x525ccb VMOVSD	(%R15),%XMM2

0x525cd0 ADD	$0x8,%R15

0x525cd4 VANDPD	%XMM11,%XMM2,%XMM0

0x525cd9 VMOVSD	%XMM0,(%RCX)

0x525cdd VMOVSD	(%R15),%XMM15

0x525ce2 ADD	$0x8,%R15

0x525ce6 VANDPD	%XMM11,%XMM15,%XMM14

0x525ceb VADDSD	%XMM14,%XMM0,%XMM0

0x525cf0 VMOVSD	%XMM0,(%RCX)

0x525cf4 VMOVSD	(%R15),%XMM1

0x525cf9 ADD	$0x8,%R15

0x525cfd VANDPD	%XMM11,%XMM1,%XMM8

0x525d02 VADDSD	%XMM8,%XMM0,%XMM0

0x525d07 VMOVSD	%XMM0,(%RCX)

0x525d0b VMOVSD	(%R15),%XMM9

0x525d10 ADD	$0x8,%R15

0x525d14 VANDPD	%XMM11,%XMM9,%XMM10

0x525d19 VADDSD	%XMM10,%XMM0,%XMM0

0x525d1e VMOVSD	%XMM0,(%RCX)

0x525d22 VMOVSD	(%R15),%XMM13

0x525d27 ADD	$0x8,%R15

0x525d2b VANDPD	%XMM11,%XMM13,%XMM6

0x525d30 VADDSD	%XMM6,%XMM0,%XMM0

0x525d34 VMOVSD	%XMM0,(%RCX)

0x525d38 VMOVSD	(%R15),%XMM4

0x525d3d ADD	$0x8,%R15

0x525d41 VANDPD	%XMM11,%XMM4,%XMM5

0x525d46 VADDSD	%XMM5,%XMM0,%XMM0

0x525d4a VMOVSD	%XMM0,(%RCX)

0x525d4e VMOVSD	(%R15),%XMM2

0x525d53 ADD	$0x8,%R15

0x525d57 VANDPD	%XMM11,%XMM2,%XMM15

0x525d5c VADDSD	%XMM15,%XMM0,%XMM0

0x525d61 VMOVSD	%XMM0,(%RCX)

0x525d65 CMP	%R15,%RAX

0x525d68 JE	525e16

  (2099) 0x525d6e VMOVSD	(%R15),%XMM14

  (2099) 0x525d73 VANDPD	%XMM11,%XMM14,%XMM1

  (2099) 0x525d78 ADD	$0x40,%R15

  (2099) 0x525d7c VADDSD	%XMM1,%XMM0,%XMM8

  (2099) 0x525d80 VMOVSD	%XMM8,(%RCX)

  (2099) 0x525d84 VMOVSD	-0x38(%R15),%XMM9

  (2099) 0x525d8a VANDPD	%XMM11,%XMM9,%XMM10

  (2099) 0x525d8f VADDSD	%XMM10,%XMM8,%XMM13

  (2099) 0x525d94 VMOVSD	%XMM13,(%RCX)

  (2099) 0x525d98 VMOVSD	-0x30(%R15),%XMM6

  (2099) 0x525d9e VANDPD	%XMM11,%XMM6,%XMM4

  (2099) 0x525da3 VADDSD	%XMM4,%XMM13,%XMM5

  (2099) 0x525da7 VMOVSD	%XMM5,(%RCX)

  (2099) 0x525dab VMOVSD	-0x28(%R15),%XMM2

  (2099) 0x525db1 VANDPD	%XMM11,%XMM2,%XMM15

  (2099) 0x525db6 VADDSD	%XMM15,%XMM5,%XMM0

  (2099) 0x525dbb VMOVSD	%XMM0,(%RCX)

  (2099) 0x525dbf VMOVSD	-0x20(%R15),%XMM14

  (2099) 0x525dc5 VANDPD	%XMM11,%XMM14,%XMM1

  (2099) 0x525dca VADDSD	%XMM1,%XMM0,%XMM8

  (2099) 0x525dce VMOVSD	%XMM8,(%RCX)

  (2099) 0x525dd2 VMOVSD	-0x18(%R15),%XMM9

  (2099) 0x525dd8 VANDPD	%XMM11,%XMM9,%XMM10

  (2099) 0x525ddd VADDSD	%XMM10,%XMM8,%XMM13

  (2099) 0x525de2 VMOVSD	%XMM13,(%RCX)

  (2099) 0x525de6 VMOVSD	-0x10(%R15),%XMM6

  (2099) 0x525dec VANDPD	%XMM11,%XMM6,%XMM4

  (2099) 0x525df1 VADDSD	%XMM4,%XMM13,%XMM5

  (2099) 0x525df5 VMOVSD	%XMM5,(%RCX)

  (2099) 0x525df9 VMOVSD	-0x8(%R15),%XMM2

  (2099) 0x525dff VANDPD	%XMM11,%XMM2,%XMM15

  (2099) 0x525e04 VADDSD	%XMM15,%XMM5,%XMM0

  (2099) 0x525e09 VMOVSD	%XMM0,(%RCX)

  (2099) 0x525e0d CMP	%R15,%RAX

  (2099) 0x525e10 JNE	525d6e

0x525e16 CMPQ	$0,-0x40(%RBP)

0x525e1b JNE	525e49

0x525e1d INC	%R8

0x525e20 ADD	$0x8,%RCX

0x525e24 CMP	%R13,%R8

0x525e27 JE	525fdb

0x525e2d MOV	-0x38(%RBP),%R15

0x525e31 MOV	%R8,%R9

0x525e34 MOVQ	$0,(%RCX)

0x525e3b MOV	(%R15,%R8,8),%RAX

0x525e3f MOV	0x8(%R15,%R8,8),%RSI

0x525e44 JMP	525c70

0x525e49 MOV	-0x70(%RBP),%RDI

0x525e4d MOV	(%RDI,%R9,8),%R15

0x525e51 MOV	0x8(%RDI,%R9,8),%R9

0x525e56 CMP	%R15,%R9

0x525e59 JLE	526ba0

0x525e5f MOV	-0x60(%RBP),%RDI

0x525e63 LEA	(%RDI,%R15,8),%RAX

0x525e67 LEA	(%RDI,%R9,8),%R15

0x525e6b MOV	%R15,%R9

0x525e6e SUB	%RAX,%R9

0x525e71 SUB	$0x8,%R9

0x525e75 SHR	$0x3,%R9

0x525e79 INC	%R9

0x525e7c AND	$0x7,%R9D

0x525e80 JE	525f37

0x525e86 CMP	$0x1,%R9

0x525e8a JE	525f19

0x525e90 CMP	$0x2,%R9

0x525e94 JE	525f04

0x525e96 CMP	$0x3,%R9

0x525e9a JE	525ef0

0x525e9c CMP	$0x4,%R9

0x525ea0 JE	525edc

0x525ea2 CMP	$0x5,%R9

0x525ea6 JE	525ec7

0x525ea8 CMP	$0x6,%R9

0x525eac JNE	52645f

0x525eb2 VMOVSD	(%RAX),%XMM8

0x525eb6 ADD	$0x8,%RAX

0x525eba VANDPD	%XMM7,%XMM8,%XMM9

0x525ebe VADDSD	%XMM9,%XMM0,%XMM0

0x525ec3 VMOVSD	%XMM0,(%RCX)

0x525ec7 VMOVSD	(%RAX),%XMM10

0x525ecb ADD	$0x8,%RAX

0x525ecf VANDPD	%XMM7,%XMM10,%XMM13

0x525ed3 VADDSD	%XMM13,%XMM0,%XMM0

0x525ed8 VMOVSD	%XMM0,(%RCX)

0x525edc VMOVSD	(%RAX),%XMM6

0x525ee0 ADD	$0x8,%RAX

0x525ee4 VANDPD	%XMM7,%XMM6,%XMM4

0x525ee8 VADDSD	%XMM4,%XMM0,%XMM0

0x525eec VMOVSD	%XMM0,(%RCX)

0x525ef0 VMOVSD	(%RAX),%XMM5

0x525ef4 ADD	$0x8,%RAX

0x525ef8 VANDPD	%XMM7,%XMM5,%XMM2

0x525efc VADDSD	%XMM2,%XMM0,%XMM0

0x525f00 VMOVSD	%XMM0,(%RCX)

0x525f04 VMOVSD	(%RAX),%XMM15

0x525f08 ADD	$0x8,%RAX

0x525f0c VANDPD	%XMM7,%XMM15,%XMM14

0x525f10 VADDSD	%XMM14,%XMM0,%XMM0

0x525f15 VMOVSD	%XMM0,(%RCX)

0x525f19 VMOVSD	(%RAX),%XMM1

0x525f1d ADD	$0x8,%RAX

0x525f21 VANDPD	%XMM7,%XMM1,%XMM8

0x525f25 VADDSD	%XMM8,%XMM0,%XMM0

0x525f2a VMOVSD	%XMM0,(%RCX)

0x525f2e CMP	%R15,%RAX

0x525f31 JE	525e1d

  (2098) 0x525f37 VMOVSD	(%RAX),%XMM9

  (2098) 0x525f3b VANDPD	%XMM7,%XMM9,%XMM10

  (2098) 0x525f3f ADD	$0x40,%RAX

  (2098) 0x525f43 VADDSD	%XMM10,%XMM0,%XMM0

  (2098) 0x525f48 VMOVSD	%XMM0,(%RCX)

  (2098) 0x525f4c VMOVSD	-0x38(%RAX),%XMM13

  (2098) 0x525f51 VANDPD	%XMM7,%XMM13,%XMM6

  (2098) 0x525f55 VADDSD	%XMM6,%XMM0,%XMM4

  (2098) 0x525f59 VMOVSD	%XMM4,(%RCX)

  (2098) 0x525f5d VMOVSD	-0x30(%RAX),%XMM5

  (2098) 0x525f62 VANDPD	%XMM7,%XMM5,%XMM2

  (2098) 0x525f66 VADDSD	%XMM2,%XMM4,%XMM15

  (2098) 0x525f6a VMOVSD	%XMM15,(%RCX)

  (2098) 0x525f6e VMOVSD	-0x28(%RAX),%XMM14

  (2098) 0x525f73 VANDPD	%XMM7,%XMM14,%XMM1

  (2098) 0x525f77 VADDSD	%XMM1,%XMM15,%XMM8

  (2098) 0x525f7b VMOVSD	%XMM8,(%RCX)

  (2098) 0x525f7f VMOVSD	-0x20(%RAX),%XMM9

  (2098) 0x525f84 VANDPD	%XMM7,%XMM9,%XMM10

  (2098) 0x525f88 VADDSD	%XMM10,%XMM8,%XMM0

  (2098) 0x525f8d VMOVSD	%XMM0,(%RCX)

  (2098) 0x525f91 VMOVSD	-0x18(%RAX),%XMM13

  (2098) 0x525f96 VANDPD	%XMM7,%XMM13,%XMM6

  (2098) 0x525f9a VADDSD	%XMM6,%XMM0,%XMM4

  (2098) 0x525f9e VMOVSD	%XMM4,(%RCX)

  (2098) 0x525fa2 VMOVSD	-0x10(%RAX),%XMM5

  (2098) 0x525fa7 VANDPD	%XMM7,%XMM5,%XMM2

  (2098) 0x525fab VADDSD	%XMM2,%XMM4,%XMM15

  (2098) 0x525faf VMOVSD	%XMM15,(%RCX)

  (2098) 0x525fb3 VMOVSD	-0x8(%RAX),%XMM14

  (2098) 0x525fb8 VANDPD	%XMM7,%XMM14,%XMM1

  (2098) 0x525fbc VADDSD	%XMM1,%XMM15,%XMM0

  (2098) 0x525fc0 VMOVSD	%XMM0,(%RCX)

  (2098) 0x525fc4 CMP	%R15,%RAX

  (2098) 0x525fc7 JNE	525f37

0x525fcd JMP	525e1d

0x525fd2 VXORPD	%XMM0,%XMM0,%XMM0

0x525fd6 JMP	525e16

0x52645f VMOVSD	(%RAX),%XMM14

0x526463 VANDPD	%XMM7,%XMM14,%XMM1

0x526467 ADD	$0x8,%RAX

0x52646b VADDSD	%XMM1,%XMM0,%XMM0

0x52646f VMOVSD	%XMM0,(%RCX)

0x526473 JMP	525eb2

0x526ba0 INC	%R8

0x526ba3 ADD	$0x8,%RCX

0x526ba7 CMP	%R13,%R8

0x526baa JE	525fdb

0x526bb0 MOV	-0x38(%RBP),%RSI

0x526bb4 MOV	%R8,%R9

0x526bb7 MOVQ	$0,(%RCX)

0x526bbe MOV	(%RSI,%R8,8),%RAX

0x526bc2 MOV	0x8(%RSI,%R8,8),%RSI

0x526bc7 JMP	525c70

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
►96.84+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.16+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_ParCSRComputeL1NormsThre[...]	ams.c:3546	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1409	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.88
CQA speedup if FP arith vectorized	2.33
CQA speedup if fully vectorized	11.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.75
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	8.06
CQA cycles if fully vectorized	1.63
Front-end cycles	18.75
P0 cycles	12.83
P1 cycles	12.83
P2 cycles	12.83
P3 cycles	12.83
P4 cycles	12.83
P5 cycles	12.83
P6 cycles	10.25
P7 cycles	10.25
P8 cycles	10.25
P9 cycles	10.25
P10 cycles	6.75
P11 cycles	6.75
P12 cycles	6.75
P13 cycles	6.75
P14 cycles	7.00
P15 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	150.00
Nb uops	150.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	4.00
FLOP/cycle	0.69
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.49
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.78
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	14.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.72
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Metric	Value
CQA speedup if no scalar integer	1.88
CQA speedup if FP arith vectorized	2.33
CQA speedup if fully vectorized	11.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.75
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	8.06
CQA cycles if fully vectorized	1.63
Front-end cycles	18.75
P0 cycles	12.83
P1 cycles	12.83
P2 cycles	12.83
P3 cycles	12.83
P4 cycles	12.83
P5 cycles	12.83
P6 cycles	10.25
P7 cycles	10.25
P8 cycles	10.25
P9 cycles	10.25
P10 cycles	6.75
P11 cycles	6.75
P12 cycles	6.75
P13 cycles	6.75
P14 cycles	7.00
P15 cycles	7.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	150.00
Nb uops	150.00
Nb loads	25.00
Nb stores	16.00
Nb stack references	4.00
FLOP/cycle	0.69
Nb FLOP add-sub	13.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.49
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	20.78
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	47.06
Vector-efficiency ratio all	14.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	11.72
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 10.00 cycles (1.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.75 to 1.63 cycles (11.48x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	150
loop length	626
used x86 registers	10
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.83	12.83	12.83	12.83	12.83	12.83	10.25	10.25	10.25	10.25	6.75	6.75	6.75	6.75	7.00	7.00
cycles	12.83	12.83	12.83	12.83	12.83	12.83	10.25	10.25	10.25	10.25	6.75	6.75	6.75	6.75	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.75
Dispatch	12.83
Overall L1	18.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.75 cycles. At this rate:

4% of peak load performance is reached (10.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.75 to 12.83 cycles (1.46x speedup).

ASM code

In the binary file, the address of the loop is: 525c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 525fd2 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a52>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R12,%RAX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525d6e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d4e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d38 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d22 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d0b <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x478b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525cf4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525cdd <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x475d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM13,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525e16 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 525e49 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525fdb <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a5b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R15,%R8,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R15,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 525c70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI,%R9,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI,%R9,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 526ba0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x5620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R9,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525f37 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525f19 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4999>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525f04 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4984>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525ef0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525edc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x495c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525ec7 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4947>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 52645f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4edf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525e1d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x489d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 525e1d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x489d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 525e16 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD (%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VANDPD %XMM7,%XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 525eb2 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4932>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525fdb <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a5b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RSI,%R8,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 525c70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 13 FP arithmetical operations:

13: addition or subtraction

The binary loop is loading 200 bytes (25 double precision FP elements). The binary loop is storing 128 bytes (16 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	150
loop length	626
used x86 registers	10
used mmx registers	0
used xmm registers	14
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.83	12.83	12.83	12.83	12.83	12.83	10.25	10.25	10.25	10.25	6.75	6.75	6.75	6.75	7.00	7.00
cycles	12.83	12.83	12.83	12.83	12.83	12.83	10.25	10.25	10.25	10.25	6.75	6.75	6.75	6.75	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.75
Dispatch	12.83
Overall L1	18.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	28%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

Vector efficiency ratios

INT

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	14%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.75 cycles. At this rate:

4% of peak load performance is reached (10.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 525c70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMP %RAX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 525fd2 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a52>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R12,%RAX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525d6e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d4e <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d38 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47b8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d22 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x47a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525d0b <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x478b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525cf4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4774>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525cdd <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x475d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM10,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM13,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM6,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM4,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM5,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM11,%XMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM15,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525e16 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 525e49 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48c9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525fdb <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a5b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R15,%R8,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R15,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 525c70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x70(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI,%R9,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI,%R9,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R15,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 526ba0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x5620>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDI,%R15,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R9,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525f37 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x49b7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525f19 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4999>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525f04 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4984>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525ef0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525edc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x495c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525ec7 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4947>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 52645f <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4edf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD (%RAX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM8,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM9,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM10,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM13,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM4,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM2,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM14,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RAX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VANDPD %XMM7,%XMM1,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM8,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 525e1d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x489d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 525e1d <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x489d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 525e16 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD (%RAX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VANDPD %XMM7,%XMM14,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 525eb2 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4932>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 525fdb <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4a5b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RSI,%R8,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 525c70 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x46f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code