OV - exec - Loop 1898

	Loop Id: 1898	Module: exec	Source: par_strength.c:2011-2048	Coverage: 0.08%

0x50c5d0 MOV	(%R8,%R10,8),%RAX

0x50c5d4 CMPQ	$0,(%R13,%RAX,8)

0x50c5da LEA	(,%RAX,8),%RBX

0x50c5e2 JLE	50c60d

0x50c5e4 MOV	(%R9,%RBX,1),%R14

0x50c5e8 MOV	-0x60(%RBP),%R11

0x50c5ec MOV	-0x58(%RBP),%RAX

0x50c5f0 LEA	(%R11,%R14,8),%R11

0x50c5f4 CMP	%RAX,(%R11)

0x50c5f7 JGE	50c60d

0x50c5f9 MOV	-0x40(%RBP),%RAX

0x50c5fd MOV	%RAX,(%R11)

0x50c600 VMOVQ	%XMM8,%R11

0x50c605 MOV	%R14,(%R11,%RAX,8)

0x50c609 INCQ	-0x40(%RBP)

0x50c60d MOV	-0x90(%RBP),%R11

0x50c614 LEA	0x8(%RBX),%R14

0x50c618 MOV	%R14,-0x68(%RBP)

0x50c61c MOV	(%R11,%RBX,1),%RAX

0x50c620 LEA	0x8(%R11,%RBX,1),%R11

0x50c625 MOV	(%R11),%R14

0x50c628 CMP	%RAX,%R14

0x50c62b JLE	50c6a8

0x50c62d MOV	%R10,-0x78(%RBP)

0x50c631 VMOVQ	%RDX,%XMM4

0x50c636 MOV	%RDI,%R10

0x50c639 MOV	%R14,%RDI

0x50c63c MOV	%RSI,-0x70(%RBP)

  (1900) 0x50c640 MOV	(%R8,%RAX,8),%RDX

  (1900) 0x50c644 CMPQ	$0,(%R13,%RDX,8)

  (1900) 0x50c64a LEA	(,%RDX,8),%RSI

  (1900) 0x50c652 JLE	50c690

  (1900) 0x50c654 MOV	(%R9,%RSI,1),%R14

  (1900) 0x50c658 CMP	%R14,%R10

  (1900) 0x50c65b JE	50c690

  (1900) 0x50c65d MOV	-0x60(%RBP),%RDX

  (1900) 0x50c661 LEA	(%RDX,%R14,8),%RSI

  (1900) 0x50c665 MOV	-0x58(%RBP),%RDX

  (1900) 0x50c669 CMP	%RDX,(%RSI)

  (1900) 0x50c66c JGE	50c690

  (1900) 0x50c66e MOV	-0x40(%RBP),%RDI

  (1900) 0x50c672 MOV	%RDI,(%RSI)

  (1900) 0x50c675 VMOVQ	%XMM8,%RSI

  (1900) 0x50c67a MOV	%R14,(%RSI,%RDI,8)

  (1900) 0x50c67e MOV	(%R11),%RDI

  (1900) 0x50c681 INCQ	-0x40(%RBP)

  (1900) 0x50c685 NOPW	%CS:(%RAX,%RAX,1)

  (1900) 0x50c690 INC	%RAX

  (1900) 0x50c693 CMP	%RDI,%RAX

  (1900) 0x50c696 JL	50c640

0x50c698 MOV	%R10,%RDI

0x50c69b MOV	-0x70(%RBP),%RSI

0x50c69f MOV	-0x78(%RBP),%R10

0x50c6a3 VMOVQ	%XMM4,%RDX

0x50c6a8 MOV	-0x88(%RBP),%R11

0x50c6af MOV	(%R11,%RBX,1),%RAX

0x50c6b3 MOV	-0x68(%RBP),%RBX

0x50c6b7 ADD	%R11,%RBX

0x50c6ba MOV	(%RBX),%R14

0x50c6bd CMP	%RAX,%R14

0x50c6c0 JLE	50c716

0x50c6c2 MOV	%R10,-0x68(%RBP)

0x50c6c6 MOV	%RDI,%R10

0x50c6c9 MOV	%RBX,%RDI

0x50c6cc NOPL	(%RAX)

  (1899) 0x50c6d0 MOV	(%RDX,%RAX,8),%RBX

  (1899) 0x50c6d4 CMPQ	$0,(%R15,%RBX,8)

  (1899) 0x50c6d9 LEA	(,%RBX,8),%R11

  (1899) 0x50c6e1 JLE	50c707

  (1899) 0x50c6e3 MOV	(%RCX,%R11,1),%RBX

  (1899) 0x50c6e7 LEA	(%R12,%RBX,8),%R11

  (1899) 0x50c6eb CMP	%RSI,(%R11)

  (1899) 0x50c6ee JGE	50c707

  (1899) 0x50c6f0 MOV	-0x38(%RBP),%R14

  (1899) 0x50c6f4 MOV	%R14,(%R11)

  (1899) 0x50c6f7 VMOVQ	%XMM3,%R11

  (1899) 0x50c6fc MOV	%RBX,(%R11,%R14,8)

  (1899) 0x50c700 MOV	(%RDI),%R14

  (1899) 0x50c703 INCQ	-0x38(%RBP)

  (1899) 0x50c707 INC	%RAX

  (1899) 0x50c70a CMP	%R14,%RAX

  (1899) 0x50c70d JL	50c6d0

0x50c70f MOV	%R10,%RDI

0x50c712 MOV	-0x68(%RBP),%R10

0x50c716 VMOVQ	%XMM5,%RAX

0x50c71b INC	%R10

0x50c71e CMP	%R10,(%RAX)

0x50c721 JG	50c5d0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048

--------------------------------------------------------------------------------

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module
►97.42+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.58+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_BoomerAMGCreate2ndS	par_strength.c:2238	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:619	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.71
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source	par_strength.c:2011-2011,par_strength.c:2014-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.81
Front-end cycles	6.00
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	2.83
P3 cycles	2.83
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	6.50
P7 cycles	6.50
P8 cycles	6.50
P9 cycles	6.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	20.00
Nb stores	7.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	3.71
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source	par_strength.c:2011-2011,par_strength.c:2014-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.75
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	0.81
Front-end cycles	6.00
P0 cycles	2.83
P1 cycles	2.83
P2 cycles	2.83
P3 cycles	2.83
P4 cycles	2.83
P5 cycles	2.83
P6 cycles	6.50
P7 cycles	6.50
P8 cycles	6.50
P9 cycles	6.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	48.00
Nb loads	20.00
Nb stores	7.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	152.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011,2014-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 60 paths individually, rerun with max-paths=60
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 60 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.75 cycles (3.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 0.81 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.50 to 6.00 cycles (1.08x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2024

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	49
nb uops	48
loop length	192
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	2.83	2.83	2.83	2.83	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.50	1.50
cycles	2.83	2.83	2.83	2.83	2.83	2.83	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

9% of peak load performance is reached (23.38 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 50c5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R8,%R10,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $0,(%R13,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
LEA (,%RAX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
JLE 50c60d <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x122d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9,%RBX,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x60(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R11,%R14,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,(%R11)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 50c60d <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x122d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,(%R11)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,%R11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
INCQ -0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%RBX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%R11,%RBX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%R11,%RBX,1),%R11	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV (%R11),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 50c6a8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %RDX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R11,%RBX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R11,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 50c716 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1336>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x68(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM5,%RAX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 50c5d0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x11f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_BoomerAMGCreate2ndS._omp_fn.7
Source file and lines	par_strength.c:2011-2048
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 60 paths individually, rerun with max-paths=60
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.75 cycles (3.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 0.81 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 6.50 to 6.00 cycles (1.08x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2024

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 152 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	49
nb uops	48
loop length	192
used x86 registers	12
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.83	2.83	2.83	2.83	2.83	2.83	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.50	1.50
cycles	2.83	2.83	2.83	2.83	2.83	2.83	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	6.50
Overall L1	6.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

9% of peak load performance is reached (23.38 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 50c5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV (%R8,%R10,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $0,(%R13,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
LEA (,%RAX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
JLE 50c60d <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x122d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9,%RBX,1),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x60(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA (%R11,%R14,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP %RAX,(%R11)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 50c60d <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x122d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,(%R11)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM8,%R11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R14,(%R11,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
INCQ -0x40(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0x90(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%RBX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV (%R11,%RBX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x8(%R11,%RBX,1),%R11	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	2	0.50	N/A
MOV (%R11),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 50c6a8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %RDX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R11,%RBX,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x68(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD %R11,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV (%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 50c716 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1336>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R10,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x68(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVQ %XMM5,%RAX	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JG 50c5d0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x11f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code