OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.27% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x599750 PUSH	%RBP

0x599751 MOV	%RSP,%RBP

0x599754 PUSH	%R15

0x599756 PUSH	%R14

0x599758 PUSH	%R13

0x59975a PUSH	%R12

0x59975c PUSH	%RBX

0x59975d SUB	$0x38,%RSP

0x599761 MOV	0x28(%RDI),%RDX

0x599765 MOV	0x10(%RDI),%R8

0x599769 MOV	0x20(%RDI),%R10

0x59976d MOV	0x30(%RDI),%RAX

0x599771 MOV	0x18(%RDI),%R14

0x599775 MOV	0x40(%RDI),%R15

0x599779 MOV	0x38(%RDI),%RBX

0x59977d MOV	0x8(%RDI),%R13

0x599781 MOV	(%RDI),%RDI

0x599784 MOV	%RDX,-0x60(%RBP)

0x599788 MOV	%R8,-0x50(%RBP)

0x59978c MOV	%R10,-0x58(%RBP)

0x599790 MOV	%RAX,-0x40(%RBP)

0x599794 MOV	%RDI,-0x48(%RBP)

0x599798 CALL	5a9ce0 <hypre_GetThreadNum>

0x59979d MOV	%RAX,%R12

0x5997a0 CALL	4110b0 <omp_get_num_threads@plt>

0x5997a5 CLTQ

0x5997a7 MOV	%RAX,-0x38(%RBP)

0x5997ab CALL	4111f0 <omp_get_thread_num@plt>

0x5997b0 MOV	-0x48(%RBP),%R11

0x5997b4 MOV	-0x50(%RBP),%R8

0x5997b8 MOVSXD	%EAX,%R9

0x5997bb MOV	%R14,%RAX

0x5997be MOV	-0x58(%RBP),%RSI

0x5997c2 CQTO

0x5997c4 IDIVQ	-0x38(%RBP)

0x5997c8 CMP	%RDX,%R9

0x5997cb MOV	%RAX,%RCX

0x5997ce JL	599c1a

0x5997d4 MOV	%RCX,%R10

0x5997d7 IMUL	%R9,%R10

0x5997db ADD	%R10,%RDX

0x5997de ADD	%RDX,%RCX

0x5997e1 CMP	%RCX,%RDX

0x5997e4 JGE	599a70

0x5997ea MOV	-0x40(%RBP),%R14

0x5997ee LEA	(%RSI,%RCX,8),%RDI

0x5997f2 SAL	$0x3,%RDX

0x5997f6 ADD	%RDX,%R13

0x5997f9 ADD	%RSI,%RDX

0x5997fc IMUL	%R14,%R12

(3145) 0x599800 MOV	(%R13),%RAX

(3145) 0x599804 MOV	0x8(%R13),%RSI

(3145) 0x599808 CMP	%RSI,%RAX

(3145) 0x59980b JGE	599a5f

(3145) 0x599811 MOV	%RSI,%RCX

(3145) 0x599814 SUB	%RAX,%RCX

(3145) 0x599817 AND	$0x7,%ECX

(3145) 0x59981a JE	59994a

(3145) 0x599820 CMP	$0x1,%RCX

(3145) 0x599824 JE	59991e

(3145) 0x59982a CMP	$0x2,%RCX

(3145) 0x59982e JE	5998fd

(3145) 0x599834 CMP	$0x3,%RCX

(3145) 0x599838 JE	5998da

(3145) 0x59983e CMP	$0x4,%RCX

(3145) 0x599842 JE	5998b7

(3145) 0x599844 CMP	$0x5,%RCX

(3145) 0x599848 JE	599896

(3145) 0x59984a CMP	$0x6,%RCX

(3145) 0x59984e JE	599873

(3145) 0x599850 MOV	(%R8,%RAX,8),%R10

(3145) 0x599854 VMOVSD	(%R11,%RAX,8),%XMM0

(3145) 0x59985a INC	%RAX

(3145) 0x59985d ADD	%R12,%R10

(3145) 0x599860 LEA	(%RBX,%R10,8),%R14

(3145) 0x599864 VMOVSD	(%R14),%XMM7

(3145) 0x599869 VFMADD132SD	(%RDX),%XMM7,%XMM0

(3145) 0x59986e VMOVSD	%XMM0,(%R14)

(3145) 0x599873 MOV	(%R8,%RAX,8),%RCX

(3145) 0x599877 VMOVSD	(%R11,%RAX,8),%XMM1

(3145) 0x59987d INC	%RAX

(3145) 0x599880 ADD	%R12,%RCX

(3145) 0x599883 LEA	(%RBX,%RCX,8),%R10

(3145) 0x599887 VMOVSD	(%R10),%XMM2

(3145) 0x59988c VFMADD132SD	(%RDX),%XMM2,%XMM1

(3145) 0x599891 VMOVSD	%XMM1,(%R10)

(3145) 0x599896 MOV	(%R8,%RAX,8),%R14

(3145) 0x59989a VMOVSD	(%R11,%RAX,8),%XMM3

(3145) 0x5998a0 INC	%RAX

(3145) 0x5998a3 ADD	%R12,%R14

(3145) 0x5998a6 LEA	(%RBX,%R14,8),%RCX

(3145) 0x5998aa VMOVSD	(%RCX),%XMM6

(3145) 0x5998ae VFMADD132SD	(%RDX),%XMM6,%XMM3

(3145) 0x5998b3 VMOVSD	%XMM3,(%RCX)

(3145) 0x5998b7 MOV	(%R8,%RAX,8),%R10

(3145) 0x5998bb VMOVSD	(%R11,%RAX,8),%XMM4

(3145) 0x5998c1 INC	%RAX

(3145) 0x5998c4 ADD	%R12,%R10

(3145) 0x5998c7 LEA	(%RBX,%R10,8),%R14

(3145) 0x5998cb VMOVSD	(%R14),%XMM5

(3145) 0x5998d0 VFMADD132SD	(%RDX),%XMM5,%XMM4

(3145) 0x5998d5 VMOVSD	%XMM4,(%R14)

(3145) 0x5998da MOV	(%R8,%RAX,8),%RCX

(3145) 0x5998de VMOVSD	(%R11,%RAX,8),%XMM8

(3145) 0x5998e4 INC	%RAX

(3145) 0x5998e7 ADD	%R12,%RCX

(3145) 0x5998ea LEA	(%RBX,%RCX,8),%R10

(3145) 0x5998ee VMOVSD	(%R10),%XMM9

(3145) 0x5998f3 VFMADD132SD	(%RDX),%XMM9,%XMM8

(3145) 0x5998f8 VMOVSD	%XMM8,(%R10)

(3145) 0x5998fd MOV	(%R8,%RAX,8),%R14

(3145) 0x599901 VMOVSD	(%R11,%RAX,8),%XMM10

(3145) 0x599907 INC	%RAX

(3145) 0x59990a ADD	%R12,%R14

(3145) 0x59990d LEA	(%RBX,%R14,8),%RCX

(3145) 0x599911 VMOVSD	(%RCX),%XMM11

(3145) 0x599915 VFMADD132SD	(%RDX),%XMM11,%XMM10

(3145) 0x59991a VMOVSD	%XMM10,(%RCX)

(3145) 0x59991e MOV	(%R8,%RAX,8),%R10

(3145) 0x599922 VMOVSD	(%R11,%RAX,8),%XMM12

(3145) 0x599928 INC	%RAX

(3145) 0x59992b ADD	%R12,%R10

(3145) 0x59992e LEA	(%RBX,%R10,8),%R14

(3145) 0x599932 VMOVSD	(%R14),%XMM13

(3145) 0x599937 VFMADD132SD	(%RDX),%XMM13,%XMM12

(3145) 0x59993c VMOVSD	%XMM12,(%R14)

(3145) 0x599941 CMP	%RSI,%RAX

(3145) 0x599944 JE	599a5f

  (3146) 0x59994a MOV	(%R8,%RAX,8),%RCX

  (3146) 0x59994e VMOVSD	(%R11,%RAX,8),%XMM14

  (3146) 0x599954 MOV	0x8(%R8,%RAX,8),%R14

  (3146) 0x599959 ADD	%R12,%RCX

  (3146) 0x59995c ADD	%R12,%R14

  (3146) 0x59995f LEA	(%RBX,%RCX,8),%R10

  (3146) 0x599963 LEA	(%RBX,%R14,8),%RCX

  (3146) 0x599967 VMOVSD	(%R10),%XMM15

  (3146) 0x59996c VFMADD132SD	(%RDX),%XMM15,%XMM14

  (3146) 0x599971 VMOVSD	%XMM14,(%R10)

  (3146) 0x599976 MOV	0x10(%R8,%RAX,8),%R10

  (3146) 0x59997b VMOVSD	0x8(%R11,%RAX,8),%XMM0

  (3146) 0x599982 VMOVSD	(%RCX),%XMM7

  (3146) 0x599986 VFMADD132SD	(%RDX),%XMM7,%XMM0

  (3146) 0x59998b VMOVSD	%XMM0,(%RCX)

  (3146) 0x59998f MOV	0x18(%R8,%RAX,8),%RCX

  (3146) 0x599994 VMOVSD	0x10(%R11,%RAX,8),%XMM1

  (3146) 0x59999b ADD	%R12,%R10

  (3146) 0x59999e LEA	(%RBX,%R10,8),%R14

  (3146) 0x5999a2 VMOVSD	(%R14),%XMM2

  (3146) 0x5999a7 VFMADD132SD	(%RDX),%XMM2,%XMM1

  (3146) 0x5999ac VMOVSD	%XMM1,(%R14)

  (3146) 0x5999b1 MOV	0x20(%R8,%RAX,8),%R14

  (3146) 0x5999b6 ADD	%R12,%RCX

  (3146) 0x5999b9 VMOVSD	0x18(%R11,%RAX,8),%XMM3

  (3146) 0x5999c0 LEA	(%RBX,%RCX,8),%R10

  (3146) 0x5999c4 VMOVSD	(%R10),%XMM6

  (3146) 0x5999c9 VFMADD132SD	(%RDX),%XMM6,%XMM3

  (3146) 0x5999ce VMOVSD	%XMM3,(%R10)

  (3146) 0x5999d3 MOV	0x28(%R8,%RAX,8),%R10

  (3146) 0x5999d8 VMOVSD	0x20(%R11,%RAX,8),%XMM4

  (3146) 0x5999df ADD	%R12,%R14

  (3146) 0x5999e2 LEA	(%RBX,%R14,8),%RCX

  (3146) 0x5999e6 VMOVSD	(%RCX),%XMM5

  (3146) 0x5999ea VFMADD132SD	(%RDX),%XMM5,%XMM4

  (3146) 0x5999ef VMOVSD	%XMM4,(%RCX)

  (3146) 0x5999f3 MOV	0x30(%R8,%RAX,8),%RCX

  (3146) 0x5999f8 ADD	%R12,%R10

  (3146) 0x5999fb VMOVSD	0x28(%R11,%RAX,8),%XMM8

  (3146) 0x599a02 LEA	(%RBX,%R10,8),%R14

  (3146) 0x599a06 VMOVSD	(%R14),%XMM9

  (3146) 0x599a0b VFMADD132SD	(%RDX),%XMM9,%XMM8

  (3146) 0x599a10 VMOVSD	%XMM8,(%R14)

  (3146) 0x599a15 VMOVSD	0x30(%R11,%RAX,8),%XMM10

  (3146) 0x599a1c ADD	%R12,%RCX

  (3146) 0x599a1f LEA	(%RBX,%RCX,8),%R10

  (3146) 0x599a23 VMOVSD	(%R10),%XMM11

  (3146) 0x599a28 MOV	0x38(%R8,%RAX,8),%R14

  (3146) 0x599a2d VFMADD132SD	(%RDX),%XMM11,%XMM10

  (3146) 0x599a32 VMOVSD	%XMM10,(%R10)

  (3146) 0x599a37 VMOVSD	0x38(%R11,%RAX,8),%XMM12

  (3146) 0x599a3e ADD	$0x8,%RAX

  (3146) 0x599a42 ADD	%R12,%R14

  (3146) 0x599a45 LEA	(%RBX,%R14,8),%RCX

  (3146) 0x599a49 VMOVSD	(%RCX),%XMM13

  (3146) 0x599a4d VFMADD132SD	(%RDX),%XMM13,%XMM12

  (3146) 0x599a52 VMOVSD	%XMM12,(%RCX)

  (3146) 0x599a56 CMP	%RSI,%RAX

  (3146) 0x599a59 JNE	59994a

(3145) 0x599a5f ADD	$0x8,%RDX

(3145) 0x599a63 ADD	$0x8,%R13

(3145) 0x599a67 CMP	%RDX,%RDI

(3145) 0x599a6a JNE	599800

0x599a70 MOV	%R9,-0x48(%RBP)

0x599a74 CALL	411290 <GOMP_barrier@plt>

0x599a79 MOV	-0x40(%RBP),%RAX

0x599a7d MOV	-0x48(%RBP),%R13

0x599a81 CQTO

0x599a83 IDIVQ	-0x38(%RBP)

0x599a87 CMP	%RDX,%R13

0x599a8a JL	599c10

0x599a90 IMUL	%RAX,%R13

0x599a94 ADD	%R13,%RDX

0x599a97 ADD	%RDX,%RAX

0x599a9a CMP	%RAX,%RDX

0x599a9d JGE	599bfd

0x599aa3 TEST	%R15,%R15

0x599aa6 JLE	599bfd

0x599aac MOV	-0x60(%RBP),%R11

0x599ab0 LEA	(,%RDX,8),%R12

0x599ab8 ADD	%R12,%R11

0x599abb ADD	%RBX,%R12

0x599abe MOV	-0x40(%RBP),%RBX

0x599ac2 SAL	$0x3,%RBX

0x599ac6 NOPW	%CS:(%RAX,%RAX,1)

(3144) 0x599ad0 VMOVSD	(%R11),%XMM14

(3144) 0x599ad5 MOV	%R15,%R9

(3144) 0x599ad8 XOR	%R8D,%R8D

(3144) 0x599adb MOV	%R12,%RDI

(3144) 0x599ade AND	$0x7,%R9D

(3144) 0x599ae2 JE	599b80

(3144) 0x599ae8 CMP	$0x1,%R9

(3144) 0x599aec JE	599b6c

(3144) 0x599aee CMP	$0x2,%R9

(3144) 0x599af2 JE	599b5d

(3144) 0x599af4 CMP	$0x3,%R9

(3144) 0x599af8 JE	599b4e

(3144) 0x599afa CMP	$0x4,%R9

(3144) 0x599afe JE	599b3f

(3144) 0x599b00 CMP	$0x5,%R9

(3144) 0x599b04 JE	599b30

(3144) 0x599b06 CMP	$0x6,%R9

(3144) 0x599b0a JE	599b21

(3144) 0x599b0c MOV	$0x1,%R8D

(3144) 0x599b12 LEA	(%R12,%RBX,1),%RDI

(3144) 0x599b16 VADDSD	(%R12),%XMM14,%XMM14

(3144) 0x599b1c VMOVSD	%XMM14,(%R11)

(3144) 0x599b21 VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b25 INC	%R8

(3144) 0x599b28 ADD	%RBX,%RDI

(3144) 0x599b2b VMOVSD	%XMM14,(%R11)

(3144) 0x599b30 VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b34 INC	%R8

(3144) 0x599b37 ADD	%RBX,%RDI

(3144) 0x599b3a VMOVSD	%XMM14,(%R11)

(3144) 0x599b3f VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b43 INC	%R8

(3144) 0x599b46 ADD	%RBX,%RDI

(3144) 0x599b49 VMOVSD	%XMM14,(%R11)

(3144) 0x599b4e VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b52 INC	%R8

(3144) 0x599b55 ADD	%RBX,%RDI

(3144) 0x599b58 VMOVSD	%XMM14,(%R11)

(3144) 0x599b5d VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b61 INC	%R8

(3144) 0x599b64 ADD	%RBX,%RDI

(3144) 0x599b67 VMOVSD	%XMM14,(%R11)

(3144) 0x599b6c INC	%R8

(3144) 0x599b6f VADDSD	(%RDI),%XMM14,%XMM14

(3144) 0x599b73 ADD	%RBX,%RDI

(3144) 0x599b76 VMOVSD	%XMM14,(%R11)

(3144) 0x599b7b CMP	%R8,%R15

(3144) 0x599b7e JE	599be9

  (3143) 0x599b80 VADDSD	(%RDI),%XMM14,%XMM15

  (3143) 0x599b84 ADD	%RBX,%RDI

  (3143) 0x599b87 VMOVSD	%XMM15,(%R11)

  (3143) 0x599b8c ADD	$0x8,%R8

  (3143) 0x599b90 VADDSD	(%RDI),%XMM15,%XMM0

  (3143) 0x599b94 ADD	%RBX,%RDI

  (3143) 0x599b97 VMOVSD	%XMM0,(%R11)

  (3143) 0x599b9c VADDSD	(%RDI),%XMM0,%XMM7

  (3143) 0x599ba0 ADD	%RBX,%RDI

  (3143) 0x599ba3 VMOVSD	%XMM7,(%R11)

  (3143) 0x599ba8 VADDSD	(%RDI),%XMM7,%XMM1

  (3143) 0x599bac ADD	%RBX,%RDI

  (3143) 0x599baf VMOVSD	%XMM1,(%R11)

  (3143) 0x599bb4 VADDSD	(%RDI),%XMM1,%XMM2

  (3143) 0x599bb8 ADD	%RBX,%RDI

  (3143) 0x599bbb VMOVSD	%XMM2,(%R11)

  (3143) 0x599bc0 VADDSD	(%RDI),%XMM2,%XMM3

  (3143) 0x599bc4 ADD	%RBX,%RDI

  (3143) 0x599bc7 VMOVSD	%XMM3,(%R11)

  (3143) 0x599bcc VADDSD	(%RDI),%XMM3,%XMM6

  (3143) 0x599bd0 ADD	%RBX,%RDI

  (3143) 0x599bd3 VMOVSD	%XMM6,(%R11)

  (3143) 0x599bd8 VADDSD	(%RDI),%XMM6,%XMM14

  (3143) 0x599bdc ADD	%RBX,%RDI

  (3143) 0x599bdf VMOVSD	%XMM14,(%R11)

  (3143) 0x599be4 CMP	%R8,%R15

  (3143) 0x599be7 JNE	599b80

(3144) 0x599be9 INC	%RDX

(3144) 0x599bec ADD	$0x8,%R11

(3144) 0x599bf0 ADD	$0x8,%R12

(3144) 0x599bf4 CMP	%RDX,%RAX

(3144) 0x599bf7 JNE	599ad0

0x599bfd ADD	$0x38,%RSP

0x599c01 POP	%RBX

0x599c02 POP	%R12

0x599c04 POP	%R13

0x599c06 POP	%R14

0x599c08 POP	%R15

0x599c0a POP	%RBP

0x599c0b JMP	411290

0x599c10 INC	%RAX

0x599c13 XOR	%EDX,%EDX

0x599c15 JMP	599a90

0x599c1a INC	%RCX

0x599c1d XOR	%EDX,%EDX

0x599c1f JMP	5997d4

0x599c24 NOPW	%CS:(%RAX,%RAX,1)

0x599c2f NOP

Coverage (%)	Name	Source Location	Module
►96.67+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.45+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecT	csr_matvec.c:554	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:432	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 24.00 to 3.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 11.00 cycles (2.18x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.00 to 10.75 cycles (2.23x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

GOMP_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
CQTO: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	88
nb uops	88
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.83	6.83	6.83	6.83	6.83	6.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.83	6.83	6.83	6.83	6.83	6.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

14.00-24.00

Cycles summary

Front-end	11.00
Dispatch	7.50
DIV/SQRT	14.00-24.00
Overall L1	14.00-24.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 599750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x28(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x20(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CLTQ																				scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CQTO																				scal (12.5%)
IDIVQ -0x38(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 599c1a <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL %R9,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 599a70 <hypre_CSRMatrixMatvecT._omp_fn.3+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (%RSI,%RCX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x48(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CQTO																				scal (12.5%)
IDIVQ -0x38(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 599c10 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 599bfd <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R15,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 599bfd <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (,%RDX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RBX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SAL $0x3,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 411290 <GOMP_barrier@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 599a90 <hypre_CSRMatrixMatvecT._omp_fn.3+0x340>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 5997d4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.00 to 10.75 cycles (2.23x speedup).

CALL instructions

Detected function call instructions.

Details

GOMP_barrier@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:557
omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
CQTO: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:558
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:564

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 56 bytes.

General properties

nb instructions	88
nb uops	88
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.00 cycles
front end	11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.83	6.83	6.83	6.83	6.83	6.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.83	6.83	6.83	6.83	6.83	6.83	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

14.00-24.00

Cycles summary

Front-end	11.00
Dispatch	7.50
DIV/SQRT	14.00-24.00
Overall L1	14.00-24.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 599750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x28(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x20(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CLTQ																				scal (12.5%)
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CQTO																				scal (12.5%)
IDIVQ -0x38(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JL 599c1a <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
IMUL %R9,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 599a70 <hypre_CSRMatrixMatvecT._omp_fn.3+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (%RSI,%RCX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R14,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 411290 <GOMP_barrier@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x48(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CQTO																				scal (12.5%)
IDIVQ -0x38(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-22	7-12	scal (12.5%)
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 599c10 <hypre_CSRMatrixMatvecT._omp_fn.3+0x4c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%R13	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %R13,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 599bfd <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R15,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 599bfd <hypre_CSRMatrixMatvecT._omp_fn.3+0x4ad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (,%RDX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %R12,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RBX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SAL $0x3,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 411290 <GOMP_barrier@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 599a90 <hypre_CSRMatrixMatvecT._omp_fn.3+0x340>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 5997d4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x84>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	1.27	0.66
▼Loop 3145 - csr_matvec.c:564-567 - exec–	1.19	0.57
○Loop 3146 - csr_matvec.c:564-567 - exec	0.04	0.02
▼Loop 3144 - csr_matvec.c:577-579 - exec–	0.00	0.00
○Loop 3143 - csr_matvec.c:577-579 - exec	0.05	0.02

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

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Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code