OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.06% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

191:             if ( num_vectors==1 )

192:             {

193:                tempx = 0;

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x5951a0 PUSH	%RBP

0x5951a1 MOV	%RSP,%RBP

0x5951a4 PUSH	%R15

0x5951a6 PUSH	%R14

0x5951a8 PUSH	%R13

0x5951aa PUSH	%R12

0x5951ac PUSH	%RBX

0x5951ad MOV	%RDI,%RBX

0x5951b0 AND	$-0x20,%RSP

0x5951b4 SUB	$0x40,%RSP

0x5951b8 CALL	4110b0 <omp_get_num_threads@plt>

0x5951bd MOV	%EAX,%R12D

0x5951c0 CALL	4111f0 <omp_get_thread_num@plt>

0x5951c5 MOVSXD	%EAX,%RCX

0x5951c8 MOV	0x20(%RBX),%RAX

0x5951cc MOVSXD	%R12D,%RSI

0x5951cf CQTO

0x5951d1 IDIV	%RSI

0x5951d4 CMP	%RDX,%RCX

0x5951d7 JL	595601

0x5951dd IMUL	%RAX,%RCX

0x5951e1 ADD	%RDX,%RCX

0x5951e4 LEA	(%RAX,%RCX,1),%R9

0x5951e8 CMP	%R9,%RCX

0x5951eb JGE	5955de

0x5951f1 MOV	0x38(%RBX),%RDI

0x5951f5 MOV	0x18(%RBX),%R10

0x5951f9 MOV	0x50(%RBX),%R11

0x5951fd VMOVQ	0x58(%RBX),%XMM4

0x595202 VMOVQ	0x40(%RBX),%XMM8

0x595207 VMOVQ	0x30(%RBX),%XMM2

0x59520c MOV	0x48(%RBX),%R8

0x595210 MOV	0x28(%RBX),%R15

0x595214 VMOVQ	0x8(%RBX),%XMM1

0x595219 MOV	0x10(%RBX),%R14

0x59521d MOV	(%RBX),%R12

0x595220 LEA	(%R10,%RCX,8),%R13

0x595224 MOV	%RDI,0x38(%RSP)

0x595229 CMP	$0x1,%R11

0x59522d JNE	59560b

0x595233 CMPQ	$0x1,0x38(%RSP)

0x595239 LEA	(,%R8,8),%RDI

0x595241 LEA	(%R10,%R9,8),%R11

0x595245 MOV	%R13,%RCX

0x595248 MOV	%RDI,0x30(%RSP)

0x59524d KXNORB	%K0,%K0,%K0

0x595251 MOV	(%R13),%RDI

0x595255 MOV	%R11,0x10(%RSP)

0x59525a JE	595cc7

0x595260 CMPQ	$0,0x38(%RSP)

0x595266 JLE	595fb9

0x59526c VMOVDQA	%XMM4,%XMM3

0x595270 VMOVQ	%R15,%XMM7

0x595275 MOV	%RDI,%RDX

0x595278 VMOVQ	%R14,%XMM14

0x59527d VMOVDQA	%XMM1,%XMM15

0x595281 VMOVQ	%R12,%XMM13

(3104) 0x595286 LEA	(,%RDX,8),%RSI

(3104) 0x59528e VMOVQ	%XMM15,%R8

(3104) 0x595293 VMOVQ	%XMM8,%R9

(3104) 0x595298 MOV	%RCX,0x8(%RSP)

(3104) 0x59529d MOV	0x8(%R8,%RSI,1),%R11

(3104) 0x5952a2 MOV	(%R8,%RSI,1),%R14

(3104) 0x5952a6 IMUL	%R9,%RDX

(3104) 0x5952aa VMOVQ	%XMM2,%RAX

(3104) 0x5952af VMOVQ	%XMM13,%RBX

(3104) 0x5952b4 XOR	%R8D,%R8D

(3104) 0x5952b7 VMOVQ	%XMM14,%R13

(3104) 0x5952bc XOR	%ESI,%ESI

(3104) 0x5952be LEA	(%RAX,%RDX,8),%RDI

(3104) 0x5952c2 MOV	%R11,%R10

(3104) 0x5952c5 LEA	(,%R14,8),%RDX

(3104) 0x5952cd MOV	%R14,%RCX

(3104) 0x5952d0 SUB	%R14,%R10

(3104) 0x5952d3 LEA	(%RBX,%RDX,1),%R15

(3104) 0x5952d7 ADD	%R13,%RDX

(3104) 0x5952da MOV	%R10,%R9

(3104) 0x5952dd MOV	%R10,%RAX

(3104) 0x5952e0 LEA	-0x1(%R10),%R12

(3104) 0x5952e4 AND	$0x3,%R10D

(3104) 0x5952e8 SHR	$0x2,%R9

(3104) 0x5952ec MOV	%R12,0x28(%RSP)

(3104) 0x5952f1 MOV	%R10,0x18(%RSP)

(3104) 0x5952f6 SAL	$0x5,%R9

(3104) 0x5952fa AND	$-0x4,%RAX

(3104) 0x5952fe MOV	%R9,%R10

(3104) 0x595301 MOV	%RBX,%R12

(3104) 0x595304 MOV	%R8,%R9

(3104) 0x595307 ADD	%R14,%RAX

(3104) 0x59530a MOV	%RDI,%R8

(3104) 0x59530d MOV	%R15,%R14

(3104) 0x595310 MOV	%RSI,%RDI

(3104) 0x595313 MOV	%RAX,0x20(%RSP)

(3104) 0x595318 VMOVQ	%XMM7,%RAX

(3104) 0x59531d NOPL	(%RAX)

  (3103) 0x595320 CMP	%RCX,%R11

  (3103) 0x595323 JLE	5955ed

  (3103) 0x595329 CMPQ	$0x2,0x28(%RSP)

  (3103) 0x59532f JBE	5955f4

  (3103) 0x595335 LEA	-0x20(%R10),%RSI

  (3103) 0x595339 XOR	%EBX,%EBX

  (3103) 0x59533b LEA	(%RAX,%RDI,8),%R15

  (3103) 0x59533f VXORPD	%XMM0,%XMM0,%XMM0

  (3103) 0x595343 SHR	$0x5,%RSI

  (3103) 0x595347 INC	%RSI

  (3103) 0x59534a AND	$0x7,%ESI

  (3103) 0x59534d JE	59543d

  (3103) 0x595353 CMP	$0x1,%RSI

  (3103) 0x595357 JE	59541a

  (3103) 0x59535d CMP	$0x2,%RSI

  (3103) 0x595361 JE	595400

  (3103) 0x595367 CMP	$0x3,%RSI

  (3103) 0x59536b JE	5953e6

  (3103) 0x59536d CMP	$0x4,%RSI

  (3103) 0x595371 JE	5953cc

  (3103) 0x595373 CMP	$0x5,%RSI

  (3103) 0x595377 JE	5953b2

  (3103) 0x595379 CMP	$0x6,%RSI

  (3103) 0x59537d JE	595398

  (3103) 0x59537f VMOVDQU	(%RDX),%YMM4

  (3103) 0x595383 KMOVB	%K0,%K2

  (3103) 0x595387 MOV	$0x20,%EBX

  (3103) 0x59538c VGATHERQPD	(%R15,%YMM4,8),%YMM10{%K2}

  (3103) 0x595393 VFMADD231PD	(%R14),%YMM10,%YMM0

  (3103) 0x595398 VMOVDQU	(%RDX,%RBX,1),%YMM5

  (3103) 0x59539d KMOVB	%K0,%K3

  (3103) 0x5953a1 VGATHERQPD	(%R15,%YMM5,8),%YMM6{%K3}

  (3103) 0x5953a8 VFMADD231PD	(%R14,%RBX,1),%YMM6,%YMM0

  (3103) 0x5953ae ADD	$0x20,%RBX

  (3103) 0x5953b2 VMOVDQU	(%RDX,%RBX,1),%YMM12

  (3103) 0x5953b7 KMOVB	%K0,%K4

  (3103) 0x5953bb VGATHERQPD	(%R15,%YMM12,8),%YMM11{%K4}

  (3103) 0x5953c2 VFMADD231PD	(%R14,%RBX,1),%YMM11,%YMM0

  (3103) 0x5953c8 ADD	$0x20,%RBX

  (3103) 0x5953cc VMOVDQU	(%RDX,%RBX,1),%YMM1

  (3103) 0x5953d1 KMOVB	%K0,%K5

  (3103) 0x5953d5 VGATHERQPD	(%R15,%YMM1,8),%YMM9{%K5}

  (3103) 0x5953dc VFMADD231PD	(%R14,%RBX,1),%YMM9,%YMM0

  (3103) 0x5953e2 ADD	$0x20,%RBX

  (3103) 0x5953e6 VMOVDQU	(%RDX,%RBX,1),%YMM4

  (3103) 0x5953eb KMOVB	%K0,%K6

  (3103) 0x5953ef VGATHERQPD	(%R15,%YMM4,8),%YMM10{%K6}

  (3103) 0x5953f6 VFMADD231PD	(%R14,%RBX,1),%YMM10,%YMM0

  (3103) 0x5953fc ADD	$0x20,%RBX

  (3103) 0x595400 VMOVDQU	(%RDX,%RBX,1),%YMM5

  (3103) 0x595405 KMOVB	%K0,%K7

  (3103) 0x595409 VGATHERQPD	(%R15,%YMM5,8),%YMM6{%K7}

  (3103) 0x595410 VFMADD231PD	(%R14,%RBX,1),%YMM6,%YMM0

  (3103) 0x595416 ADD	$0x20,%RBX

  (3103) 0x59541a VMOVDQU	(%RDX,%RBX,1),%YMM12

  (3103) 0x59541f KMOVB	%K0,%K1

  (3103) 0x595423 VGATHERQPD	(%R15,%YMM12,8),%YMM11{%K1}

  (3103) 0x59542a VFMADD231PD	(%R14,%RBX,1),%YMM11,%YMM0

  (3103) 0x595430 ADD	$0x20,%RBX

  (3103) 0x595434 CMP	%RBX,%R10

  (3103) 0x595437 JE	595523

    (3105) 0x59543d VMOVDQU	(%RDX,%RBX,1),%YMM9

    (3105) 0x595442 VMOVDQU	0x20(%RDX,%RBX,1),%YMM4

    (3105) 0x595448 KMOVB	%K0,%K2

    (3105) 0x59544c KMOVB	%K0,%K3

    (3105) 0x595450 VMOVDQU	0x40(%RDX,%RBX,1),%YMM5

    (3105) 0x595456 VMOVDQU	0x60(%RDX,%RBX,1),%YMM12

    (3105) 0x59545c KMOVB	%K0,%K4

    (3105) 0x595460 KMOVB	%K0,%K5

    (3105) 0x595464 VMOVDQU	0x80(%RDX,%RBX,1),%YMM11

    (3105) 0x59546d KMOVB	%K0,%K6

    (3105) 0x595471 KMOVB	%K0,%K7

    (3105) 0x595475 KMOVB	%K0,%K1

    (3105) 0x595479 VGATHERQPD	(%R15,%YMM9,8),%YMM1{%K2}

    (3105) 0x595480 VMOVDQU	0xa0(%RDX,%RBX,1),%YMM9

    (3105) 0x595489 VFMADD231PD	(%R14,%RBX,1),%YMM1,%YMM0

    (3105) 0x59548f KMOVB	%K0,%K2

    (3105) 0x595493 VGATHERQPD	(%R15,%YMM4,8),%YMM10{%K3}

    (3105) 0x59549a VGATHERQPD	(%R15,%YMM5,8),%YMM6{%K4}

    (3105) 0x5954a1 VFMADD231PD	0x20(%R14,%RBX,1),%YMM10,%YMM0

    (3105) 0x5954a8 VMOVDQU	0xc0(%RDX,%RBX,1),%YMM10

    (3105) 0x5954b1 VFMADD132PD	0x40(%R14,%RBX,1),%YMM0,%YMM6

    (3105) 0x5954b8 VGATHERQPD	(%R15,%YMM12,8),%YMM0{%K5}

    (3105) 0x5954bf VFMADD132PD	0x60(%R14,%RBX,1),%YMM6,%YMM0

    (3105) 0x5954c6 VMOVDQU	0xe0(%RDX,%RBX,1),%YMM6

    (3105) 0x5954cf VGATHERQPD	(%R15,%YMM11,8),%YMM1{%K6}

    (3105) 0x5954d6 VFMADD132PD	0x80(%R14,%RBX,1),%YMM0,%YMM1

    (3105) 0x5954e0 VGATHERQPD	(%R15,%YMM9,8),%YMM4{%K7}

    (3105) 0x5954e7 VFMADD132PD	0xa0(%R14,%RBX,1),%YMM1,%YMM4

    (3105) 0x5954f1 VGATHERQPD	(%R15,%YMM10,8),%YMM5{%K1}

    (3105) 0x5954f8 VFMADD132PD	0xc0(%R14,%RBX,1),%YMM4,%YMM5

    (3105) 0x595502 VGATHERQPD	(%R15,%YMM6,8),%YMM0{%K2}

    (3105) 0x595509 VFMADD132PD	0xe0(%R14,%RBX,1),%YMM5,%YMM0

    (3105) 0x595513 ADD	$0x100,%RBX

    (3105) 0x59551a CMP	%RBX,%R10

    (3105) 0x59551d JNE	59543d

  (3103) 0x595523 CMPQ	$0,0x18(%RSP)

  (3103) 0x595529 VEXTRACTF64X2	$0x1,%YMM0,%XMM12

  (3103) 0x595530 VADDPD	%XMM0,%XMM12,%XMM11

  (3103) 0x595534 MOV	0x20(%RSP),%RSI

  (3103) 0x595539 VUNPCKHPD	%XMM11,%XMM11,%XMM1

  (3103) 0x59553e VADDPD	%XMM11,%XMM1,%XMM9

  (3103) 0x595543 JE	59559b

  (3103) 0x595545 MOV	(%R13,%RSI,8),%RBX

  (3103) 0x59554a LEA	(,%RSI,8),%R15

  (3103) 0x595552 ADD	%RDI,%RBX

  (3103) 0x595555 VMOVSD	(%RAX,%RBX,8),%XMM4

  (3103) 0x59555a LEA	0x1(%RSI),%RBX

  (3103) 0x59555e VFMADD231SD	(%R12,%RSI,8),%XMM4,%XMM9

  (3103) 0x595564 CMP	%R11,%RBX

  (3103) 0x595567 JGE	59559b

  (3103) 0x595569 MOV	0x8(%R13,%R15,1),%RBX

  (3103) 0x59556e ADD	$0x2,%RSI

  (3103) 0x595572 ADD	%RDI,%RBX

  (3103) 0x595575 VMOVSD	(%RAX,%RBX,8),%XMM10

  (3103) 0x59557a VFMADD231SD	0x8(%R12,%R15,1),%XMM10,%XMM9

  (3103) 0x595581 CMP	%R11,%RSI

  (3103) 0x595584 JGE	59559b

  (3103) 0x595586 MOV	0x10(%R13,%R15,1),%RSI

  (3103) 0x59558b VMOVSD	0x10(%R12,%R15,1),%XMM5

  (3103) 0x595592 ADD	%RDI,%RSI

  (3103) 0x595595 VFMADD231SD	(%RAX,%RSI,8),%XMM5,%XMM9

  (3103) 0x59559b MOV	0x30(%RSP),%R15

  (3103) 0x5955a0 VMOVQ	%XMM3,%RBX

  (3103) 0x5955a5 VADDSD	(%R8),%XMM9,%XMM9

  (3103) 0x5955aa INC	%R9

  (3103) 0x5955ad VMOVSD	%XMM9,(%R8)

  (3103) 0x5955b2 ADD	%RBX,%RDI

  (3103) 0x5955b5 ADD	%R15,%R8

  (3103) 0x5955b8 CMP	%R9,0x38(%RSP)

  (3103) 0x5955bd JNE	595320

(3104) 0x5955c3 MOV	0x8(%RSP),%RCX

(3104) 0x5955c8 ADD	$0x8,%RCX

(3104) 0x5955cc CMP	%RCX,0x10(%RSP)

(3104) 0x5955d1 JE	5955db

(3104) 0x5955d3 MOV	(%RCX),%RDX

(3104) 0x5955d6 JMP	595286

0x5955db VZEROUPPER

0x5955de LEA	-0x28(%RBP),%RSP

0x5955e2 POP	%RBX

0x5955e3 POP	%R12

0x5955e5 POP	%R13

0x5955e7 POP	%R14

0x5955e9 POP	%R15

0x5955eb POP	%RBP

0x5955ec RET

  (3103) 0x5955ed VXORPD	%XMM9,%XMM9,%XMM9

  (3103) 0x5955f2 JMP	59559b

  (3103) 0x5955f4 MOV	%RCX,%RSI

  (3103) 0x5955f7 VXORPD	%XMM9,%XMM9,%XMM9

  (3103) 0x5955fc JMP	595545

0x595601 INC	%RAX

0x595604 XOR	%EDX,%EDX

0x595606 JMP	5951dd

0x59560b CMPQ	$0x1,0x38(%RSP)

0x595611 LEA	(,%R8,8),%RBX

0x595619 MOV	(%R13),%RDX

0x59561d MOV	%R13,%RAX

0x595620 LEA	(%R10,%R9,8),%RCX

0x595624 KXNORB	%K1,%K1,%K1

0x595628 MOV	%RBX,0x28(%RSP)

0x59562d JE	595c07

0x595633 CMPQ	$0,0x38(%RSP)

0x595639 JLE	596034

0x59563f MOV	%RCX,(%RSP)

0x595643 VPBROADCASTQ	%R11,%YMM9

0x595649 KXNORB	%K0,%K0,%K0

0x59564d VMOVQ	%R15,%XMM7

0x595652 VMOVQ	%R14,%XMM14

0x595657 VMOVDQA	%XMM1,%XMM10

0x59565b MOV	%R13,%RCX

0x59565e VMOVQ	%R12,%XMM15

(3098) 0x595663 LEA	(,%RDX,8),%R12

(3098) 0x59566b VMOVQ	%XMM10,%RAX

(3098) 0x595670 VMOVQ	%XMM8,%RSI

(3098) 0x595675 MOV	%RCX,0x8(%RSP)

(3098) 0x59567a MOV	0x8(%RAX,%R12,1),%R10

(3098) 0x59567f MOV	(%RAX,%R12,1),%R14

(3098) 0x595683 IMUL	%RSI,%RDX

(3098) 0x595687 VMOVQ	%XMM2,%RBX

(3098) 0x59568c VMOVQ	%XMM15,%R12

(3098) 0x595691 VMOVQ	%XMM14,%R15

(3098) 0x595696 XOR	%ESI,%ESI

(3098) 0x595698 MOV	%R12,%RCX

(3098) 0x59569b LEA	(%RBX,%RDX,8),%RDI

(3098) 0x59569f MOV	%R10,%R13

(3098) 0x5956a2 LEA	(,%R14,8),%RDX

(3098) 0x5956aa MOV	%R14,0x30(%RSP)

(3098) 0x5956af SUB	%R14,%R13

(3098) 0x5956b2 LEA	(%R12,%RDX,1),%RBX

(3098) 0x5956b6 ADD	%R15,%RDX

(3098) 0x5956b9 MOV	%R13,%R9

(3098) 0x5956bc MOV	%R13,%RAX

(3098) 0x5956bf LEA	-0x1(%R13),%R8

(3098) 0x5956c3 AND	$0x3,%R13D

(3098) 0x5956c7 SHR	$0x2,%R9

(3098) 0x5956cb MOV	%R8,0x20(%RSP)

(3098) 0x5956d0 MOV	%R13,0x10(%RSP)

(3098) 0x5956d5 AND	$-0x4,%RAX

(3098) 0x5956d9 XOR	%R8D,%R8D

(3098) 0x5956dc SAL	$0x5,%R9

(3098) 0x5956e0 ADD	%R14,%RAX

(3098) 0x5956e3 VMOVQ	%XMM7,%R14

(3098) 0x5956e8 MOV	%RAX,0x18(%RSP)

(3098) 0x5956ed NOPL	(%RAX)

  (3097) 0x5956f0 CMP	%R10,0x30(%RSP)

  (3097) 0x5956f5 JGE	595cb0

  (3097) 0x5956fb CMPQ	$0x2,0x20(%RSP)

  (3097) 0x595701 JBE	595cb9

  (3097) 0x595707 LEA	-0x20(%R9),%R13

  (3097) 0x59570b XOR	%EAX,%EAX

  (3097) 0x59570d LEA	(%R14,%RSI,8),%R12

  (3097) 0x595711 VXORPD	%XMM0,%XMM0,%XMM0

  (3097) 0x595715 SHR	$0x5,%R13

  (3097) 0x595719 INC	%R13

  (3097) 0x59571c AND	$0x7,%R13D

  (3097) 0x595720 JE	595822

  (3097) 0x595726 CMP	$0x1,%R13

  (3097) 0x59572a JE	5957fd

  (3097) 0x595730 CMP	$0x2,%R13

  (3097) 0x595734 JE	5957e1

  (3097) 0x59573a CMP	$0x3,%R13

  (3097) 0x59573e JE	5957c5

  (3097) 0x595744 CMP	$0x4,%R13

  (3097) 0x595748 JE	5957a9

  (3097) 0x59574a CMP	$0x5,%R13

  (3097) 0x59574e JE	59578d

  (3097) 0x595750 CMP	$0x6,%R13

  (3097) 0x595754 JE	595771

  (3097) 0x595756 VPMULLQ	(%RDX),%YMM9,%YMM5

  (3097) 0x59575c KMOVB	%K0,%K1

  (3097) 0x595760 MOV	$0x20,%EAX

  (3097) 0x595765 VGATHERQPD	(%R12,%YMM5,8),%YMM3{%K1}

  (3097) 0x59576c VFMADD231PD	(%RBX),%YMM3,%YMM0

  (3097) 0x595771 VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM6

  (3097) 0x595778 KMOVB	%K0,%K2

  (3097) 0x59577c VGATHERQPD	(%R12,%YMM6,8),%YMM11{%K2}

  (3097) 0x595783 VFMADD231PD	(%RBX,%RAX,1),%YMM11,%YMM0

  (3097) 0x595789 ADD	$0x20,%RAX

  (3097) 0x59578d VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM12

  (3097) 0x595794 KMOVB	%K0,%K3

  (3097) 0x595798 VGATHERQPD	(%R12,%YMM12,8),%YMM13{%K3}

  (3097) 0x59579f VFMADD231PD	(%RBX,%RAX,1),%YMM13,%YMM0

  (3097) 0x5957a5 ADD	$0x20,%RAX

  (3097) 0x5957a9 VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM1

  (3097) 0x5957b0 KMOVB	%K0,%K4

  (3097) 0x5957b4 VGATHERQPD	(%R12,%YMM1,8),%YMM5{%K4}

  (3097) 0x5957bb VFMADD231PD	(%RBX,%RAX,1),%YMM5,%YMM0

  (3097) 0x5957c1 ADD	$0x20,%RAX

  (3097) 0x5957c5 VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM3

  (3097) 0x5957cc KMOVB	%K0,%K5

  (3097) 0x5957d0 VGATHERQPD	(%R12,%YMM3,8),%YMM6{%K5}

  (3097) 0x5957d7 VFMADD231PD	(%RBX,%RAX,1),%YMM6,%YMM0

  (3097) 0x5957dd ADD	$0x20,%RAX

  (3097) 0x5957e1 VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM12

  (3097) 0x5957e8 KMOVB	%K0,%K6

  (3097) 0x5957ec VGATHERQPD	(%R12,%YMM12,8),%YMM11{%K6}

  (3097) 0x5957f3 VFMADD231PD	(%RBX,%RAX,1),%YMM11,%YMM0

  (3097) 0x5957f9 ADD	$0x20,%RAX

  (3097) 0x5957fd VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM13

  (3097) 0x595804 KMOVB	%K0,%K7

  (3097) 0x595808 VGATHERQPD	(%R12,%YMM13,8),%YMM1{%K7}

  (3097) 0x59580f VFMADD231PD	(%RBX,%RAX,1),%YMM1,%YMM0

  (3097) 0x595815 ADD	$0x20,%RAX

  (3097) 0x595819 CMP	%R9,%RAX

  (3097) 0x59581c JE	59590b

    (3099) 0x595822 VPMULLQ	(%RDX,%RAX,1),%YMM9,%YMM5

    (3099) 0x595829 VPMULLQ	0x20(%RDX,%RAX,1),%YMM9,%YMM6

    (3099) 0x595831 KMOVB	%K0,%K1

    (3099) 0x595835 KMOVB	%K0,%K2

    (3099) 0x595839 VPMULLQ	0x40(%RDX,%RAX,1),%YMM9,%YMM13

    (3099) 0x595841 VPMULLQ	0x60(%RDX,%RAX,1),%YMM9,%YMM1

    (3099) 0x595849 KMOVB	%K0,%K3

    (3099) 0x59584d KMOVB	%K0,%K4

    (3099) 0x595851 KMOVB	%K0,%K5

    (3099) 0x595855 KMOVB	%K0,%K6

    (3099) 0x595859 KMOVB	%K0,%K7

    (3099) 0x59585d VGATHERQPD	(%R12,%YMM5,8),%YMM3{%K1}

    (3099) 0x595864 VPMULLQ	0x80(%RDX,%RAX,1),%YMM9,%YMM5

    (3099) 0x59586c VFMADD231PD	(%RBX,%RAX,1),%YMM3,%YMM0

    (3099) 0x595872 KMOVB	%K0,%K1

    (3099) 0x595876 VGATHERQPD	(%R12,%YMM6,8),%YMM12{%K2}

    (3099) 0x59587d VGATHERQPD	(%R12,%YMM13,8),%YMM11{%K3}

    (3099) 0x595884 VFMADD231PD	0x20(%RBX,%RAX,1),%YMM12,%YMM0

    (3099) 0x59588b VPMULLQ	0xa0(%RDX,%RAX,1),%YMM9,%YMM6

    (3099) 0x595893 VFMADD132PD	0x40(%RBX,%RAX,1),%YMM0,%YMM11

    (3099) 0x59589a VPMULLQ	0xc0(%RDX,%RAX,1),%YMM9,%YMM12

    (3099) 0x5958a2 VGATHERQPD	(%R12,%YMM1,8),%YMM0{%K4}

    (3099) 0x5958a9 VPMULLQ	0xe0(%RDX,%RAX,1),%YMM9,%YMM1

    (3099) 0x5958b1 VFMADD132PD	0x60(%RBX,%RAX,1),%YMM11,%YMM0

    (3099) 0x5958b8 VGATHERQPD	(%R12,%YMM5,8),%YMM3{%K5}

    (3099) 0x5958bf VFMADD132PD	0x80(%RBX,%RAX,1),%YMM0,%YMM3

    (3099) 0x5958c9 VGATHERQPD	(%R12,%YMM6,8),%YMM13{%K6}

    (3099) 0x5958d0 VFMADD132PD	0xa0(%RBX,%RAX,1),%YMM3,%YMM13

    (3099) 0x5958da VGATHERQPD	(%R12,%YMM12,8),%YMM11{%K7}

    (3099) 0x5958e1 VGATHERQPD	(%R12,%YMM1,8),%YMM0{%K1}

    (3099) 0x5958e8 VFMADD132PD	0xc0(%RBX,%RAX,1),%YMM13,%YMM11

    (3099) 0x5958f2 VFMADD132PD	0xe0(%RBX,%RAX,1),%YMM11,%YMM0

    (3099) 0x5958fc ADD	$0x100,%RAX

    (3099) 0x595902 CMP	%R9,%RAX

    (3099) 0x595905 JNE	595822

  (3097) 0x59590b CMPQ	$0,0x10(%RSP)

  (3097) 0x595911 VEXTRACTF64X2	$0x1,%YMM0,%XMM5

  (3097) 0x595918 VADDPD	%XMM0,%XMM5,%XMM3

  (3097) 0x59591c MOV	0x18(%RSP),%RAX

  (3097) 0x595921 VUNPCKHPD	%XMM3,%XMM3,%XMM6

  (3097) 0x595925 VADDPD	%XMM3,%XMM6,%XMM1

  (3097) 0x595929 JE	59598d

  (3097) 0x59592b MOV	(%R15,%RAX,8),%R13

  (3097) 0x59592f VMOVSD	(%RCX,%RAX,8),%XMM13

  (3097) 0x595934 LEA	(,%RAX,8),%R12

  (3097) 0x59593c IMUL	%R11,%R13

  (3097) 0x595940 ADD	%RSI,%R13

  (3097) 0x595943 VFMADD231SD	(%R14,%R13,8),%XMM13,%XMM1

  (3097) 0x595949 LEA	0x1(%RAX),%R13

  (3097) 0x59594d CMP	%R13,%R10

  (3097) 0x595950 JLE	59598d

  (3097) 0x595952 MOV	0x8(%R15,%R12,1),%R13

  (3097) 0x595957 ADD	$0x2,%RAX

  (3097) 0x59595b VMOVSD	0x8(%RCX,%R12,1),%XMM12

  (3097) 0x595962 IMUL	%R11,%R13

  (3097) 0x595966 ADD	%RSI,%R13

  (3097) 0x595969 VFMADD231SD	(%R14,%R13,8),%XMM12,%XMM1

  (3097) 0x59596f CMP	%RAX,%R10

  (3097) 0x595972 JLE	59598d

  (3097) 0x595974 MOV	0x10(%R15,%R12,1),%RAX

  (3097) 0x595979 VMOVSD	0x10(%RCX,%R12,1),%XMM11

  (3097) 0x595980 IMUL	%R11,%RAX

  (3097) 0x595984 ADD	%RSI,%RAX

  (3097) 0x595987 VFMADD231SD	(%R14,%RAX,8),%XMM11,%XMM1

  (3097) 0x59598d MOV	0x28(%RSP),%R12

  (3097) 0x595992 VMOVQ	%XMM4,%R13

  (3097) 0x595997 VADDSD	(%RDI),%XMM1,%XMM1

  (3097) 0x59599b INC	%R8

  (3097) 0x59599e VMOVSD	%XMM1,(%RDI)

  (3097) 0x5959a2 ADD	%R13,%RSI

  (3097) 0x5959a5 ADD	%R12,%RDI

  (3097) 0x5959a8 CMP	%R8,0x38(%RSP)

  (3097) 0x5959ad JNE	5956f0

(3098) 0x5959b3 MOV	0x8(%RSP),%RCX

(3098) 0x5959b8 MOV	(%RSP),%R10

(3098) 0x5959bc ADD	$0x8,%RCX

(3098) 0x5959c0 CMP	%R10,%RCX

(3098) 0x5959c3 JE	5955db

(3098) 0x5959c9 MOV	(%RCX),%RDX

(3098) 0x5959cc JMP	595663

(3094) 0x5959d1 VMOVDQU	(%RSI),%YMM7

(3094) 0x5959d5 KMOVB	%K1,%K5

(3094) 0x5959d9 MOV	$0x20,%EDX

(3094) 0x5959de VGATHERQPD	(%R15,%YMM7,8),%YMM3{%K5}

(3094) 0x5959e5 VFMADD231PD	(%RDI),%YMM3,%YMM0

(3094) 0x5959ea VMOVDQU	(%RSI,%RDX,1),%YMM5

(3094) 0x5959ef KMOVB	%K1,%K6

(3094) 0x5959f3 VGATHERQPD	(%R15,%YMM5,8),%YMM6{%K6}

(3094) 0x5959fa VFMADD231PD	(%RDI,%RDX,1),%YMM6,%YMM0

(3094) 0x595a00 ADD	$0x20,%RDX

(3094) 0x595a04 VMOVDQU	(%RSI,%RDX,1),%YMM9

(3094) 0x595a09 KMOVB	%K1,%K7

(3094) 0x595a0d VGATHERQPD	(%R15,%YMM9,8),%YMM10{%K7}

(3094) 0x595a14 VFMADD231PD	(%RDI,%RDX,1),%YMM10,%YMM0

(3094) 0x595a1a ADD	$0x20,%RDX

(3094) 0x595a1e VMOVDQU	(%RSI,%RDX,1),%YMM11

(3094) 0x595a23 KMOVB	%K1,%K2

(3094) 0x595a27 VGATHERQPD	(%R15,%YMM11,8),%YMM12{%K2}

(3094) 0x595a2e VFMADD231PD	(%RDI,%RDX,1),%YMM12,%YMM0

(3094) 0x595a34 ADD	$0x20,%RDX

(3094) 0x595a38 VMOVDQU	(%RSI,%RDX,1),%YMM13

(3094) 0x595a3d KMOVB	%K1,%K3

(3094) 0x595a41 VGATHERQPD	(%R15,%YMM13,8),%YMM14{%K3}

(3094) 0x595a48 VFMADD231PD	(%RDI,%RDX,1),%YMM14,%YMM0

(3094) 0x595a4e ADD	$0x20,%RDX

(3094) 0x595a52 VMOVDQU	(%RSI,%RDX,1),%YMM15

(3094) 0x595a57 KMOVB	%K1,%K4

(3094) 0x595a5b VGATHERQPD	(%R15,%YMM15,8),%YMM4{%K4}

(3094) 0x595a62 VFMADD231PD	(%RDI,%RDX,1),%YMM4,%YMM0

(3094) 0x595a68 ADD	$0x20,%RDX

(3094) 0x595a6c VMOVDQU	(%RSI,%RDX,1),%YMM8

(3094) 0x595a71 KMOVB	%K1,%K5

(3094) 0x595a75 VGATHERQPD	(%R15,%YMM8,8),%YMM7{%K5}

(3094) 0x595a7c VFMADD231PD	(%RDI,%RDX,1),%YMM7,%YMM0

(3094) 0x595a82 ADD	$0x20,%RDX

(3094) 0x595a86 CMP	%R13,%RDX

(3094) 0x595a89 JE	595b75

  (3095) 0x595a8f VMOVDQU	(%RSI,%RDX,1),%YMM5

  (3095) 0x595a94 VMOVDQU	0x20(%RSI,%RDX,1),%YMM6

  (3095) 0x595a9a KMOVB	%K1,%K6

  (3095) 0x595a9e KMOVB	%K1,%K7

  (3095) 0x595aa2 VMOVDQU	0x40(%RSI,%RDX,1),%YMM10

  (3095) 0x595aa8 VMOVDQU	0x60(%RSI,%RDX,1),%YMM12

  (3095) 0x595aae KMOVB	%K1,%K2

  (3095) 0x595ab2 VMOVDQU	0x80(%RSI,%RDX,1),%YMM13

  (3095) 0x595abb VMOVDQU	0xa0(%RSI,%RDX,1),%YMM15

  (3095) 0x595ac4 KMOVB	%K1,%K3

  (3095) 0x595ac8 VMOVDQU	0xc0(%RSI,%RDX,1),%YMM8

  (3095) 0x595ad1 VMOVDQU	0xe0(%RSI,%RDX,1),%YMM7

  (3095) 0x595ada KMOVB	%K1,%K4

  (3095) 0x595ade KMOVB	%K1,%K5

  (3095) 0x595ae2 VGATHERQPD	(%R15,%YMM5,8),%YMM3{%K6}

  (3095) 0x595ae9 KMOVB	%K1,%K6

  (3095) 0x595aed VGATHERQPD	(%R15,%YMM6,8),%YMM9{%K7}

  (3095) 0x595af4 VFMADD231PD	(%RDI,%RDX,1),%YMM3,%YMM0

  (3095) 0x595afa KMOVB	%K1,%K7

  (3095) 0x595afe VFMADD231PD	0x20(%RDI,%RDX,1),%YMM9,%YMM0

  (3095) 0x595b05 VGATHERQPD	(%R15,%YMM10,8),%YMM11{%K2}

  (3095) 0x595b0c VFMADD132PD	0x40(%RDI,%RDX,1),%YMM0,%YMM11

  (3095) 0x595b13 VGATHERQPD	(%R15,%YMM13,8),%YMM14{%K4}

  (3095) 0x595b1a VGATHERQPD	(%R15,%YMM12,8),%YMM0{%K3}

  (3095) 0x595b21 VGATHERQPD	(%R15,%YMM15,8),%YMM4{%K5}

  (3095) 0x595b28 VFMADD132PD	0x60(%RDI,%RDX,1),%YMM11,%YMM0

  (3095) 0x595b2f VGATHERQPD	(%R15,%YMM8,8),%YMM5{%K6}

  (3095) 0x595b36 VFMADD132PD	0x80(%RDI,%RDX,1),%YMM0,%YMM14

  (3095) 0x595b40 VGATHERQPD	(%R15,%YMM7,8),%YMM0{%K7}

  (3095) 0x595b47 VFMADD132PD	0xa0(%RDI,%RDX,1),%YMM14,%YMM4

  (3095) 0x595b51 VFMADD132PD	0xc0(%RDI,%RDX,1),%YMM4,%YMM5

  (3095) 0x595b5b VFMADD132PD	0xe0(%RDI,%RDX,1),%YMM5,%YMM0

  (3095) 0x595b65 ADD	$0x100,%RDX

  (3095) 0x595b6c CMP	%R13,%RDX

  (3095) 0x595b6f JNE	595a8f

(3094) 0x595b75 VEXTRACTF64X2	$0x1,%YMM0,%XMM3

(3094) 0x595b7c VADDPD	%XMM0,%XMM3,%XMM6

(3094) 0x595b80 MOV	%RBX,%RSI

(3094) 0x595b83 AND	$-0x4,%RSI

(3094) 0x595b87 ADD	%RSI,%R9

(3094) 0x595b8a AND	$0x3,%EBX

(3094) 0x595b8d VUNPCKHPD	%XMM6,%XMM6,%XMM9

(3094) 0x595b91 VADDPD	%XMM6,%XMM9,%XMM0

(3094) 0x595b95 JE	595be5

(3094) 0x595b97 LEA	(,%R9,8),%RBX

(3094) 0x595b9f LEA	0x1(%R9),%R13

(3094) 0x595ba3 MOV	(%R14,%RBX,1),%RDI

(3094) 0x595ba7 VMOVSD	(%R15,%RDI,8),%XMM10

(3094) 0x595bad VFMADD231SD	(%R12,%RBX,1),%XMM10,%XMM0

(3094) 0x595bb3 CMP	%R11,%R13

(3094) 0x595bb6 JGE	595be5

(3094) 0x595bb8 MOV	0x8(%R14,%RBX,1),%R8

(3094) 0x595bbd ADD	$0x2,%R9

(3094) 0x595bc1 VMOVSD	0x8(%R12,%RBX,1),%XMM11

(3094) 0x595bc8 VFMADD231SD	(%R15,%R8,8),%XMM11,%XMM0

(3094) 0x595bce CMP	%R9,%R11

(3094) 0x595bd1 JLE	595be5

(3094) 0x595bd3 MOV	0x10(%R14,%RBX,1),%R9

(3094) 0x595bd8 VMOVSD	0x10(%R12,%RBX,1),%XMM12

(3094) 0x595bdf VFMADD231SD	(%R15,%R9,8),%XMM12,%XMM0

(3094) 0x595be5 VMOVQ	%XMM2,%R11

(3094) 0x595bea ADD	$0x8,%RAX

(3094) 0x595bee ADD	%R11,%R10

(3094) 0x595bf1 VADDSD	(%R10),%XMM0,%XMM13

(3094) 0x595bf6 VMOVSD	%XMM13,(%R10)

(3094) 0x595bfb CMP	%RCX,%RAX

(3094) 0x595bfe JE	5955db

(3094) 0x595c04 MOV	(%RAX),%RDX

(3094) 0x595c07 LEA	(,%RDX,8),%R10

(3094) 0x595c0f VMOVQ	%XMM1,%RSI

(3094) 0x595c14 MOV	(%RSI,%R10,1),%R9

(3094) 0x595c18 MOV	0x8(%RSI,%R10,1),%R11

(3094) 0x595c1d CMP	%R11,%R9

(3094) 0x595c20 JGE	595fa7

(3094) 0x595c26 MOV	%R11,%RBX

(3094) 0x595c29 SUB	%R9,%RBX

(3094) 0x595c2c LEA	-0x1(%RBX),%RDX

(3094) 0x595c30 CMP	$0x2,%RDX

(3094) 0x595c34 JBE	595fb0

(3094) 0x595c3a MOV	%RBX,%R13

(3094) 0x595c3d LEA	(,%R9,8),%RSI

(3094) 0x595c45 XOR	%EDX,%EDX

(3094) 0x595c47 VXORPD	%XMM0,%XMM0,%XMM0

(3094) 0x595c4b SHR	$0x2,%R13

(3094) 0x595c4f SAL	$0x5,%R13

(3094) 0x595c53 LEA	-0x20(%R13),%R8

(3094) 0x595c57 LEA	(%R12,%RSI,1),%RDI

(3094) 0x595c5b ADD	%R14,%RSI

(3094) 0x595c5e SHR	$0x5,%R8

(3094) 0x595c62 INC	%R8

(3094) 0x595c65 AND	$0x7,%R8D

(3094) 0x595c69 JE	595a8f

(3094) 0x595c6f CMP	$0x1,%R8

(3094) 0x595c73 JE	595a6c

(3094) 0x595c79 CMP	$0x2,%R8

(3094) 0x595c7d JE	595a52

(3094) 0x595c83 CMP	$0x3,%R8

(3094) 0x595c87 JE	595a38

(3094) 0x595c8d CMP	$0x4,%R8

(3094) 0x595c91 JE	595a1e

(3094) 0x595c97 CMP	$0x5,%R8

(3094) 0x595c9b JE	595a04

(3094) 0x595ca1 CMP	$0x6,%R8

(3094) 0x595ca5 JE	5959ea

(3094) 0x595cab JMP	5959d1

  (3097) 0x595cb0 VXORPD	%XMM1,%XMM1,%XMM1

  (3097) 0x595cb4 JMP	59598d

  (3097) 0x595cb9 MOV	0x30(%RSP),%RAX

  (3097) 0x595cbe VXORPD	%XMM1,%XMM1,%XMM1

  (3097) 0x595cc2 JMP	59592b

0x595cc7 VMOVQ	%XMM1,%RBX

(3100) 0x595ccc LEA	(,%RDI,8),%RDI

(3100) 0x595cd4 MOV	(%RBX,%RDI,1),%R9

(3100) 0x595cd8 MOV	0x8(%RBX,%RDI,1),%R13

(3100) 0x595cdd CMP	%R9,%R13

(3100) 0x595ce0 JLE	595f96

(3100) 0x595ce6 MOV	%R13,%R11

(3100) 0x595ce9 SUB	%R9,%R11

(3100) 0x595cec LEA	-0x1(%R11),%RAX

(3100) 0x595cf0 CMP	$0x2,%RAX

(3100) 0x595cf4 JBE	595f9d

(3100) 0x595cfa MOV	%R11,%R10

(3100) 0x595cfd LEA	(,%R9,8),%RDX

(3100) 0x595d05 XOR	%EAX,%EAX

(3100) 0x595d07 VXORPD	%XMM0,%XMM0,%XMM0

(3100) 0x595d0b SHR	$0x2,%R10

(3100) 0x595d0f SAL	$0x5,%R10

(3100) 0x595d13 LEA	-0x20(%R10),%R8

(3100) 0x595d17 LEA	(%R12,%RDX,1),%RSI

(3100) 0x595d1b ADD	%R14,%RDX

(3100) 0x595d1e SHR	$0x5,%R8

(3100) 0x595d22 INC	%R8

(3100) 0x595d25 AND	$0x7,%R8D

(3100) 0x595d29 JE	595e19

(3100) 0x595d2f CMP	$0x1,%R8

(3100) 0x595d33 JE	595df6

(3100) 0x595d39 CMP	$0x2,%R8

(3100) 0x595d3d JE	595ddc

(3100) 0x595d43 CMP	$0x3,%R8

(3100) 0x595d47 JE	595dc2

(3100) 0x595d49 CMP	$0x4,%R8

(3100) 0x595d4d JE	595da8

(3100) 0x595d4f CMP	$0x5,%R8

(3100) 0x595d53 JE	595d8e

(3100) 0x595d55 CMP	$0x6,%R8

(3100) 0x595d59 JE	595d74

(3100) 0x595d5b VMOVDQU	(%RDX),%YMM7

(3100) 0x595d5f KMOVB	%K0,%K3

(3100) 0x595d63 MOV	$0x20,%EAX

(3100) 0x595d68 VGATHERQPD	(%R15,%YMM7,8),%YMM3{%K3}

(3100) 0x595d6f VFMADD231PD	(%RSI),%YMM3,%YMM0

(3100) 0x595d74 VMOVDQU	(%RDX,%RAX,1),%YMM14

(3100) 0x595d79 KMOVB	%K0,%K4

(3100) 0x595d7d VGATHERQPD	(%R15,%YMM14,8),%YMM15{%K4}

(3100) 0x595d84 VFMADD231PD	(%RSI,%RAX,1),%YMM15,%YMM0

(3100) 0x595d8a ADD	$0x20,%RAX

(3100) 0x595d8e VMOVDQU	(%RDX,%RAX,1),%YMM13

(3100) 0x595d93 KMOVB	%K0,%K5

(3100) 0x595d97 VGATHERQPD	(%R15,%YMM13,8),%YMM6{%K5}

(3100) 0x595d9e VFMADD231PD	(%RSI,%RAX,1),%YMM6,%YMM0

(3100) 0x595da4 ADD	$0x20,%RAX

(3100) 0x595da8 VMOVDQU	(%RDX,%RAX,1),%YMM12

(3100) 0x595dad KMOVB	%K0,%K6

(3100) 0x595db1 VGATHERQPD	(%R15,%YMM12,8),%YMM11{%K6}

(3100) 0x595db8 VFMADD231PD	(%RSI,%RAX,1),%YMM11,%YMM0

(3100) 0x595dbe ADD	$0x20,%RAX

(3100) 0x595dc2 VMOVDQU	(%RDX,%RAX,1),%YMM1

(3100) 0x595dc7 KMOVB	%K0,%K7

(3100) 0x595dcb VGATHERQPD	(%R15,%YMM1,8),%YMM4{%K7}

(3100) 0x595dd2 VFMADD231PD	(%RSI,%RAX,1),%YMM4,%YMM0

(3100) 0x595dd8 ADD	$0x20,%RAX

(3100) 0x595ddc VMOVDQU	(%RDX,%RAX,1),%YMM10

(3100) 0x595de1 KMOVB	%K0,%K1

(3100) 0x595de5 VGATHERQPD	(%R15,%YMM10,8),%YMM5{%K1}

(3100) 0x595dec VFMADD231PD	(%RSI,%RAX,1),%YMM5,%YMM0

(3100) 0x595df2 ADD	$0x20,%RAX

(3100) 0x595df6 VMOVDQU	(%RDX,%RAX,1),%YMM9

(3100) 0x595dfb KMOVB	%K0,%K2

(3100) 0x595dff VGATHERQPD	(%R15,%YMM9,8),%YMM8{%K2}

(3100) 0x595e06 VFMADD231PD	(%RSI,%RAX,1),%YMM8,%YMM0

(3100) 0x595e0c ADD	$0x20,%RAX

(3100) 0x595e10 CMP	%RAX,%R10

(3100) 0x595e13 JE	595efe

  (3101) 0x595e19 VMOVDQU	(%RDX,%RAX,1),%YMM7

  (3101) 0x595e1e VMOVDQU	0x20(%RDX,%RAX,1),%YMM14

  (3101) 0x595e24 KMOVB	%K0,%K3

  (3101) 0x595e28 KMOVB	%K0,%K4

  (3101) 0x595e2c VMOVDQU	0x40(%RDX,%RAX,1),%YMM13

  (3101) 0x595e32 VMOVDQU	0x60(%RDX,%RAX,1),%YMM12

  (3101) 0x595e38 KMOVB	%K0,%K5

  (3101) 0x595e3c VMOVDQU	0x80(%RDX,%RAX,1),%YMM11

  (3101) 0x595e45 VMOVDQU	0xa0(%RDX,%RAX,1),%YMM4

  (3101) 0x595e4e KMOVB	%K0,%K6

  (3101) 0x595e52 VMOVDQU	0xc0(%RDX,%RAX,1),%YMM5

  (3101) 0x595e5b VMOVDQU	0xe0(%RDX,%RAX,1),%YMM8

  (3101) 0x595e64 KMOVB	%K0,%K7

  (3101) 0x595e68 KMOVB	%K0,%K1

  (3101) 0x595e6c KMOVB	%K0,%K2

  (3101) 0x595e70 VGATHERQPD	(%R15,%YMM7,8),%YMM3{%K3}

  (3101) 0x595e77 KMOVB	%K0,%K3

  (3101) 0x595e7b VFMADD231PD	(%RSI,%RAX,1),%YMM3,%YMM0

  (3101) 0x595e81 VGATHERQPD	(%R15,%YMM14,8),%YMM15{%K4}

  (3101) 0x595e88 VGATHERQPD	(%R15,%YMM13,8),%YMM6{%K5}

  (3101) 0x595e8f VFMADD231PD	0x20(%RSI,%RAX,1),%YMM15,%YMM0

  (3101) 0x595e96 VFMADD132PD	0x40(%RSI,%RAX,1),%YMM0,%YMM6

  (3101) 0x595e9d VGATHERQPD	(%R15,%YMM12,8),%YMM0{%K6}

  (3101) 0x595ea4 VGATHERQPD	(%R15,%YMM11,8),%YMM1{%K7}

  (3101) 0x595eab VFMADD132PD	0x60(%RSI,%RAX,1),%YMM6,%YMM0

  (3101) 0x595eb2 VGATHERQPD	(%R15,%YMM4,8),%YMM10{%K1}

  (3101) 0x595eb9 VFMADD132PD	0x80(%RSI,%RAX,1),%YMM0,%YMM1

  (3101) 0x595ec3 VGATHERQPD	(%R15,%YMM5,8),%YMM9{%K2}

  (3101) 0x595eca VFMADD132PD	0xa0(%RSI,%RAX,1),%YMM1,%YMM10

  (3101) 0x595ed4 VGATHERQPD	(%R15,%YMM8,8),%YMM0{%K3}

  (3101) 0x595edb VFMADD132PD	0xc0(%RSI,%RAX,1),%YMM10,%YMM9

  (3101) 0x595ee5 VFMADD132PD	0xe0(%RSI,%RAX,1),%YMM9,%YMM0

  (3101) 0x595eef ADD	$0x100,%RAX

  (3101) 0x595ef5 CMP	%RAX,%R10

  (3101) 0x595ef8 JNE	595e19

(3100) 0x595efe VEXTRACTF64X2	$0x1,%YMM0,%XMM7

(3100) 0x595f05 VADDPD	%XMM0,%XMM7,%XMM3

(3100) 0x595f09 MOV	%R11,%RDX

(3100) 0x595f0c AND	$-0x4,%RDX

(3100) 0x595f10 ADD	%RDX,%R9

(3100) 0x595f13 AND	$0x3,%R11D

(3100) 0x595f17 VUNPCKHPD	%XMM3,%XMM3,%XMM14

(3100) 0x595f1b VADDPD	%XMM3,%XMM14,%XMM8

(3100) 0x595f1f JE	595f6f

(3100) 0x595f21 LEA	(,%R9,8),%R11

(3100) 0x595f29 LEA	0x1(%R9),%R10

(3100) 0x595f2d MOV	(%R14,%R11,1),%RSI

(3100) 0x595f31 VMOVSD	(%R12,%R11,1),%XMM15

(3100) 0x595f37 VFMADD231SD	(%R15,%RSI,8),%XMM15,%XMM8

(3100) 0x595f3d CMP	%R13,%R10

(3100) 0x595f40 JGE	595f6f

(3100) 0x595f42 MOV	0x8(%R14,%R11,1),%R8

(3100) 0x595f47 ADD	$0x2,%R9

(3100) 0x595f4b VMOVSD	(%R15,%R8,8),%XMM13

(3100) 0x595f51 VFMADD231SD	0x8(%R12,%R11,1),%XMM13,%XMM8

(3100) 0x595f58 CMP	%R13,%R9

(3100) 0x595f5b JGE	595f6f

(3100) 0x595f5d MOV	0x10(%R14,%R11,1),%R9

(3100) 0x595f62 VMOVSD	(%R15,%R9,8),%XMM6

(3100) 0x595f68 VFMADD231SD	0x10(%R12,%R11,1),%XMM6,%XMM8

(3100) 0x595f6f VMOVQ	%XMM2,%R13

(3100) 0x595f74 ADD	$0x8,%RCX

(3100) 0x595f78 ADD	%R13,%RDI

(3100) 0x595f7b VADDSD	(%RDI),%XMM8,%XMM12

(3100) 0x595f7f VMOVSD	%XMM12,(%RDI)

(3100) 0x595f83 CMP	%RCX,0x10(%RSP)

(3100) 0x595f88 JE	5955db

(3100) 0x595f8e MOV	(%RCX),%RDI

(3100) 0x595f91 JMP	595ccc

(3100) 0x595f96 VXORPD	%XMM8,%XMM8,%XMM8

(3100) 0x595f9b JMP	595f6f

(3100) 0x595f9d VXORPD	%XMM8,%XMM8,%XMM8

(3100) 0x595fa2 JMP	595f21

(3094) 0x595fa7 VXORPD	%XMM0,%XMM0,%XMM0

(3094) 0x595fab JMP	595be5

(3094) 0x595fb0 VXORPD	%XMM0,%XMM0,%XMM0

(3094) 0x595fb4 JMP	595b97

0x595fb9 MOV	0x10(%RSP),%RBX

0x595fbe SUB	%R13,%RBX

0x595fc1 SUB	$0x8,%RBX

0x595fc5 SHR	$0x3,%RBX

0x595fc9 INC	%RBX

0x595fcc AND	$0x7,%EBX

0x595fcf JE	596021

0x595fd1 CMP	$0x1,%RBX

0x595fd5 JE	59600f

0x595fd7 CMP	$0x2,%RBX

0x595fdb JE	59600b

0x595fdd CMP	$0x3,%RBX

0x595fe1 JE	596007

0x595fe3 CMP	$0x4,%RBX

0x595fe7 JE	596003

0x595fe9 CMP	$0x5,%RBX

0x595fed JE	595fff

0x595fef ADD	$0x8,%R13

0x595ff3 CMP	$0x6,%RBX

0x595ff7 CMOVNE	%R13,%RCX

0x595ffb ADD	$0x8,%RCX

0x595fff ADD	$0x8,%RCX

0x596003 ADD	$0x8,%RCX

0x596007 ADD	$0x8,%RCX

0x59600b ADD	$0x8,%RCX

0x59600f MOV	0x10(%RSP),%RDX

0x596014 ADD	$0x8,%RCX

0x596018 CMP	%RDX,%RCX

0x59601b JE	5955de

(3102) 0x596021 MOV	0x10(%RSP),%R15

(3102) 0x596026 ADD	$0x40,%RCX

(3102) 0x59602a CMP	%R15,%RCX

(3102) 0x59602d JNE	596021

0x59602f JMP	5955de

0x596034 MOV	%RCX,%R15

0x596037 SUB	%R13,%R15

0x59603a SUB	$0x8,%R15

0x59603e SHR	$0x3,%R15

0x596042 INC	%R15

0x596045 AND	$0x7,%R15D

0x596049 JE	596096

0x59604b CMP	$0x1,%R15

0x59604f JE	596089

0x596051 CMP	$0x2,%R15

0x596055 JE	596085

0x596057 CMP	$0x3,%R15

0x59605b JE	596081

0x59605d CMP	$0x4,%R15

0x596061 JE	59607d

0x596063 CMP	$0x5,%R15

0x596067 JE	596079

0x596069 ADD	$0x8,%R13

0x59606d CMP	$0x6,%R15

0x596071 CMOVNE	%R13,%RAX

0x596075 ADD	$0x8,%RAX

0x596079 ADD	$0x8,%RAX

0x59607d ADD	$0x8,%RAX

0x596081 ADD	$0x8,%RAX

0x596085 ADD	$0x8,%RAX

0x596089 ADD	$0x8,%RAX

0x59608d CMP	%RCX,%RAX

0x596090 JE	5955de

(3096) 0x596096 ADD	$0x40,%RAX

(3096) 0x59609a CMP	%RCX,%RAX

(3096) 0x59609d JNE	596096

0x59609f JMP	5955de

0x5960a4 NOPW	%CS:(%RAX,%RAX,1)

0x5960af NOP

Coverage (%)	Name	Source Location	Module
►96.91+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.84+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:231	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_BoomerAMGCycle	par_cycle.c:429	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►1.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:231	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_PCGSolve	pcg.c:496	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 7.83 cycles (2.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:203

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	149
nb uops	150
loop length	575
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	1
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	16.00	16.00	16.00	16.00	16.00	16.00	6.75	6.75	6.75	6.75	1.50	0.50	0.50	1.50	0.50	0.50
cycles	16.00	16.00	16.00	16.00	16.00	16.00	6.75	6.75	6.75	6.75	1.50	0.50	0.50	1.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.75
Dispatch	16.00
DIV/SQRT	7.00-12.00
Overall L1	18.75

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.75 cycles. At this rate:

3% of peak load performance is reached (8.53 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 18.75 to 16.00 cycles (1.17x speedup).

ASM code

In the binary file, the address of the function is: 5951a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 595601 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x58(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (%R10,%RCX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 59560b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x46b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA (,%R8,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R9,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
KXNORB %K0,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV (%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 595cc7 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xb27>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 595fb9 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R15,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R12,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 5951dd <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMPQ $0x1,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA (,%R8,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R13),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
KXNORB %K1,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 595c07 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xa67>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 596034 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R11,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
KXNORB %K0,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVQ %R15,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R12,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 596021 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59600f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59600b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe6b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596007 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe67>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596003 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe63>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595fff <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe5f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNE %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R13,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 596096 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xef6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596089 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596085 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596081 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59607d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xedd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596079 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xed9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNE %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 7.83 cycles (2.39x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
VPBROADCASTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:203

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 160 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	149
nb uops	150
loop length	575
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	1
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	16.00	16.00	16.00	16.00	16.00	16.00	6.75	6.75	6.75	6.75	1.50	0.50	0.50	1.50	0.50	0.50
cycles	16.00	16.00	16.00	16.00	16.00	16.00	6.75	6.75	6.75	6.75	1.50	0.50	0.50	1.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.75
Dispatch	16.00
DIV/SQRT	7.00-12.00
Overall L1	18.75

Vectorization ratios

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.75 cycles. At this rate:

3% of peak load performance is reached (8.53 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.13 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5951a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 595601 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x461>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x58(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x40(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x8(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
LEA (%R10,%RCX,8),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 59560b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x46b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA (,%R8,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R10,%R9,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
KXNORB %K0,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV (%R13),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 595cc7 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xb27>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 595fb9 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe19>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R15,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA %XMM1,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R12,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 5951dd <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x3d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMPQ $0x1,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
LEA (,%R8,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%R13),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
KXNORB %K1,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 595c07 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xa67>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,0x38(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 596034 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R11,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
KXNORB %K0,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVQ %R15,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %R12,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R13,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RBX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x7,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 596021 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59600f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe6f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59600b <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe6b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596007 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe67>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596003 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe63>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595fff <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xe5f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNE %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R13,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB $0x8,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x3,%R15	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
INC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 596096 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xef6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596089 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596085 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596081 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xee1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 59607d <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xedd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 596079 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0xed9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD $0x8,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVNE %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 5955de <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3+0x43e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.3–	0.06	0.03
▼Loop 3100 - csr_matvec.c:183-196 - exec–	0.06	0.03
○Loop 3101 - csr_matvec.c:194-195 - exec	0.00	0.00
▼Loop 3094 - csr_matvec.c:183-196 - exec–	0.00	0.00
○Loop 3095 - csr_matvec.c:194-195 - exec	0.00	0.00
▼Loop 3098 - csr_matvec.c:183-204 - exec–	0.00	0.00
▼Loop 3097 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 3099 - csr_matvec.c:202-203 - exec	0.00	0.00
○Loop 3102 - csr_matvec.c:193-193 - exec	0.00	0.00
○Loop 3096 - csr_matvec.c:193-193 - exec	0.00	0.00
▼Loop 3104 - csr_matvec.c:183-204 - exec–	0.00	0.00
▼Loop 3103 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 3105 - csr_matvec.c:202-203 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code