OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2	Module: exec	Source: csr_matvec.c:158-161	Coverage (incl. loops): 0.40% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 158 - 161

--------------------------------------------------------------------------------

158: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

159: #endif

160:             for (i = 0; i < num_rows*num_vectors; i++)

161:                y_data[i] = b_data[i]*temp;

0x594e30 PUSH	%RBP

0x594e31 MOV	%RSP,%RBP

0x594e34 PUSH	%R12

0x594e36 PUSH	%RBX

0x594e37 MOV	%RDI,%RBX

0x594e3a AND	$-0x20,%RSP

0x594e3e CALL	4110b0 <omp_get_num_threads@plt>

0x594e43 MOV	%EAX,%R12D

0x594e46 CALL	4111f0 <omp_get_thread_num@plt>

0x594e4b MOVSXD	%EAX,%RCX

0x594e4e MOV	0x18(%RBX),%RAX

0x594e52 MOVSXD	%R12D,%RSI

0x594e55 IMUL	(%RBX),%RAX

0x594e59 CQTO

0x594e5b IDIV	%RSI

0x594e5e CMP	%RDX,%RCX

0x594e61 JL	595060

0x594e67 IMUL	%RAX,%RCX

0x594e6b ADD	%RCX,%RDX

0x594e6e LEA	(%RAX,%RDX,1),%R10

0x594e72 CMP	%R10,%RDX

0x594e75 JGE	595047

0x594e7b LEA	-0x1(%RAX),%RDI

0x594e7f MOV	0x10(%RBX),%R12

0x594e83 MOV	0x8(%RBX),%R9

0x594e87 VMOVSD	0x20(%RBX),%XMM1

0x594e8c CMP	$0x2,%RDI

0x594e90 JBE	595070

0x594e96 LEA	(,%RDX,8),%RBX

0x594e9e LEA	(%R12,%RBX,1),%RSI

0x594ea2 LEA	0x8(%R9,%RBX,1),%R8

0x594ea7 MOV	%RSI,%R11

0x594eaa SUB	%R8,%R11

0x594ead CMP	$0x10,%R11

0x594eb1 JBE	595070

0x594eb7 MOV	%RAX,%RDI

0x594eba ADD	%R9,%RBX

0x594ebd XOR	%ECX,%ECX

0x594ebf VBROADCASTSD	%XMM1,%YMM0

0x594ec4 SHR	$0x2,%RDI

0x594ec8 SAL	$0x5,%RDI

0x594ecc LEA	-0x20(%RDI),%R8

0x594ed0 SHR	$0x5,%R8

0x594ed4 INC	%R8

0x594ed7 AND	$0x7,%R8D

0x594edb JE	594f6f

0x594ee1 CMP	$0x1,%R8

0x594ee5 JE	594f58

0x594ee7 CMP	$0x2,%R8

0x594eeb JE	594f4a

0x594eed CMP	$0x3,%R8

0x594ef1 JE	594f3c

0x594ef3 CMP	$0x4,%R8

0x594ef7 JE	594f2e

0x594ef9 CMP	$0x5,%R8

0x594efd JE	594f20

0x594eff CMP	$0x6,%R8

0x594f03 JE	594f12

0x594f05 VMULPD	(%RBX),%YMM0,%YMM2

0x594f09 MOV	$0x20,%ECX

0x594f0e VMOVUPD	%YMM2,(%RSI)

0x594f12 VMULPD	(%RBX,%RCX,1),%YMM0,%YMM3

0x594f17 VMOVUPD	%YMM3,(%RSI,%RCX,1)

0x594f1c ADD	$0x20,%RCX

0x594f20 VMULPD	(%RBX,%RCX,1),%YMM0,%YMM4

0x594f25 VMOVUPD	%YMM4,(%RSI,%RCX,1)

0x594f2a ADD	$0x20,%RCX

0x594f2e VMULPD	(%RBX,%RCX,1),%YMM0,%YMM5

0x594f33 VMOVUPD	%YMM5,(%RSI,%RCX,1)

0x594f38 ADD	$0x20,%RCX

0x594f3c VMULPD	(%RBX,%RCX,1),%YMM0,%YMM6

0x594f41 VMOVUPD	%YMM6,(%RSI,%RCX,1)

0x594f46 ADD	$0x20,%RCX

0x594f4a VMULPD	(%RBX,%RCX,1),%YMM0,%YMM7

0x594f4f VMOVUPD	%YMM7,(%RSI,%RCX,1)

0x594f54 ADD	$0x20,%RCX

0x594f58 VMULPD	(%RBX,%RCX,1),%YMM0,%YMM8

0x594f5d VMOVUPD	%YMM8,(%RSI,%RCX,1)

0x594f62 ADD	$0x20,%RCX

0x594f66 CMP	%RDI,%RCX

0x594f69 JE	594ff5

(3093) 0x594f6f VMULPD	(%RBX,%RCX,1),%YMM0,%YMM9

(3093) 0x594f74 VMOVUPD	%YMM9,(%RSI,%RCX,1)

(3093) 0x594f79 VMULPD	0x20(%RBX,%RCX,1),%YMM0,%YMM10

(3093) 0x594f7f VMOVUPD	%YMM10,0x20(%RSI,%RCX,1)

(3093) 0x594f85 VMULPD	0x40(%RBX,%RCX,1),%YMM0,%YMM11

(3093) 0x594f8b VMOVUPD	%YMM11,0x40(%RSI,%RCX,1)

(3093) 0x594f91 VMULPD	0x60(%RBX,%RCX,1),%YMM0,%YMM12

(3093) 0x594f97 VMOVUPD	%YMM12,0x60(%RSI,%RCX,1)

(3093) 0x594f9d VMULPD	0x80(%RBX,%RCX,1),%YMM0,%YMM13

(3093) 0x594fa6 VMOVUPD	%YMM13,0x80(%RSI,%RCX,1)

(3093) 0x594faf VMULPD	0xa0(%RBX,%RCX,1),%YMM0,%YMM14

(3093) 0x594fb8 VMOVUPD	%YMM14,0xa0(%RSI,%RCX,1)

(3093) 0x594fc1 VMULPD	0xc0(%RBX,%RCX,1),%YMM0,%YMM15

(3093) 0x594fca VMOVUPD	%YMM15,0xc0(%RSI,%RCX,1)

(3093) 0x594fd3 VMULPD	0xe0(%RBX,%RCX,1),%YMM0,%YMM2

(3093) 0x594fdc VMOVUPD	%YMM2,0xe0(%RSI,%RCX,1)

(3093) 0x594fe5 ADD	$0x100,%RCX

(3093) 0x594fec CMP	%RDI,%RCX

(3093) 0x594fef JNE	594f6f

0x594ff5 MOV	%RAX,%RBX

0x594ff8 AND	$-0x4,%RBX

0x594ffc ADD	%RBX,%RDX

0x594fff CMP	%RBX,%RAX

0x595002 JE	595050

0x595004 LEA	0x1(%RDX),%RAX

0x595008 VMULSD	(%R9,%RDX,8),%XMM1,%XMM0

0x59500e VMOVSD	%XMM0,(%R12,%RDX,8)

0x595014 CMP	%RAX,%R10

0x595017 JLE	595050

0x595019 LEA	(,%RAX,8),%RSI

0x595021 ADD	$0x2,%RDX

0x595025 VMULSD	(%R9,%RAX,8),%XMM1,%XMM3

0x59502b VMOVSD	%XMM3,(%R12,%RSI,1)

0x595031 CMP	%RDX,%R10

0x595034 JLE	595050

0x595036 VMULSD	0x8(%R9,%RSI,1),%XMM1,%XMM1

0x59503d VMOVSD	%XMM1,0x8(%R12,%RSI,1)

0x595044 VZEROUPPER

0x595047 LEA	-0x10(%RBP),%RSP

0x59504b POP	%RBX

0x59504c POP	%R12

0x59504e POP	%RBP

0x59504f RET

0x595050 VZEROUPPER

0x595053 LEA	-0x10(%RBP),%RSP

0x595057 POP	%RBX

0x595058 POP	%R12

0x59505a POP	%RBP

0x59505b RET

0x59505c NOPL	(%RAX)

0x595060 INC	%RAX

0x595063 XOR	%EDX,%EDX

0x595065 JMP	594e67

0x59506a NOPW	(%RAX,%RAX,1)

0x595070 MOV	%R10,%R11

0x595073 SUB	%RDX,%R11

0x595076 AND	$0x7,%R11D

0x59507a JE	595116

0x595080 CMP	$0x1,%R11

0x595084 JE	5950fe

0x595086 CMP	$0x2,%R11

0x59508a JE	5950ef

0x59508c CMP	$0x3,%R11

0x595090 JE	5950e0

0x595092 CMP	$0x4,%R11

0x595096 JE	5950d1

0x595098 CMP	$0x5,%R11

0x59509c JE	5950c2

0x59509e CMP	$0x6,%R11

0x5950a2 JE	5950b3

0x5950a4 VMULSD	(%R9,%RDX,8),%XMM1,%XMM4

0x5950aa VMOVSD	%XMM4,(%R12,%RDX,8)

0x5950b0 INC	%RDX

0x5950b3 VMULSD	(%R9,%RDX,8),%XMM1,%XMM5

0x5950b9 VMOVSD	%XMM5,(%R12,%RDX,8)

0x5950bf INC	%RDX

0x5950c2 VMULSD	(%R9,%RDX,8),%XMM1,%XMM6

0x5950c8 VMOVSD	%XMM6,(%R12,%RDX,8)

0x5950ce INC	%RDX

0x5950d1 VMULSD	(%R9,%RDX,8),%XMM1,%XMM7

0x5950d7 VMOVSD	%XMM7,(%R12,%RDX,8)

0x5950dd INC	%RDX

0x5950e0 VMULSD	(%R9,%RDX,8),%XMM1,%XMM8

0x5950e6 VMOVSD	%XMM8,(%R12,%RDX,8)

0x5950ec INC	%RDX

0x5950ef VMULSD	(%R9,%RDX,8),%XMM1,%XMM9

0x5950f5 VMOVSD	%XMM9,(%R12,%RDX,8)

0x5950fb INC	%RDX

0x5950fe VMULSD	(%R9,%RDX,8),%XMM1,%XMM10

0x595104 VMOVSD	%XMM10,(%R12,%RDX,8)

0x59510a INC	%RDX

0x59510d CMP	%RDX,%R10

0x595110 JE	595047

(3092) 0x595116 VMULSD	(%R9,%RDX,8),%XMM1,%XMM11

(3092) 0x59511c VMOVSD	%XMM11,(%R12,%RDX,8)

(3092) 0x595122 VMULSD	0x8(%R9,%RDX,8),%XMM1,%XMM12

(3092) 0x595129 VMOVSD	%XMM12,0x8(%R12,%RDX,8)

(3092) 0x595130 VMULSD	0x10(%R9,%RDX,8),%XMM1,%XMM13

(3092) 0x595137 VMOVSD	%XMM13,0x10(%R12,%RDX,8)

(3092) 0x59513e VMULSD	0x18(%R9,%RDX,8),%XMM1,%XMM14

(3092) 0x595145 VMOVSD	%XMM14,0x18(%R12,%RDX,8)

(3092) 0x59514c VMULSD	0x20(%R9,%RDX,8),%XMM1,%XMM15

(3092) 0x595153 VMOVSD	%XMM15,0x20(%R12,%RDX,8)

(3092) 0x59515a VMULSD	0x28(%R9,%RDX,8),%XMM1,%XMM2

(3092) 0x595161 VMOVSD	%XMM2,0x28(%R12,%RDX,8)

(3092) 0x595168 VMULSD	0x30(%R9,%RDX,8),%XMM1,%XMM0

(3092) 0x59516f VMOVSD	%XMM0,0x30(%R12,%RDX,8)

(3092) 0x595176 VMULSD	0x38(%R9,%RDX,8),%XMM1,%XMM3

(3092) 0x59517d VMOVSD	%XMM3,0x38(%R12,%RDX,8)

(3092) 0x595184 ADD	$0x8,%RDX

(3092) 0x595188 CMP	%RDX,%R10

(3092) 0x59518b JNE	595116

0x59518d JMP	595047

0x595192 NOPW	%CS:(%RAX,%RAX,1)

0x59519d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.78+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:158	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:232	exec
○	hypre_BoomerAMGCycle	par_cycle.c:429	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:158-161
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 9.25 cycles (2.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

38% of SSE/AVX loads are used in vector version.
41% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
41% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
6% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:160
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 7 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 38 FP arithmetical operations:

38: multiply

The binary function is loading 344 bytes (43 double precision FP elements). The binary function is storing 304 bytes (38 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	158
nb uops	157
loop length	627
used x86 registers	13
used mmx registers	0
used xmm registers	10
used ymm registers	8
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	15.83	15.83	15.83	15.83	15.83	15.83	10.50	10.50	10.50	10.50	9.00	8.50	0.50	0.00	8.50	8.50
cycles	15.83	15.83	15.83	15.83	15.83	15.83	10.50	10.50	10.50	10.50	9.00	8.50	0.50	0.00	8.50	8.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	15.83
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	38%
load	38%
store	41%
mul	41%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	23%
load	38%
store	41%
mul	41%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	27%
load	27%
store	27%
mul	27%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	20%
load	27%
store	27%
mul	27%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

6% of peak load performance is reached (17.53 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.49 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.63 to 15.83 cycles (1.24x speedup).

ASM code

In the binary file, the address of the function is: 594e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL (%RBX),%RAX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 595060 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595070 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R9,%RBX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595070 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%RDI),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 594f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x13f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x128>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f4a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x11a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f3c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x10c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f2e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xfe>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f12 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xe2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RBX),%YMM0,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM2,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RBX,%RCX,1),%YMM0,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM3,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM4,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM5,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM6,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM7,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594ff5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x1c5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R12,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD 0x8(%R9,%RSI,1),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%R12,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 594e67 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x37>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 595116 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2e6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950fe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950ef <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2bf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950e0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950d1 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950c2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x292>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950b3 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x283>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM9,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	csr_matvec.c:158-161
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 9.25 cycles (2.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

38% of SSE/AVX loads are used in vector version.
41% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
41% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
6% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:160
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:158

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:160

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 38 FP arithmetical operations:

38: multiply

The binary function is loading 344 bytes (43 double precision FP elements). The binary function is storing 304 bytes (38 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	158
nb uops	157
loop length	627
used x86 registers	13
used mmx registers	0
used xmm registers	10
used ymm registers	8
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	15.83	15.83	15.83	15.83	15.83	15.83	10.50	10.50	10.50	10.50	9.00	8.50	0.50	0.00	8.50	8.50
cycles	15.83	15.83	15.83	15.83	15.83	15.83	10.50	10.50	10.50	10.50	9.00	8.50	0.50	0.00	8.50	8.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	15.83
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	38%
load	38%
store	41%
mul	41%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	23%
load	38%
store	41%
mul	41%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	27%
load	27%
store	27%
mul	27%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	20%
load	27%
store	27%
mul	27%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

6% of peak load performance is reached (17.53 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.49 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 594e30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL (%RBX),%RAX	1	0.33	0.33	0.33	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.33	N/A
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 595060 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x230>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RDX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x20(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP $0x2,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595070 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RDX,8),%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R12,%RBX,1),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x8(%R9,%RBX,1),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RSI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %R8,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP $0x10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JBE 595070 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x240>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R9,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VBROADCASTSD %XMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
SHR $0x2,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SAL $0x5,%RDI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA -0x20(%RDI),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SHR $0x5,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 594f6f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x13f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f58 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x128>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f4a <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x11a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f3c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x10c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f2e <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xfe>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594f12 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0xe2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULPD (%RBX),%YMM0,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV $0x20,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVUPD %YMM2,(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMULPD (%RBX,%RCX,1),%YMM0,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM3,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM4,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM5,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM6,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM7,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULPD (%RBX,%RCX,1),%YMM0,%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVUPD %YMM8,(%RSI,%RCX,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
ADD $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 594ff5 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x1c5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RDX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM0,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x2,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RAX,8),%XMM1,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM3,(%R12,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 595050 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x220>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD 0x8(%R9,%RSI,1),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM1,0x8(%R12,%RSI,1)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x10(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 594e67 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x37>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
AND $0x7,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JE 595116 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2e6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x1,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950fe <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x2,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950ef <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2bf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x3,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950e0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950d1 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x2a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x5,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950c2 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x292>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x6,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 5950b3 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x283>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM4,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM5,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM6,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM7,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM8,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM9,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSD (%R9,%RDX,8),%XMM1,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VMOVSD %XMM10,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 595047 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2+0x217>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.2–	0.40	0.21
○Loop 3093 - csr_matvec.c:161-161 - exec	0.40	0.19
○Loop 3092 - csr_matvec.c:161-161 - exec	0.00	0.00

Report Configuration

Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code