OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 1.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x5536b0 PUSH	%RBP

0x5536b1 MOV	%RDI,%RCX

0x5536b4 MOV	%RSP,%RBP

0x5536b7 PUSH	%R15

0x5536b9 PUSH	%R14

0x5536bb PUSH	%R13

0x5536bd PUSH	%R12

0x5536bf PUSH	%RBX

0x5536c0 SUB	$0xe8,%RSP

0x5536c7 MOV	0xf0(%RDI),%RAX

0x5536ce MOV	0xe8(%RDI),%R11

0x5536d5 MOV	0xe0(%RDI),%RDX

0x5536dc MOV	0xd8(%RDI),%RBX

0x5536e3 MOV	0xd0(%RDI),%RSI

0x5536ea MOV	0xc8(%RDI),%R8

0x5536f1 MOV	0xc0(%RDI),%R9

0x5536f8 MOV	0xb0(%RDI),%R10

0x5536ff VMOVSD	0xf8(%RDI),%XMM2

0x553707 VMOVSD	%XMM2,-0xa8(%RBP)

0x55370f MOV	%RAX,-0xf0(%RBP)

0x553716 MOV	%R11,-0x78(%RBP)

0x55371a MOV	%RDX,-0xc0(%RBP)

0x553721 MOV	%RBX,-0x100(%RBP)

0x553728 MOV	%RSI,-0x108(%RBP)

0x55372f MOV	%R8,-0xc8(%RBP)

0x553736 MOV	%R9,-0x110(%RBP)

0x55373d MOV	%R10,-0x58(%RBP)

0x553741 MOV	0xa0(%RDI),%R12

0x553748 MOV	0x80(%RDI),%R13

0x55374f MOV	0x78(%RDI),%R14

0x553753 MOV	0x70(%RDI),%RAX

0x553757 MOV	0x68(%RDI),%R11

0x55375b MOV	0x38(%RDI),%R8

0x55375f MOV	0x30(%RDI),%R9

0x553763 MOV	0x20(%RCX),%R10

0x553767 MOV	0x48(%RDI),%RSI

0x55376b MOV	0x58(%RDI),%RBX

0x55376f MOV	0x60(%RDI),%RDX

0x553773 MOV	0x98(%RDI),%R15

0x55377a MOV	%R12,-0x48(%RBP)

0x55377e MOV	%R13,-0x60(%RBP)

0x553782 MOV	0x88(%RDI),%R12

0x553789 MOV	0x50(%RDI),%R13

0x55378d MOV	%R14,-0x88(%RBP)

0x553794 MOV	%RAX,-0x40(%RBP)

0x553798 MOV	0x40(%RDI),%R14

0x55379c MOV	0x18(%RCX),%RAX

0x5537a0 MOV	0x28(%RDI),%RDI

0x5537a4 MOV	%R11,-0xe8(%RBP)

0x5537ab MOV	0x10(%RCX),%R11

0x5537af MOV	%R8,-0x70(%RBP)

0x5537b3 MOV	%R9,-0x38(%RBP)

0x5537b7 MOV	%R10,-0xb8(%RBP)

0x5537be MOV	%RSI,-0x90(%RBP)

0x5537c5 MOV	%RBX,-0x68(%RBP)

0x5537c9 MOV	%RDX,-0xd0(%RBP)

0x5537d0 MOV	%RAX,-0xe0(%RBP)

0x5537d7 MOV	%R11,-0x98(%RBP)

0x5537de MOV	%RDI,-0xd8(%RBP)

0x5537e5 MOV	0x8(%RCX),%RDX

0x5537e9 MOV	(%RCX),%RBX

0x5537ec MOV	%RCX,-0x50(%RBP)

0x5537f0 MOV	%RDX,-0x80(%RBP)

0x5537f4 MOV	%RBX,-0xa0(%RBP)

0x5537fb CALL	5a9ce0 <hypre_GetThreadNum>

0x553800 MOV	%RAX,%RBX

0x553803 CALL	5a9cd0 <hypre_NumActiveThreads>

0x553808 MOV	-0x50(%RBP),%R9

0x55380c MOV	-0x70(%RBP),%R10

0x553810 MOV	%RAX,%RCX

0x553813 MOV	-0x38(%RBP),%RAX

0x553817 MOV	%RBX,%R8

0x55381a MOV	-0x78(%RBP),%R11

0x55381e VMOVSD	-0xa8(%RBP),%XMM5

0x553826 CQTO

0x553828 IDIV	%RCX

0x55382b IMUL	%RAX,%R8

0x55382f ADD	%R8,%RAX

0x553832 CMP	%RDX,%RBX

0x553835 JGE	553e5b

0x55383b LEA	(%RBX,%R8,1),%RCX

0x55383f LEA	0x1(%RBX,%RAX,1),%RDX

0x553844 MOV	%RCX,%RAX

0x553847 MOV	%RCX,-0x78(%RBP)

0x55384b MOV	0x90(%R9),%RBX

0x553852 MOV	0xa8(%R9),%R8

0x553859 SAL	$0x3,%RAX

0x55385d MOV	(%RBX),%RSI

0x553860 MOV	(%R8),%RDI

0x553863 MOV	-0x40(%RBP),%R8

0x553867 MOV	(%RSI,%RAX,1),%RBX

0x55386b MOV	(%RDI,%RAX,1),%RCX

0x55386f MOV	0xb8(%R9),%RAX

0x553876 MOV	(%RAX),%RSI

0x553879 MOV	%RCX,-0x38(%RBP)

0x55387d OR	%RSI,%R8

0x553880 JNE	553dcf

0x553886 XOR	%EDI,%EDI

0x553888 CMP	%RDX,-0x78(%RBP)

0x55388c JGE	553db9

0x553892 CMPQ	$0,-0xf0(%RBP)

0x55389a VMOVQ	%R11,%XMM15

0x55389f VMOVQ	%R15,%XMM11

0x5538a4 MOV	%RDX,-0xf8(%RBP)

0x5538ab VMOVQ	%R12,%XMM12

0x5538b0 VMOVQ	%R13,%XMM13

0x5538b5 VMOVQ	%R14,%XMM14

0x5538ba VMOVQ	%R10,%XMM7

0x5538bf JNE	553a13

    (2488) 0x5538c5 VMOVQ	%XMM7,%RDX

    (2488) 0x5538ca MOV	%RBX,-0x70(%RBP)

    (2488) 0x5538ce TEST	%RDX,%RDX

    (2488) 0x5538d1 JNE	553a4e

  (2486) 0x5538d7 MOV	-0x38(%RBP),%R15

    (2488) 0x5538db MOV	-0x80(%RBP),%R12

    (2488) 0x5538df MOV	-0x78(%RBP),%R8

    (2488) 0x5538e3 MOV	(%R12,%R8,8),%R9

    (2488) 0x5538e7 CMP	0x8(%R12,%R8,8),%R9

    (2488) 0x5538ec JGE	5539e8

    (2488) 0x5538f2 MOV	-0xe8(%RBP),%R12

    (2488) 0x5538f9 MOV	-0x70(%RBP),%RAX

    (2488) 0x5538fd VMOVDQA	%XMM11,%XMM2

    (2488) 0x553901 VMOVQ	%XMM12,%R10

    (2488) 0x553906 VMOVQ	%XMM13,%R13

    (2488) 0x55390b VMOVQ	%XMM14,%R11

    (2488) 0x553910 MOV	%R15,-0xa8(%RBP)

    (2488) 0x553917 MOV	%R9,-0x50(%RBP)

    (2488) 0x55391b NOPL	(%RAX,%RAX,1)

      (2492) 0x553920 MOV	-0x50(%RBP),%RCX

      (2492) 0x553924 MOV	-0x98(%RBP),%RDX

      (2492) 0x55392b MOV	-0x90(%RBP),%R15

      (2492) 0x553932 MOV	-0xa0(%RBP),%R14

      (2492) 0x553939 MOV	(%RDX,%RCX,8),%RSI

      (2492) 0x55393d VMOVSD	(%R14,%RCX,8),%XMM8

      (2492) 0x553943 MOV	%RAX,%RCX

      (2492) 0x553946 LEA	(,%RSI,8),%R8

      (2492) 0x55394e LEA	0x8(%R8),%R9

      (2492) 0x553952 MOV	(%R15,%R8,1),%RDX

      (2492) 0x553956 MOV	%R9,-0x70(%RBP)

      (2492) 0x55395a LEA	0x8(%R15,%R8,1),%R9

      (2492) 0x55395f MOV	(%R9),%R14

      (2492) 0x553962 MOV	%R14,%RSI

      (2492) 0x553965 CMP	%R14,%RDX

      (2492) 0x553968 JGE	5539b4

      (2492) 0x55396a NOPW	%CS:(%RAX,%RAX,1)

      (2492) 0x553975 NOPW	%CS:(%RAX,%RAX,1)

        (2494) 0x553980 MOV	(%R13,%RDX,8),%R15

        (2494) 0x553985 VMULSD	(%R11,%RDX,8),%XMM8,%XMM1

        (2494) 0x55398b LEA	(%RDI,%R15,8),%R14

        (2494) 0x55398f MOV	(%R14),%RAX

        (2494) 0x553992 CMP	%RAX,%RBX

        (2494) 0x553995 JG	553c30

        (2494) 0x55399b LEA	(%R10,%RAX,8),%R15

        (2494) 0x55399f INC	%RDX

        (2494) 0x5539a2 VADDSD	(%R15),%XMM1,%XMM0

        (2494) 0x5539a7 VMOVSD	%XMM0,(%R15)

        (2494) 0x5539ac CMP	%RSI,%RDX

        (2494) 0x5539af JL	553980

      (2492) 0x5539b1 MOV	%RCX,%RAX

      (2492) 0x5539b4 CMPQ	$0,-0x88(%RBP)

      (2492) 0x5539bc JNE	553c70

      (2492) 0x5539c2 MOV	-0x80(%RBP),%R9

      (2492) 0x5539c6 MOV	-0x78(%RBP),%RDX

      (2492) 0x5539ca INCQ	-0x50(%RBP)

      (2492) 0x5539ce MOV	-0x50(%RBP),%RCX

      (2492) 0x5539d2 CMP	%RCX,0x8(%R9,%RDX,8)

      (2492) 0x5539d7 JG	553920

    (2488) 0x5539dd MOV	-0xa8(%RBP),%R15

    (2488) 0x5539e4 MOV	%RAX,-0x70(%RBP)

    (2488) 0x5539e8 INCQ	-0x78(%RBP)

    (2488) 0x5539ec MOV	-0x78(%RBP),%RBX

    (2488) 0x5539f0 CMP	%RBX,-0xf8(%RBP)

    (2488) 0x5539f7 JE	553db9

    (2488) 0x5539fd CMPQ	$0,-0xf0(%RBP)

    (2488) 0x553a05 MOV	-0x70(%RBP),%RBX

    (2488) 0x553a09 MOV	%R15,-0x38(%RBP)

    (2488) 0x553a0d JE	5538c5

(2491) 0x553a13 MOV	-0x78(%RBP),%R15

(2491) 0x553a17 LEA	(,%RBX,8),%R12

(2491) 0x553a1f VMOVQ	%XMM12,%R13

(2491) 0x553a24 VMOVQ	%XMM11,%R14

(2491) 0x553a29 LEA	0x1(%RBX),%R11

(2491) 0x553a2d VMOVQ	%XMM7,%RDX

(2491) 0x553a32 MOV	%R11,-0x70(%RBP)

(2491) 0x553a36 MOV	%RBX,(%RDI,%R15,8)

(2491) 0x553a3a VMOVSD	%XMM5,(%R13,%R12,1)

(2491) 0x553a41 MOV	%R15,(%R14,%R12,1)

(2491) 0x553a45 TEST	%RDX,%RDX

(2491) 0x553a48 JE	5538d7

    (2488) 0x553a4e MOV	-0xb8(%RBP),%R9

    (2488) 0x553a55 MOV	-0x78(%RBP),%RSI

    (2488) 0x553a59 MOV	(%R9,%RSI,8),%RAX

    (2488) 0x553a5d CMP	0x8(%R9,%RSI,8),%RAX

    (2488) 0x553a62 JGE	5538d7

    (2488) 0x553a68 MOV	-0x38(%RBP),%RCX

    (2488) 0x553a6c MOV	-0x100(%RBP),%R15

    (2488) 0x553a73 MOV	-0x110(%RBP),%R8

    (2488) 0x553a7a MOV	-0x108(%RBP),%R14

    (2488) 0x553a81 VMOVQ	%XMM15,%R12

    (2488) 0x553a86 VMOVDQA	%XMM11,%XMM8

    (2488) 0x553a8b MOV	%RBX,%R10

    (2488) 0x553a8e MOV	%RAX,-0x50(%RBP)

    (2488) 0x553a92 VMOVQ	%XMM12,%R9

    (2488) 0x553a97 MOV	%RCX,-0xb0(%RBP)

    (2488) 0x553a9e XCHG	%AX,%AX

      (2487) 0x553aa0 MOV	-0x50(%RBP),%R13

      (2487) 0x553aa4 MOV	-0xd8(%RBP),%R11

      (2487) 0x553aab MOV	-0xe0(%RBP),%RBX

      (2487) 0x553ab2 MOV	(%R11,%R13,8),%RDX

      (2487) 0x553ab6 VMOVSD	(%RBX,%R13,8),%XMM1

      (2487) 0x553abc MOV	-0xc0(%RBP),%RBX

      (2487) 0x553ac3 MOV	%RDX,-0xa8(%RBP)

      (2487) 0x553aca SAL	$0x3,%RDX

      (2487) 0x553ace LEA	0x8(%RBX,%RDX,1),%R13

      (2487) 0x553ad3 MOV	(%RBX,%RDX,1),%RAX

      (2487) 0x553ad7 VMOVQ	%RDX,%XMM0

      (2487) 0x553adc LEA	0x8(%RDX),%RSI

      (2487) 0x553ae0 MOV	(%R13),%RDX

      (2487) 0x553ae4 VMOVQ	%R13,%XMM4

      (2487) 0x553ae9 CMP	%RDX,%RAX

      (2487) 0x553aec JGE	553b8d

      (2487) 0x553af2 MOV	%RSI,-0xa8(%RBP)

      (2487) 0x553af9 MOV	-0xb0(%RBP),%RSI

      (2487) 0x553b00 MOV	%RDI,%R11

      (2487) 0x553b03 MOV	%RDX,%RDI

      (2487) 0x553b06 NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553b11 NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553b1c NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553b27 NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553b32 NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553b3d NOPL	(%RAX)

        (2490) 0x553b40 MOV	(%R12,%RAX,8),%R13

        (2490) 0x553b44 MOV	-0x40(%RBP),%RBX

        (2490) 0x553b48 VMULSD	(%R15,%RAX,8),%XMM1,%XMM6

        (2490) 0x553b4e LEA	(%RBX,%R13,1),%RCX

        (2490) 0x553b52 LEA	(%R11,%RCX,8),%RDX

        (2490) 0x553b56 MOV	(%RDX),%RCX

        (2490) 0x553b59 CMP	%RCX,-0x38(%RBP)

        (2490) 0x553b5d JG	553d80

        (2490) 0x553b63 MOV	-0x48(%RBP),%R13

        (2490) 0x553b67 INC	%RAX

        (2490) 0x553b6a LEA	(%R13,%RCX,8),%RBX

        (2490) 0x553b6f VADDSD	(%RBX),%XMM6,%XMM3

        (2490) 0x553b73 VMOVSD	%XMM3,(%RBX)

        (2490) 0x553b77 CMP	%RDI,%RAX

        (2490) 0x553b7a JL	553b40

      (2487) 0x553b7c MOV	%RSI,-0xb0(%RBP)

      (2487) 0x553b83 MOV	-0xa8(%RBP),%RSI

      (2487) 0x553b8a MOV	%R11,%RDI

      (2487) 0x553b8d MOV	-0xc8(%RBP),%R11

      (2487) 0x553b94 VMOVQ	%XMM0,%RAX

      (2487) 0x553b99 LEA	(%R11,%RSI,1),%RBX

      (2487) 0x553b9d MOV	(%R11,%RAX,1),%RAX

      (2487) 0x553ba1 MOV	(%RBX),%RDX

      (2487) 0x553ba4 CMP	%RDX,%RAX

      (2487) 0x553ba7 JGE	553bf6

      (2487) 0x553ba9 MOV	-0x70(%RBP),%RCX

      (2487) 0x553bad MOV	%RDI,%R11

      (2487) 0x553bb0 MOV	%RDX,%RDI

      (2487) 0x553bb3 NOPW	%CS:(%RAX,%RAX,1)

      (2487) 0x553bbe XCHG	%AX,%AX

        (2489) 0x553bc0 MOV	(%R14,%RAX,8),%RSI

        (2489) 0x553bc4 VMULSD	(%R8,%RAX,8),%XMM1,%XMM9

        (2489) 0x553bca LEA	(%R11,%RSI,8),%R13

        (2489) 0x553bce MOV	(%R13),%RDX

        (2489) 0x553bd2 CMP	%RDX,%R10

        (2489) 0x553bd5 JG	553d40

        (2489) 0x553bdb LEA	(%R9,%RDX,8),%RSI

        (2489) 0x553bdf INC	%RAX

        (2489) 0x553be2 VADDSD	(%RSI),%XMM9,%XMM10

        (2489) 0x553be6 VMOVSD	%XMM10,(%RSI)

        (2489) 0x553bea CMP	%RDI,%RAX

        (2489) 0x553bed JL	553bc0

      (2487) 0x553bef MOV	%R11,%RDI

      (2487) 0x553bf2 MOV	%RCX,-0x70(%RBP)

      (2487) 0x553bf6 MOV	-0xb8(%RBP),%R11

      (2487) 0x553bfd MOV	-0x78(%RBP),%RBX

      (2487) 0x553c01 INCQ	-0x50(%RBP)

      (2487) 0x553c05 MOV	-0x50(%RBP),%RAX

      (2487) 0x553c09 CMP	%RAX,0x8(%R11,%RBX,8)

      (2487) 0x553c0e JG	553aa0

    (2488) 0x553c14 MOV	-0xb0(%RBP),%R15

    (2488) 0x553c1b VMOVQ	%R12,%XMM15

    (2488) 0x553c20 MOV	%R10,%RBX

    (2488) 0x553c23 JMP	5538db

0x553c28 NOPL	(%RAX,%RAX,1)

        (2494) 0x553c30 MOV	%RCX,(%R14)

        (2494) 0x553c33 VMOVQ	%XMM2,%RSI

        (2494) 0x553c38 LEA	(,%RCX,8),%R14

        (2494) 0x553c40 INC	%RDX

        (2494) 0x553c43 VMOVSD	%XMM1,(%R10,%R14,1)

        (2494) 0x553c49 MOV	%R15,(%RSI,%R14,1)

        (2494) 0x553c4d MOV	(%R9),%RSI

        (2494) 0x553c50 INC	%RCX

        (2494) 0x553c53 CMP	%RDX,%RSI

        (2494) 0x553c56 JG	553980

      (2492) 0x553c5c JMP	5539b1

0x553c61 NOPW	%CS:(%RAX,%RAX,1)

0x553c6c NOPL	(%RAX)

      (2492) 0x553c70 MOV	-0xd0(%RBP),%R9

      (2492) 0x553c77 MOV	(%R9,%R8,1),%RDX

      (2492) 0x553c7b MOV	-0x70(%RBP),%R8

      (2492) 0x553c7f ADD	%R9,%R8

      (2492) 0x553c82 MOV	(%R8),%R15

      (2492) 0x553c85 CMP	%R15,%RDX

      (2492) 0x553c88 JGE	5539c2

      (2492) 0x553c8e MOV	-0xa8(%RBP),%RCX

      (2492) 0x553c95 MOV	%RAX,-0x70(%RBP)

      (2492) 0x553c99 MOV	%R8,%RAX

      (2492) 0x553c9c NOPL	(%RAX)

        (2493) 0x553ca0 MOV	(%R12,%RDX,8),%R14

        (2493) 0x553ca4 MOV	-0x60(%RBP),%RSI

        (2493) 0x553ca8 MOV	-0x40(%RBP),%R8

        (2493) 0x553cac MOV	(%RSI,%R14,8),%R9

        (2493) 0x553cb0 MOV	-0x68(%RBP),%RSI

        (2493) 0x553cb4 LEA	(%R8,%R9,1),%R14

        (2493) 0x553cb8 VMULSD	(%RSI,%RDX,8),%XMM8,%XMM4

        (2493) 0x553cbd LEA	(%RDI,%R14,8),%R14

        (2493) 0x553cc1 MOV	(%R14),%R8

        (2493) 0x553cc4 CMP	%R8,-0x38(%RBP)

        (2493) 0x553cc8 JG	553d00

        (2493) 0x553cca MOV	-0x48(%RBP),%R9

        (2493) 0x553cce INC	%RDX

        (2493) 0x553cd1 LEA	(%R9,%R8,8),%R14

        (2493) 0x553cd5 VADDSD	(%R14),%XMM4,%XMM6

        (2493) 0x553cda VMOVSD	%XMM6,(%R14)

        (2493) 0x553cdf CMP	%R15,%RDX

        (2493) 0x553ce2 JL	553ca0

      (2492) 0x553ce4 MOV	-0x70(%RBP),%RAX

      (2492) 0x553ce8 MOV	%RCX,-0xa8(%RBP)

      (2492) 0x553cef JMP	5539c2

0x553cf4 NOPW	%CS:(%RAX,%RAX,1)

0x553cff NOP

        (2493) 0x553d00 MOV	-0x48(%RBP),%R8

        (2493) 0x553d04 MOV	-0x58(%RBP),%RSI

        (2493) 0x553d08 LEA	(,%RCX,8),%R15

        (2493) 0x553d10 MOV	%RCX,(%R14)

        (2493) 0x553d13 INC	%RDX

        (2493) 0x553d16 INC	%RCX

        (2493) 0x553d19 VMOVSD	%XMM4,(%R8,%R15,1)

        (2493) 0x553d1f MOV	%R9,(%RSI,%R15,1)

        (2493) 0x553d23 MOV	(%RAX),%R15

        (2493) 0x553d26 CMP	%RDX,%R15

        (2493) 0x553d29 JG	553ca0

      (2492) 0x553d2f MOV	-0x70(%RBP),%RAX

      (2492) 0x553d33 MOV	%RCX,-0xa8(%RBP)

      (2492) 0x553d3a JMP	5539c2

0x553d3f NOP

        (2489) 0x553d40 MOV	%RCX,(%R13)

        (2489) 0x553d44 VMOVQ	%XMM8,%RDI

        (2489) 0x553d49 LEA	(,%RCX,8),%R13

        (2489) 0x553d51 INC	%RAX

        (2489) 0x553d54 VMOVSD	%XMM9,(%R9,%R13,1)

        (2489) 0x553d5a MOV	%RSI,(%RDI,%R13,1)

        (2489) 0x553d5e MOV	(%RBX),%RDI

        (2489) 0x553d61 INC	%RCX

        (2489) 0x553d64 CMP	%RAX,%RDI

        (2489) 0x553d67 JG	553bc0

      (2487) 0x553d6d JMP	553bef

0x553d72 NOPW	%CS:(%RAX,%RAX,1)

0x553d7d NOPL	(%RAX)

        (2490) 0x553d80 MOV	-0x48(%RBP),%RDI

        (2490) 0x553d84 MOV	-0x58(%RBP),%RCX

        (2490) 0x553d88 MOV	%RSI,(%RDX)

        (2490) 0x553d8b LEA	(,%RSI,8),%RDX

        (2490) 0x553d93 INC	%RAX

        (2490) 0x553d96 INC	%RSI

        (2490) 0x553d99 VMOVSD	%XMM6,(%RDI,%RDX,1)

        (2490) 0x553d9e MOV	%R13,(%RCX,%RDX,1)

        (2490) 0x553da2 VMOVQ	%XMM4,%R13

        (2490) 0x553da7 MOV	(%R13),%RDI

        (2490) 0x553dab CMP	%RAX,%RDI

        (2490) 0x553dae JG	553b40

      (2487) 0x553db4 JMP	553b7c

0x553db9 ADD	$0xe8,%RSP

0x553dc0 POP	%RBX

0x553dc1 POP	%R12

0x553dc3 POP	%R13

0x553dc5 POP	%R14

0x553dc7 POP	%R15

0x553dc9 POP	%RBP

0x553dca JMP	5a6cb0

0x553dcf MOV	-0x40(%RBP),%RDI

0x553dd3 MOV	%R9,-0xf8(%RBP)

0x553dda MOV	%R10,-0xb0(%RBP)

0x553de1 MOV	%R11,-0xa8(%RBP)

0x553de8 VMOVSD	%XMM5,-0x70(%RBP)

0x553ded MOV	%RDX,-0x50(%RBP)

0x553df1 ADD	%RSI,%RDI

0x553df4 MOV	$0x8,%ESI

0x553df9 CALL	5a6c20 <hypre_CAlloc>

0x553dfe MOV	-0xf8(%RBP),%R9

0x553e05 MOV	-0x40(%RBP),%R10

0x553e09 MOV	-0x50(%RBP),%RDX

0x553e0d MOV	-0xa8(%RBP),%R11

0x553e14 MOV	%RAX,%RDI

0x553e17 VMOVSD	-0x70(%RBP),%XMM5

0x553e1c MOV	0xb8(%R9),%RSI

0x553e23 ADD	(%RSI),%R10

0x553e26 TEST	%R10,%R10

0x553e29 MOV	-0xb0(%RBP),%R10

0x553e30 JLE	553888

0x553e36 MOV	-0x40(%RBP),%R8

0x553e3a XOR	%EAX,%EAX

0x553e3c NOPL	(%RAX)

(2495) 0x553e40 MOVQ	$-0x1,(%RDI,%RAX,8)

(2495) 0x553e48 MOV	(%RSI),%RCX

(2495) 0x553e4b INC	%RAX

(2495) 0x553e4e ADD	%R8,%RCX

(2495) 0x553e51 CMP	%RAX,%RCX

(2495) 0x553e54 JG	553e40

0x553e56 JMP	553888

0x553e5b LEA	(%RDX,%R8,1),%RDI

0x553e5f LEA	(%RDX,%RAX,1),%RDX

0x553e63 MOV	%RDI,-0x78(%RBP)

0x553e67 MOV	%RDI,%RAX

0x553e6a JMP	55384b

0x553e6f NOP

Coverage (%)	Name	Source Location	Module
►97.05+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.95+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_ParMatmul	par_csr_matop.c:998	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 6.00 cycles (3.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 23.50 to 2.94 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 23.50 to 18.63 cycles (1.26x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:844
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:847

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:844

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 440 bytes. The binary function is storing 280 bytes.

General properties

nb instructions	155
nb uops	149
loop length	744
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.63 cycles
front end	18.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	1.00	1.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.63
Dispatch	23.50
DIV/SQRT	7.00-12.00
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

7% of peak load performance is reached (18.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5536b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0xf0(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xe0(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc8(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0xf8(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x80(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x78(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RCX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x88(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R14,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a9cd0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x78(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD -0xa8(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 553e5b <hypre_ParMatmul._omp_fn.3+0x7ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RBX,%R8,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RBX,%RAX,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%R9),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%R9),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI,%RAX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI,%RAX,1),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%R9),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
OR %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 553dcf <hypre_ParMatmul._omp_fn.3+0x71f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDX,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 553db9 <hypre_ParMatmul._omp_fn.3+0x709>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
VMOVQ %R11,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R15,%XMM11	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %R12,%XMM12	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R13,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R10,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
JNE 553a13 <hypre_ParMatmul._omp_fn.3+0x363>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a6cb0 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0xf8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xa8(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x70(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD (%RSI),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %R10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xb0(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 553888 <hypre_ParMatmul._omp_fn.3+0x1d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 553888 <hypre_ParMatmul._omp_fn.3+0x1d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RDX,%R8,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 55384b <hypre_ParMatmul._omp_fn.3+0x19b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 6.00 cycles (3.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 23.50 to 18.63 cycles (1.26x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:857
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:840
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:841

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:844
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:847

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:844

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 440 bytes. The binary function is storing 280 bytes.

General properties

nb instructions	155
nb uops	149
loop length	744
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	28

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.63 cycles
front end	18.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	1.00	1.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	18.63
Dispatch	23.50
DIV/SQRT	7.00-12.00
Overall L1	23.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

7% of peak load performance is reached (18.72 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (11.91 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5536b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0xf0(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xe0(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc8(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb0(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0xf8(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM2,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x80(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x78(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x70(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x68(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x30(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RCX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R12,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x88(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R14,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x8(%RCX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a9cd0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x78(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD -0xa8(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
IMUL %RAX,%R8	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 553e5b <hypre_ParMatmul._omp_fn.3+0x7ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RBX,%R8,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RBX,%RAX,1),%RDX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%R9),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%R9),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI,%RAX,1),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI,%RAX,1),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%R9),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
OR %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 553dcf <hypre_ParMatmul._omp_fn.3+0x71f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDX,-0x78(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 553db9 <hypre_ParMatmul._omp_fn.3+0x709>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,-0xf0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
VMOVQ %R11,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R15,%XMM11	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
MOV %RDX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %R12,%XMM12	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R13,%XMM13	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R14,%XMM14	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R10,%XMM7	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
JNE 553a13 <hypre_ParMatmul._omp_fn.3+0x363>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a6cb0 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM5,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RSI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0xf8(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xa8(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD -0x70(%RBP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb8(%R9),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD (%RSI),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
TEST %R10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0xb0(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 553888 <hypre_ParMatmul._omp_fn.3+0x1d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 553888 <hypre_ParMatmul._omp_fn.3+0x1d8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA (%RDX,%R8,1),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 55384b <hypre_ParMatmul._omp_fn.3+0x19b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	1.33	0.69
○Loop 2495 - par_csr_matop.c:858-859 - exec	0.01	0.01
▼Loop 2491 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2486 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2488 - par_csr_matop.c:865-989 - exec–	0.02	0.01
▼Loop 2492 - par_csr_matop.c:937-989 - exec–	0.40	0.19
○Loop 2494 - par_csr_matop.c:946-965 - exec	0.89	0.42
○Loop 2493 - par_csr_matop.c:970-989 - exec	0.00	0.01
▼Loop 2487 - par_csr_matop.c:888-928 - exec–	0.00	0.01
○Loop 2490 - par_csr_matop.c:897-915 - exec	0.00	0.01
○Loop 2489 - par_csr_matop.c:917-928 - exec	0.00	0.01

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