OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage (incl. loops): 48.36% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x527740 PUSH	%RBP

0x527741 MOV	%RSP,%RBP

0x527744 PUSH	%R15

0x527746 PUSH	%R14

0x527748 PUSH	%R13

0x52774a PUSH	%R12

0x52774c PUSH	%RBX

0x52774d MOV	%RDI,%RBX

0x527750 AND	$-0x20,%RSP

0x527754 CALL	4110b0 <omp_get_num_threads@plt>

0x527759 MOV	%EAX,%R12D

0x52775c CALL	4111f0 <omp_get_thread_num@plt>

0x527761 MOVSXD	%EAX,%RCX

0x527764 MOV	0x40(%RBX),%RAX

0x527768 MOVSXD	%R12D,%RSI

0x52776b CQTO

0x52776d IDIV	%RSI

0x527770 CMP	%RDX,%RCX

0x527773 JL	527d80

0x527779 IMUL	%RAX,%RCX

0x52777d ADD	%RCX,%RDX

0x527780 ADD	%RDX,%RAX

0x527783 CMP	%RAX,%RDX

0x527786 JGE	527d68

0x52778c VMOVQ	0x50(%RBX),%XMM11

0x527791 VMOVQ	0x48(%RBX),%XMM8

0x527796 MOV	0x60(%RBX),%R10

0x52779a MOV	0x58(%RBX),%R9

0x52779e VMOVQ	0x38(%RBX),%XMM6

0x5277a3 VMOVQ	0x30(%RBX),%XMM5

0x5277a8 MOV	0x18(%RBX),%R12

0x5277ac MOV	0x10(%RBX),%R11

0x5277b0 VMOVQ	0x28(%RBX),%XMM7

0x5277b5 VMOVQ	0x20(%RBX),%XMM4

0x5277ba KXNORB	%K1,%K1,%K1

0x5277be VMOVSD	0x68(%RBX),%XMM3

0x5277c3 VMOVQ	(%RBX),%XMM9

0x5277c7 VMOVSD	0x8(%RBX),%XMM10

0x5277cc JMP	5277ec

0x5277ce NOPW	%CS:(%RAX,%RAX,1)

0x5277d9 NOPL	(%RAX)

(2134) 0x5277e0 INC	%RDX

(2134) 0x5277e3 CMP	%RDX,%RAX

(2134) 0x5277e6 JE	527d65

(2134) 0x5277ec MOV	(%R12,%RDX,8),%R8

(2134) 0x5277f0 LEA	(,%R8,8),%RCX

(2134) 0x5277f8 LEA	(%R11,%RCX,1),%RSI

(2134) 0x5277fc VCOMISD	(%RSI),%XMM3

(2134) 0x527800 JE	5277e0

(2134) 0x527802 MOV	0x8(%R12,%RDX,8),%R14

(2134) 0x527807 VMOVQ	%XMM11,%RDI

(2134) 0x52780c VMOVSD	(%RDI,%RDX,8),%XMM0

(2134) 0x527811 CMP	%R14,%R8

(2134) 0x527814 JGE	527a90

(2134) 0x52781a MOV	%R14,%R13

(2134) 0x52781d SUB	%R8,%R13

(2134) 0x527820 LEA	-0x1(%R13),%R15

(2134) 0x527824 CMP	$0x2,%R15

(2134) 0x527828 JBE	527a44

(2134) 0x52782e MOV	%R13,%R15

(2134) 0x527831 VMOVQ	%XMM4,%RBX

(2134) 0x527836 VXORPD	%XMM1,%XMM1,%XMM1

(2134) 0x52783a SHR	$0x2,%R15

(2134) 0x52783e SAL	$0x5,%R15

(2134) 0x527842 LEA	(%RBX,%RCX,1),%RDI

(2134) 0x527846 LEA	-0x20(%R15),%RBX

(2134) 0x52784a XOR	%ECX,%ECX

(2134) 0x52784c SHR	$0x5,%RBX

(2134) 0x527850 INC	%RBX

(2134) 0x527853 AND	$0x7,%EBX

(2134) 0x527856 JE	527931

(2134) 0x52785c CMP	$0x1,%RBX

(2134) 0x527860 JE	52790e

(2134) 0x527866 CMP	$0x2,%RBX

(2134) 0x52786a JE	5278f4

(2134) 0x527870 CMP	$0x3,%RBX

(2134) 0x527874 JE	5278da

(2134) 0x527876 CMP	$0x4,%RBX

(2134) 0x52787a JE	5278c0

(2134) 0x52787c CMP	$0x5,%RBX

(2134) 0x527880 JE	5278a6

(2134) 0x527882 CMP	$0x6,%RBX

(2134) 0x527886 JNE	527d90

(2134) 0x52788c VMOVDQU	(%RDI,%RCX,1),%YMM13

(2134) 0x527891 KMOVB	%K1,%K7

(2134) 0x527895 VGATHERQPD	(%R9,%YMM13,8),%YMM14{%K7}

(2134) 0x52789c VFNMADD231PD	(%RSI,%RCX,1),%YMM14,%YMM1

(2134) 0x5278a2 ADD	$0x20,%RCX

(2134) 0x5278a6 VMOVDQU	(%RDI,%RCX,1),%YMM15

(2134) 0x5278ab KMOVB	%K1,%K5

(2134) 0x5278af VGATHERQPD	(%R9,%YMM15,8),%YMM12{%K5}

(2134) 0x5278b6 VFNMADD231PD	(%RSI,%RCX,1),%YMM12,%YMM1

(2134) 0x5278bc ADD	$0x20,%RCX

(2134) 0x5278c0 VMOVDQU	(%RDI,%RCX,1),%YMM13

(2134) 0x5278c5 KMOVB	%K1,%K2

(2134) 0x5278c9 VGATHERQPD	(%R9,%YMM13,8),%YMM2{%K2}

(2134) 0x5278d0 VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

(2134) 0x5278d6 ADD	$0x20,%RCX

(2134) 0x5278da VMOVDQU	(%RDI,%RCX,1),%YMM14

(2134) 0x5278df KMOVB	%K1,%K4

(2134) 0x5278e3 VGATHERQPD	(%R9,%YMM14,8),%YMM15{%K4}

(2134) 0x5278ea VFNMADD231PD	(%RSI,%RCX,1),%YMM15,%YMM1

(2134) 0x5278f0 ADD	$0x20,%RCX

(2134) 0x5278f4 VMOVDQU	(%RDI,%RCX,1),%YMM12

(2134) 0x5278f9 KMOVB	%K1,%K6

(2134) 0x5278fd VGATHERQPD	(%R9,%YMM12,8),%YMM13{%K6}

(2134) 0x527904 VFNMADD231PD	(%RSI,%RCX,1),%YMM13,%YMM1

(2134) 0x52790a ADD	$0x20,%RCX

(2134) 0x52790e VMOVDQU	(%RDI,%RCX,1),%YMM14

(2134) 0x527913 KMOVB	%K1,%K3

(2134) 0x527917 VGATHERQPD	(%R9,%YMM14,8),%YMM2{%K3}

(2134) 0x52791e VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

(2134) 0x527924 ADD	$0x20,%RCX

(2134) 0x527928 CMP	%R15,%RCX

(2134) 0x52792b JE	527a17

  (2136) 0x527931 VMOVDQU	(%RDI,%RCX,1),%YMM15

  (2136) 0x527936 VMOVDQU	0x20(%RDI,%RCX,1),%YMM12

  (2136) 0x52793c KMOVB	%K1,%K7

  (2136) 0x527940 KMOVB	%K1,%K5

  (2136) 0x527944 VMOVDQU	0x40(%RDI,%RCX,1),%YMM14

  (2136) 0x52794a KMOVB	%K1,%K2

  (2136) 0x52794e KMOVB	%K1,%K4

  (2136) 0x527952 KMOVB	%K1,%K6

  (2136) 0x527956 KMOVB	%K1,%K3

  (2136) 0x52795a VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K7}

  (2136) 0x527961 VMOVDQU	0x60(%RDI,%RCX,1),%YMM15

  (2136) 0x527967 VFNMADD132PD	(%RSI,%RCX,1),%YMM1,%YMM13

  (2136) 0x52796d KMOVB	%K1,%K7

  (2136) 0x527971 VGATHERQPD	(%R9,%YMM12,8),%YMM1{%K5}

  (2136) 0x527978 VMOVDQU	0x80(%RDI,%RCX,1),%YMM12

  (2136) 0x527981 VFNMADD132PD	0x20(%RSI,%RCX,1),%YMM13,%YMM1

  (2136) 0x527988 VGATHERQPD	(%R9,%YMM14,8),%YMM2{%K2}

  (2136) 0x52798f VFNMADD132PD	0x40(%RSI,%RCX,1),%YMM1,%YMM2

  (2136) 0x527996 KMOVB	%K1,%K5

  (2136) 0x52799a VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K4}

  (2136) 0x5279a1 VMOVDQU	0xc0(%RDI,%RCX,1),%YMM15

  (2136) 0x5279aa VFNMADD132PD	0x60(%RSI,%RCX,1),%YMM2,%YMM13

  (2136) 0x5279b1 VMOVDQU	0xa0(%RDI,%RCX,1),%YMM2

  (2136) 0x5279ba VGATHERQPD	(%R9,%YMM12,8),%YMM14{%K6}

  (2136) 0x5279c1 VMOVDQU	0xe0(%RDI,%RCX,1),%YMM12

  (2136) 0x5279ca VFNMADD132PD	0x80(%RSI,%RCX,1),%YMM13,%YMM14

  (2136) 0x5279d4 VGATHERQPD	(%R9,%YMM2,8),%YMM1{%K3}

  (2136) 0x5279db VGATHERQPD	(%R9,%YMM15,8),%YMM13{%K7}

  (2136) 0x5279e2 VFNMADD132PD	0xa0(%RSI,%RCX,1),%YMM14,%YMM1

  (2136) 0x5279ec VFNMADD132PD	0xc0(%RSI,%RCX,1),%YMM1,%YMM13

  (2136) 0x5279f6 VGATHERQPD	(%R9,%YMM12,8),%YMM1{%K5}

  (2136) 0x5279fd VFNMADD132PD	0xe0(%RSI,%RCX,1),%YMM13,%YMM1

  (2136) 0x527a07 ADD	$0x100,%RCX

  (2136) 0x527a0e CMP	%R15,%RCX

  (2136) 0x527a11 JNE	527931

(2134) 0x527a17 VEXTRACTF64X2	$0x1,%YMM1,%XMM14

(2134) 0x527a1e VADDPD	%XMM1,%XMM14,%XMM2

(2134) 0x527a22 VUNPCKHPD	%XMM2,%XMM2,%XMM15

(2134) 0x527a26 VADDPD	%XMM2,%XMM15,%XMM13

(2134) 0x527a2a VADDSD	%XMM13,%XMM0,%XMM0

(2134) 0x527a2f TEST	$0x3,%R13B

(2134) 0x527a33 JE	527a90

(2134) 0x527a35 AND	$-0x4,%R13

(2134) 0x527a39 ADD	%R13,%R8

(2134) 0x527a3c LEA	(,%R8,8),%RCX

(2134) 0x527a44 VMOVQ	%XMM4,%R13

(2134) 0x527a49 LEA	0x1(%R8),%RDI

(2134) 0x527a4d MOV	(%R13,%RCX,1),%RSI

(2134) 0x527a52 VMOVSD	(%R9,%RSI,8),%XMM12

(2134) 0x527a58 VFNMADD231SD	(%R11,%RCX,1),%XMM12,%XMM0

(2134) 0x527a5e CMP	%R14,%RDI

(2134) 0x527a61 JGE	527a90

(2134) 0x527a63 MOV	0x8(%R13,%RCX,1),%R15

(2134) 0x527a68 ADD	$0x2,%R8

(2134) 0x527a6c VMOVSD	0x8(%R11,%RCX,1),%XMM1

(2134) 0x527a73 VFNMADD231SD	(%R9,%R15,8),%XMM1,%XMM0

(2134) 0x527a79 CMP	%R8,%R14

(2134) 0x527a7c JLE	527a90

(2134) 0x527a7e MOV	0x10(%R13,%RCX,1),%R14

(2134) 0x527a83 VMOVSD	(%R9,%R14,8),%XMM14

(2134) 0x527a89 VFNMADD231SD	0x10(%R11,%RCX,1),%XMM14,%XMM0

(2134) 0x527a90 VMOVQ	%XMM7,%RCX

(2134) 0x527a95 MOV	(%RCX,%RDX,8),%RBX

(2134) 0x527a99 MOV	0x8(%RCX,%RDX,8),%R14

(2134) 0x527a9e CMP	%R14,%RBX

(2134) 0x527aa1 JGE	527d38

(2134) 0x527aa7 MOV	%R14,%R13

(2134) 0x527aaa SUB	%RBX,%R13

(2134) 0x527aad LEA	-0x1(%R13),%RSI

(2134) 0x527ab1 CMP	$0x2,%RSI

(2134) 0x527ab5 JBE	527cdb

(2134) 0x527abb LEA	(,%RBX,8),%RSI

(2134) 0x527ac3 VMOVQ	%XMM5,%R15

(2134) 0x527ac8 VMOVQ	%XMM6,%RDI

(2134) 0x527acd XOR	%ECX,%ECX

(2134) 0x527acf ADD	%RSI,%RDI

(2134) 0x527ad2 ADD	%R15,%RSI

(2134) 0x527ad5 MOV	%R13,%R15

(2134) 0x527ad8 VXORPD	%XMM1,%XMM1,%XMM1

(2134) 0x527adc SHR	$0x2,%R15

(2134) 0x527ae0 SAL	$0x5,%R15

(2134) 0x527ae4 LEA	-0x20(%R15),%R8

(2134) 0x527ae8 SHR	$0x5,%R8

(2134) 0x527aec INC	%R8

(2134) 0x527aef AND	$0x7,%R8D

(2134) 0x527af3 JE	527bce

(2134) 0x527af9 CMP	$0x1,%R8

(2134) 0x527afd JE	527bab

(2134) 0x527b03 CMP	$0x2,%R8

(2134) 0x527b07 JE	527b91

(2134) 0x527b0d CMP	$0x3,%R8

(2134) 0x527b11 JE	527b77

(2134) 0x527b13 CMP	$0x4,%R8

(2134) 0x527b17 JE	527b5d

(2134) 0x527b19 CMP	$0x5,%R8

(2134) 0x527b1d JE	527b43

(2134) 0x527b1f CMP	$0x6,%R8

(2134) 0x527b23 JNE	527db0

(2134) 0x527b29 VMOVDQU	(%RDI,%RCX,1),%YMM13

(2134) 0x527b2e KMOVB	%K1,%K4

(2134) 0x527b32 VGATHERQPD	(%R10,%YMM13,8),%YMM12{%K4}

(2134) 0x527b39 VFNMADD231PD	(%RSI,%RCX,1),%YMM12,%YMM1

(2134) 0x527b3f ADD	$0x20,%RCX

(2134) 0x527b43 VMOVDQU	(%RDI,%RCX,1),%YMM14

(2134) 0x527b48 KMOVB	%K1,%K6

(2134) 0x527b4c VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K6}

(2134) 0x527b53 VFNMADD231PD	(%RSI,%RCX,1),%YMM15,%YMM1

(2134) 0x527b59 ADD	$0x20,%RCX

(2134) 0x527b5d VMOVDQU	(%RDI,%RCX,1),%YMM13

(2134) 0x527b62 KMOVB	%K1,%K3

(2134) 0x527b66 VGATHERQPD	(%R10,%YMM13,8),%YMM2{%K3}

(2134) 0x527b6d VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

(2134) 0x527b73 ADD	$0x20,%RCX

(2134) 0x527b77 VMOVDQU	(%RDI,%RCX,1),%YMM12

(2134) 0x527b7c KMOVB	%K1,%K7

(2134) 0x527b80 VGATHERQPD	(%R10,%YMM12,8),%YMM14{%K7}

(2134) 0x527b87 VFNMADD231PD	(%RSI,%RCX,1),%YMM14,%YMM1

(2134) 0x527b8d ADD	$0x20,%RCX

(2134) 0x527b91 VMOVDQU	(%RDI,%RCX,1),%YMM15

(2134) 0x527b96 KMOVB	%K1,%K5

(2134) 0x527b9a VGATHERQPD	(%R10,%YMM15,8),%YMM13{%K5}

(2134) 0x527ba1 VFNMADD231PD	(%RSI,%RCX,1),%YMM13,%YMM1

(2134) 0x527ba7 ADD	$0x20,%RCX

(2134) 0x527bab VMOVDQU	(%RDI,%RCX,1),%YMM12

(2134) 0x527bb0 KMOVB	%K1,%K2

(2134) 0x527bb4 VGATHERQPD	(%R10,%YMM12,8),%YMM2{%K2}

(2134) 0x527bbb VFNMADD231PD	(%RSI,%RCX,1),%YMM2,%YMM1

(2134) 0x527bc1 ADD	$0x20,%RCX

(2134) 0x527bc5 CMP	%RCX,%R15

(2134) 0x527bc8 JE	527cb4

  (2135) 0x527bce VMOVDQU	(%RDI,%RCX,1),%YMM14

  (2135) 0x527bd3 VMOVDQU	0x20(%RDI,%RCX,1),%YMM13

  (2135) 0x527bd9 KMOVB	%K1,%K4

  (2135) 0x527bdd KMOVB	%K1,%K6

  (2135) 0x527be1 VMOVDQU	0x40(%RDI,%RCX,1),%YMM12

  (2135) 0x527be7 KMOVB	%K1,%K3

  (2135) 0x527beb KMOVB	%K1,%K7

  (2135) 0x527bef KMOVB	%K1,%K5

  (2135) 0x527bf3 KMOVB	%K1,%K2

  (2135) 0x527bf7 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K4}

  (2135) 0x527bfe VMOVDQU	0x60(%RDI,%RCX,1),%YMM14

  (2135) 0x527c04 VFNMADD132PD	(%RSI,%RCX,1),%YMM1,%YMM15

  (2135) 0x527c0a KMOVB	%K1,%K4

  (2135) 0x527c0e VGATHERQPD	(%R10,%YMM13,8),%YMM1{%K6}

  (2135) 0x527c15 VMOVDQU	0x80(%RDI,%RCX,1),%YMM13

  (2135) 0x527c1e VFNMADD132PD	0x20(%RSI,%RCX,1),%YMM15,%YMM1

  (2135) 0x527c25 VGATHERQPD	(%R10,%YMM12,8),%YMM2{%K3}

  (2135) 0x527c2c VMOVDQU	0xa0(%RDI,%RCX,1),%YMM12

  (2135) 0x527c35 VFNMADD132PD	0x40(%RSI,%RCX,1),%YMM1,%YMM2

  (2135) 0x527c3c KMOVB	%K1,%K6

  (2135) 0x527c40 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K7}

  (2135) 0x527c47 VMOVDQU	0xc0(%RDI,%RCX,1),%YMM14

  (2135) 0x527c50 VFNMADD132PD	0x60(%RSI,%RCX,1),%YMM2,%YMM15

  (2135) 0x527c57 VGATHERQPD	(%R10,%YMM13,8),%YMM2{%K5}

  (2135) 0x527c5e VMOVDQU	0xe0(%RDI,%RCX,1),%YMM13

  (2135) 0x527c67 VFNMADD132PD	0x80(%RSI,%RCX,1),%YMM15,%YMM2

  (2135) 0x527c71 VGATHERQPD	(%R10,%YMM12,8),%YMM1{%K2}

  (2135) 0x527c78 VFNMADD132PD	0xa0(%RSI,%RCX,1),%YMM2,%YMM1

  (2135) 0x527c82 VGATHERQPD	(%R10,%YMM14,8),%YMM15{%K4}

  (2135) 0x527c89 VFNMADD132PD	0xc0(%RSI,%RCX,1),%YMM1,%YMM15

  (2135) 0x527c93 VGATHERQPD	(%R10,%YMM13,8),%YMM1{%K6}

  (2135) 0x527c9a VFNMADD132PD	0xe0(%RSI,%RCX,1),%YMM15,%YMM1

  (2135) 0x527ca4 ADD	$0x100,%RCX

  (2135) 0x527cab CMP	%RCX,%R15

  (2135) 0x527cae JNE	527bce

(2134) 0x527cb4 VEXTRACTF64X2	$0x1,%YMM1,%XMM2

(2134) 0x527cbb VADDPD	%XMM1,%XMM2,%XMM12

(2134) 0x527cbf VUNPCKHPD	%XMM12,%XMM12,%XMM14

(2134) 0x527cc4 VADDPD	%XMM12,%XMM14,%XMM15

(2134) 0x527cc9 VADDSD	%XMM15,%XMM0,%XMM0

(2134) 0x527cce TEST	$0x3,%R13B

(2134) 0x527cd2 JE	527d38

(2134) 0x527cd4 AND	$-0x4,%R13

(2134) 0x527cd8 ADD	%R13,%RBX

(2134) 0x527cdb LEA	(,%RBX,8),%R13

(2134) 0x527ce3 VMOVQ	%XMM6,%RSI

(2134) 0x527ce8 VMOVQ	%XMM5,%RDI

(2134) 0x527ced LEA	0x1(%RBX),%R8

(2134) 0x527cf1 MOV	(%RSI,%R13,1),%R15

(2134) 0x527cf5 VMOVSD	(%RDI,%R13,1),%XMM13

(2134) 0x527cfb VFNMADD231SD	(%R10,%R15,8),%XMM13,%XMM0

(2134) 0x527d01 CMP	%R14,%R8

(2134) 0x527d04 JGE	527d38

(2134) 0x527d06 MOV	0x8(%RSI,%R13,1),%RSI

(2134) 0x527d0b ADD	$0x2,%RBX

(2134) 0x527d0f VMOVSD	0x8(%RDI,%R13,1),%XMM1

(2134) 0x527d16 VMOVQ	%XMM6,%RCX

(2134) 0x527d1b VFNMADD231SD	(%R10,%RSI,8),%XMM1,%XMM0

(2134) 0x527d21 CMP	%R14,%RBX

(2134) 0x527d24 JGE	527d38

(2134) 0x527d26 MOV	0x10(%RCX,%R13,1),%R14

(2134) 0x527d2b VMOVSD	(%R10,%R14,8),%XMM2

(2134) 0x527d31 VFNMADD231SD	0x10(%RDI,%R13,1),%XMM2,%XMM0

(2134) 0x527d38 VMOVQ	%XMM8,%R8

(2134) 0x527d3d VMOVQ	%XMM9,%R13

(2134) 0x527d42 VMULSD	%XMM0,%XMM10,%XMM0

(2134) 0x527d46 VDIVSD	(%R13,%RDX,8),%XMM0,%XMM12

(2134) 0x527d4d VADDSD	(%R8,%RDX,8),%XMM12,%XMM14

(2134) 0x527d53 VMOVSD	%XMM14,(%R8,%RDX,8)

(2134) 0x527d59 INC	%RDX

(2134) 0x527d5c CMP	%RDX,%RAX

(2134) 0x527d5f JNE	5277ec

0x527d65 VZEROUPPER

0x527d68 LEA	-0x28(%RBP),%RSP

0x527d6c POP	%RBX

0x527d6d POP	%R12

0x527d6f POP	%R13

0x527d71 POP	%R14

0x527d73 POP	%R15

0x527d75 POP	%RBP

0x527d76 RET

0x527d77 NOPW	(%RAX,%RAX,1)

0x527d80 INC	%RAX

0x527d83 XOR	%EDX,%EDX

0x527d85 JMP	527779

0x527d8a NOPW	(%RAX,%RAX,1)

(2134) 0x527d90 VMOVDQU	(%RDI),%YMM12

(2134) 0x527d94 KMOVB	%K1,%K3

(2134) 0x527d98 MOV	$0x20,%ECX

(2134) 0x527d9d VGATHERQPD	(%R9,%YMM12,8),%YMM2{%K3}

(2134) 0x527da4 VFNMADD231PD	(%RSI),%YMM2,%YMM1

(2134) 0x527da9 JMP	52788c

0x527dae XCHG	%AX,%AX

(2134) 0x527db0 VMOVDQU	(%RDI),%YMM15

(2134) 0x527db4 KMOVB	%K1,%K2

(2134) 0x527db8 MOV	$0x20,%ECX

(2134) 0x527dbd VGATHERQPD	(%R10,%YMM15,8),%YMM2{%K2}

(2134) 0x527dc4 VFNMADD231PD	(%RSI),%YMM2,%YMM1

(2134) 0x527dc9 JMP	527b29

0x527dce XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.68+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.90+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 6.63 cycles (1.81x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 6.50 cycles (1.85x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes.

General properties

nb instructions	57
nb uops	53
loop length	207
used x86 registers	15
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	4.00	4.00	4.00	4.00	0.50	0.00	0.00	0.50	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	4.00	4.00	4.00	4.00	0.50	0.00	0.00	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	6.63
Dispatch	4.00
DIV/SQRT	7.00-12.00
Overall L1	7.00-12.00

Vectorization ratios

INT

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 527740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x40(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 527d80 <hypre_ParCSRRelaxThreads._omp_fn.1+0x640>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d68 <hypre_ParCSRRelaxThreads._omp_fn.1+0x628>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0x50(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x48(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x58(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
KXNORB %K1,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVSD 0x68(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ (%RBX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 5277ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 527779 <hypre_ParCSRRelaxThreads._omp_fn.1+0x39>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 6.50 cycles (1.85x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 112 bytes.

General properties

nb instructions	57
nb uops	53
loop length	207
used x86 registers	15
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.63 cycles
front end	6.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.17	3.17	3.17	3.17	3.17	3.17	4.00	4.00	4.00	4.00	0.50	0.00	0.00	0.50	0.00	0.00
cycles	3.17	3.17	3.17	3.17	3.17	3.17	4.00	4.00	4.00	4.00	0.50	0.00	0.00	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	6.63
Dispatch	4.00
DIV/SQRT	7.00-12.00
Overall L1	7.00-12.00

Vectorization ratios

INT

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	4%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 527740

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 4110b0 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 4111f0 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x40(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSXD %R12D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 527d80 <hypre_ParCSRRelaxThreads._omp_fn.1+0x640>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
ADD %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 527d68 <hypre_ParCSRRelaxThreads._omp_fn.1+0x628>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ 0x50(%RBX),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x48(%RBX),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x58(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RBX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
KXNORB %K1,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VMOVSD 0x68(%RBX),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ (%RBX),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%RBX),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 5277ec <hypre_ParCSRRelaxThreads._omp_fn.1+0xac>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 527779 <hypre_ParCSRRelaxThreads._omp_fn.1+0x39>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	48.36	25.16
▼Loop 2134 - ams.c:3662-3682 - exec–	47.94	22.87
○Loop 2136 - ams.c:3672-3675 - exec	0.42	0.20
○Loop 2135 - ams.c:3677-3680 - exec	0.01	0.01

Report Configuration

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code