OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.9	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.43% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1584:            tmp_marker = NULL;

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

1600:            {  thread_stop = pass_pointer[1] + pass_length; }

1601:            else

1602:            {  thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); }

1603:

1604:            /* determine P for points of pass 1, i.e. neighbors of coarse points */

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x4752d0 PUSH	%RBP

0x4752d1 MOV	%RSP,%RBP

0x4752d4 PUSH	%R15

0x4752d6 PUSH	%R14

0x4752d8 PUSH	%R13

0x4752da PUSH	%R12

0x4752dc PUSH	%RBX

0x4752dd AND	$-0x20,%RSP

0x4752e1 SUB	$0x100,%RSP

0x4752e8 MOV	0xf8(%RDI),%RAX

0x4752ef MOV	0xf0(%RDI),%RDX

0x4752f6 MOV	0xe0(%RDI),%RCX

0x4752fd MOV	0xd8(%RDI),%RSI

0x475304 MOV	0xd0(%RDI),%R8

0x47530b MOV	0xc8(%RDI),%R9

0x475312 MOV	0xc0(%RDI),%R10

0x475319 MOV	0xb8(%RDI),%R11

0x475320 MOV	0xe8(%RDI),%RBX

0x475327 MOV	%RAX,0xe0(%RSP)

0x47532f MOV	%RDX,0xb8(%RSP)

0x475337 MOV	%RCX,0x28(%RSP)

0x47533c MOV	%RSI,0xb0(%RSP)

0x475344 MOV	%R8,0x50(%RSP)

0x475349 MOV	%R9,0x48(%RSP)

0x47534e MOV	%R10,0x88(%RSP)

0x475356 MOV	%R11,0x80(%RSP)

0x47535e MOV	0xb0(%RDI),%R12

0x475365 MOV	0x88(%RDI),%RAX

0x47536c MOV	0x80(%RDI),%RDX

0x475373 MOV	0x78(%RDI),%RCX

0x475377 MOV	0xa8(%RDI),%R13

0x47537e MOV	0x90(%RDI),%R15

0x475385 MOV	0x68(%RDI),%R8

0x475389 MOV	0x60(%RDI),%R9

0x47538d MOV	0x58(%RDI),%R10

0x475391 MOV	0x70(%RDI),%RSI

0x475395 MOV	0x98(%RDI),%R14

0x47539c MOV	0x50(%RDI),%R11

0x4753a0 MOV	%R12,0x98(%RSP)

0x4753a8 MOV	%RAX,0x40(%RSP)

0x4753ad MOV	0x40(%RDI),%R12

0x4753b1 MOV	0x38(%RDI),%RAX

0x4753b5 MOV	%RDX,0xa8(%RSP)

0x4753bd MOV	%RCX,0x78(%RSP)

0x4753c2 MOV	0x30(%RDI),%RDX

0x4753c6 MOV	0x28(%RDI),%RCX

0x4753ca MOV	%R13,0x18(%RSP)

0x4753cf MOV	%R15,0xc0(%RSP)

0x4753d7 MOV	0xa0(%RDI),%R13

0x4753de MOV	0x48(%RDI),%R15

0x4753e2 MOV	%R8,0xa0(%RSP)

0x4753ea MOV	%R9,0x70(%RSP)

0x4753ef MOV	%R10,0xc8(%RSP)

0x4753f7 MOV	%RSI,0xd0(%RSP)

0x4753ff MOV	%R12,0x68(%RSP)

0x475404 MOV	%RAX,0xf0(%RSP)

0x47540c MOV	%RDX,0x38(%RSP)

0x475411 MOV	%RCX,0x60(%RSP)

0x475416 MOV	0x20(%RDI),%RSI

0x47541a MOV	0x18(%RDI),%R8

0x47541e MOV	0x10(%RDI),%R9

0x475422 MOV	0x8(%RDI),%R10

0x475426 MOV	(%RDI),%RDI

0x475429 MOV	%RSI,0xe8(%RSP)

0x475431 MOV	%R8,0x30(%RSP)

0x475436 MOV	%R9,0xd8(%RSP)

0x47543e MOV	%R10,0xf8(%RSP)

0x475446 TEST	%RBX,%RBX

0x475449 JNE	4760e2

0x47544f TEST	%R11,%R11

0x475452 JNE	475a13

0x475458 XOR	%EBX,%EBX

0x47545a XOR	%R12D,%R12D

0x47545d VMOVSD	%XMM1,0x58(%RSP)

0x475463 MOV	%RDI,0x20(%RSP)

0x475468 CALL	5a9ce0 <hypre_GetThreadNum>

0x47546d MOV	%RAX,0x90(%RSP)

0x475475 CALL	5a9cd0 <hypre_NumActiveThreads>

0x47547a MOV	0x98(%RSP),%RDX

0x475482 MOV	0x90(%RSP),%R8

0x47548a MOV	%RAX,%RSI

0x47548d MOV	0xe0(%RSP),%RAX

0x475495 MOV	0xe0(%RSP),%R11

0x47549d VMOVSD	0x58(%RSP),%XMM1

0x4754a3 MOV	0x8(%RDX),%RCX

0x4754a7 MOV	%R8,%R10

0x4754aa CQTO

0x4754ac IDIV	%RSI

0x4754af DEC	%RSI

0x4754b2 ADD	%RCX,%R11

0x4754b5 IMUL	%RAX,%R10

0x4754b9 LEA	(%RCX,%R10,1),%R9

0x4754bd ADD	%RAX,%R10

0x4754c0 ADD	%RCX,%R10

0x4754c3 CMP	%RSI,%R8

0x4754c6 MOV	0x20(%RSP),%RCX

0x4754cb CMOVNE	%R10,%R11

0x4754cf CMP	%R9,%R11

0x4754d2 JLE	475e59

0x4754d8 MOV	0x18(%RSP),%RDI

0x4754dd MOV	%R14,%R10

0x4754e0 VXORPD	%XMM6,%XMM6,%XMM6

0x4754e4 VMOVQ	0x13a7d4(%RIP),%XMM7

0x4754ec LEA	(%RDI,%R9,8),%RSI

0x4754f0 LEA	(%RDI,%R11,8),%RAX

0x4754f4 MOV	%RCX,%R9

0x4754f7 MOV	%R15,%RDI

0x4754fa MOV	%RSI,0xe0(%RSP)

0x475502 MOV	%RAX,0x58(%RSP)

0x475507 NOPW	(%RAX,%RAX,1)

(655) 0x475510 MOV	0xe0(%RSP),%R14

(655) 0x475518 MOV	0x70(%RSP),%RCX

(655) 0x47551d MOV	0x80(%RSP),%R15

(655) 0x475525 MOV	(%R14),%R8

(655) 0x475528 LEA	(,%R8,8),%R14

(655) 0x475530 LEA	(%RCX,%R14,1),%RSI

(655) 0x475534 MOV	(%R15,%R14,1),%R11

(655) 0x475538 MOV	0x8(%RCX,%R14,1),%RAX

(655) 0x47553d LEA	0x8(%R14),%RDX

(655) 0x475541 VMOVQ	%RSI,%XMM11

(655) 0x475546 MOV	(%RSI),%RSI

(655) 0x475549 ADD	%R11,%RAX

(655) 0x47554c SUB	%RSI,%RAX

(655) 0x47554f CMP	%RAX,%R11

(655) 0x475552 JGE	475685

(655) 0x475558 MOV	0x48(%RSP),%R15

(655) 0x47555d MOV	0x8(%R15),%RSI

(655) 0x475561 LEA	(%RSI,%RAX,8),%RCX

(655) 0x475565 LEA	(%RSI,%R11,8),%R11

(655) 0x475569 MOV	%RCX,%RAX

(655) 0x47556c SUB	%R11,%RAX

(655) 0x47556f SUB	$0x8,%RAX

(655) 0x475573 SHR	$0x3,%RAX

(655) 0x475577 INC	%RAX

(655) 0x47557a AND	$0x7,%EAX

(655) 0x47557d JE	475615

(655) 0x475583 CMP	$0x1,%RAX

(655) 0x475587 JE	475601

(655) 0x475589 CMP	$0x2,%RAX

(655) 0x47558d JE	4755f2

(655) 0x47558f CMP	$0x3,%RAX

(655) 0x475593 JE	4755e3

(655) 0x475595 CMP	$0x4,%RAX

(655) 0x475599 JE	4755d4

(655) 0x47559b CMP	$0x5,%RAX

(655) 0x47559f JE	4755c5

(655) 0x4755a1 CMP	$0x6,%RAX

(655) 0x4755a5 JE	4755b6

(655) 0x4755a7 MOV	(%R11),%R15

(655) 0x4755aa ADD	$0x8,%R11

(655) 0x4755ae MOV	(%R10,%R15,8),%RSI

(655) 0x4755b2 MOV	%R8,(%R12,%RSI,8)

(655) 0x4755b6 MOV	(%R11),%RAX

(655) 0x4755b9 ADD	$0x8,%R11

(655) 0x4755bd MOV	(%R10,%RAX,8),%R15

(655) 0x4755c1 MOV	%R8,(%R12,%R15,8)

(655) 0x4755c5 MOV	(%R11),%RSI

(655) 0x4755c8 ADD	$0x8,%R11

(655) 0x4755cc MOV	(%R10,%RSI,8),%RAX

(655) 0x4755d0 MOV	%R8,(%R12,%RAX,8)

(655) 0x4755d4 MOV	(%R11),%R15

(655) 0x4755d7 ADD	$0x8,%R11

(655) 0x4755db MOV	(%R10,%R15,8),%RSI

(655) 0x4755df MOV	%R8,(%R12,%RSI,8)

(655) 0x4755e3 MOV	(%R11),%RAX

(655) 0x4755e6 ADD	$0x8,%R11

(655) 0x4755ea MOV	(%R10,%RAX,8),%R15

(655) 0x4755ee MOV	%R8,(%R12,%R15,8)

(655) 0x4755f2 MOV	(%R11),%RSI

(655) 0x4755f5 ADD	$0x8,%R11

(655) 0x4755f9 MOV	(%R10,%RSI,8),%RAX

(655) 0x4755fd MOV	%R8,(%R12,%RAX,8)

(655) 0x475601 MOV	(%R11),%R15

(655) 0x475604 ADD	$0x8,%R11

(655) 0x475608 MOV	(%R10,%R15,8),%RSI

(655) 0x47560c MOV	%R8,(%R12,%RSI,8)

(655) 0x475610 CMP	%RCX,%R11

(655) 0x475613 JE	47567d

  (664) 0x475615 MOV	(%R11),%RAX

  (664) 0x475618 ADD	$0x40,%R11

  (664) 0x47561c MOV	(%R10,%RAX,8),%R15

  (664) 0x475620 MOV	%R8,(%R12,%R15,8)

  (664) 0x475624 MOV	-0x38(%R11),%RSI

  (664) 0x475628 MOV	(%R10,%RSI,8),%RAX

  (664) 0x47562c MOV	%R8,(%R12,%RAX,8)

  (664) 0x475630 MOV	-0x30(%R11),%R15

  (664) 0x475634 MOV	(%R10,%R15,8),%RSI

  (664) 0x475638 MOV	%R8,(%R12,%RSI,8)

  (664) 0x47563c MOV	-0x28(%R11),%RAX

  (664) 0x475640 MOV	(%R10,%RAX,8),%R15

  (664) 0x475644 MOV	%R8,(%R12,%R15,8)

  (664) 0x475648 MOV	-0x20(%R11),%RSI

  (664) 0x47564c MOV	(%R10,%RSI,8),%RAX

  (664) 0x475650 MOV	%R8,(%R12,%RAX,8)

  (664) 0x475654 MOV	-0x18(%R11),%R15

  (664) 0x475658 MOV	(%R10,%R15,8),%RSI

  (664) 0x47565c MOV	%R8,(%R12,%RSI,8)

  (664) 0x475660 MOV	-0x10(%R11),%RAX

  (664) 0x475664 MOV	(%R10,%RAX,8),%R15

  (664) 0x475668 MOV	%R8,(%R12,%R15,8)

  (664) 0x47566c MOV	-0x8(%R11),%RSI

  (664) 0x475670 MOV	(%R10,%RSI,8),%RAX

  (664) 0x475674 MOV	%R8,(%R12,%RAX,8)

  (664) 0x475678 CMP	%RCX,%R11

  (664) 0x47567b JNE	475615

(655) 0x47567d VMOVQ	%XMM11,%R11

(655) 0x475682 MOV	(%R11),%RSI

(655) 0x475685 MOV	0x60(%RSP),%RCX

(655) 0x47568a VXORPD	%XMM0,%XMM0,%XMM0

(655) 0x47568e VMOVAPD	%XMM0,%XMM2

(655) 0x475692 LEA	(%RCX,%R14,1),%R15

(655) 0x475696 MOV	(%R15),%RAX

(655) 0x475699 VMOVQ	%R15,%XMM12

(655) 0x47569e LEA	(%RCX,%RDX,1),%R15

(655) 0x4756a2 INC	%RAX

(655) 0x4756a5 CMP	(%R15),%RAX

(655) 0x4756a8 JGE	475787

(655) 0x4756ae CMPQ	$0x1,0xf8(%RSP)

(655) 0x4756b7 MOV	%RBX,0x98(%RSP)

(655) 0x4756bf JE	475e80

(655) 0x4756c5 MOV	%RSI,%RBX

(655) 0x4756c8 MOV	%RDX,0x90(%RSP)

(655) 0x4756d0 MOV	0xd8(%RSP),%RSI

(655) 0x4756d8 MOV	0x38(%RSP),%RDX

(655) 0x4756dd VMOVQ	%RDI,%XMM8

(655) 0x4756e2 NOPW	%CS:(%RAX,%RAX,1)

(655) 0x4756ed NOPL	(%RAX)

  (663) 0x4756f0 MOV	(%RDX,%RAX,8),%RCX

  (663) 0x4756f4 CMPQ	$-0x3,(%R9,%RCX,8)

  (663) 0x4756f9 LEA	(,%RCX,8),%R11

  (663) 0x475701 JE	47571a

  (663) 0x475703 MOV	(%RSI,%R11,1),%RDI

  (663) 0x475707 CMP	%RDI,(%RSI,%R14,1)

  (663) 0x47570b JNE	47571a

  (663) 0x47570d MOV	0xe8(%RSP),%RDI

  (663) 0x475715 VADDSD	(%RDI,%RAX,8),%XMM0,%XMM0

  (663) 0x47571a CMP	$-0x1,%RCX

  (663) 0x47571e JE	475767

  (663) 0x475720 CMP	(%R12,%R11,1),%R8

  (663) 0x475724 JNE	475767

  (663) 0x475726 MOV	0xe8(%RSP),%RDI

  (663) 0x47572e LEA	(,%RBX,8),%RCX

  (663) 0x475736 INC	%RBX

  (663) 0x475739 VMOVSD	(%RDI,%RAX,8),%XMM3

  (663) 0x47573e MOV	0xc8(%RSP),%RDI

  (663) 0x475746 VADDSD	%XMM3,%XMM2,%XMM2

  (663) 0x47574a VMOVSD	%XMM3,(%RDI,%RCX,1)

  (663) 0x47574f MOV	0xb8(%RSP),%RDI

  (663) 0x475757 MOV	(%RDI,%R11,1),%R11

  (663) 0x47575b MOV	0xa0(%RSP),%RDI

  (663) 0x475763 MOV	%R11,(%RDI,%RCX,1)

  (663) 0x475767 INC	%RAX

  (663) 0x47576a CMP	(%R15),%RAX

  (663) 0x47576d JL	4756f0

(655) 0x47576f MOV	%RBX,%RSI

(655) 0x475772 MOV	0x90(%RSP),%RDX

(655) 0x47577a MOV	0x98(%RSP),%RBX

(655) 0x475782 VMOVQ	%XMM8,%RDI

(655) 0x475787 MOV	0x88(%RSP),%RAX

(655) 0x47578f MOV	0x78(%RSP),%R15

(655) 0x475794 MOV	(%RAX,%R14,1),%R11

(655) 0x475798 LEA	(%R15,%R14,1),%RCX

(655) 0x47579c MOV	(%R15,%RDX,1),%RAX

(655) 0x4757a0 VMOVQ	%RCX,%XMM13

(655) 0x4757a5 MOV	(%RCX),%RCX

(655) 0x4757a8 ADD	%R11,%RAX

(655) 0x4757ab SUB	%RCX,%RAX

(655) 0x4757ae CMP	%RAX,%R11

(655) 0x4757b1 JGE	4758fd

(655) 0x4757b7 MOV	0x50(%RSP),%R15

(655) 0x4757bc MOV	0x8(%R15),%RCX

(655) 0x4757c0 LEA	(%RCX,%R11,8),%R11

(655) 0x4757c4 LEA	(%RCX,%RAX,8),%RCX

(655) 0x4757c8 MOV	%RCX,%RAX

(655) 0x4757cb SUB	%R11,%RAX

(655) 0x4757ce SUB	$0x8,%RAX

(655) 0x4757d2 SHR	$0x3,%RAX

(655) 0x4757d6 INC	%RAX

(655) 0x4757d9 AND	$0x7,%EAX

(655) 0x4757dc JE	47587b

(655) 0x4757e2 CMP	$0x1,%RAX

(655) 0x4757e6 JE	475866

(655) 0x4757e8 CMP	$0x2,%RAX

(655) 0x4757ec JE	475856

(655) 0x4757ee CMP	$0x3,%RAX

(655) 0x4757f2 JE	475846

(655) 0x4757f4 CMP	$0x4,%RAX

(655) 0x4757f8 JE	475836

(655) 0x4757fa CMP	$0x5,%RAX

(655) 0x4757fe JE	475826

(655) 0x475800 CMP	$0x6,%RAX

(655) 0x475804 JE	475816

(655) 0x475806 MOV	(%R11),%R15

(655) 0x475809 ADD	$0x8,%R11

(655) 0x47580d MOV	(%R13,%R15,8),%RAX

(655) 0x475812 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475816 MOV	(%R11),%R15

(655) 0x475819 ADD	$0x8,%R11

(655) 0x47581d MOV	(%R13,%R15,8),%RAX

(655) 0x475822 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475826 MOV	(%R11),%R15

(655) 0x475829 ADD	$0x8,%R11

(655) 0x47582d MOV	(%R13,%R15,8),%RAX

(655) 0x475832 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475836 MOV	(%R11),%R15

(655) 0x475839 ADD	$0x8,%R11

(655) 0x47583d MOV	(%R13,%R15,8),%RAX

(655) 0x475842 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475846 MOV	(%R11),%R15

(655) 0x475849 ADD	$0x8,%R11

(655) 0x47584d MOV	(%R13,%R15,8),%RAX

(655) 0x475852 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475856 MOV	(%R11),%R15

(655) 0x475859 ADD	$0x8,%R11

(655) 0x47585d MOV	(%R13,%R15,8),%RAX

(655) 0x475862 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475866 MOV	(%R11),%R15

(655) 0x475869 ADD	$0x8,%R11

(655) 0x47586d MOV	(%R13,%R15,8),%RAX

(655) 0x475872 MOV	%R8,(%RBX,%RAX,8)

(655) 0x475876 CMP	%R11,%RCX

(655) 0x475879 JE	4758f5

(655) 0x47587b VMOVQ	%XMM13,%R15

  (661) 0x475880 MOV	(%R11),%RAX

  (661) 0x475883 ADD	$0x40,%R11

  (661) 0x475887 MOV	(%R13,%RAX,8),%RAX

  (661) 0x47588c MOV	%R8,(%RBX,%RAX,8)

  (661) 0x475890 MOV	-0x38(%R11),%RAX

  (661) 0x475894 MOV	(%R13,%RAX,8),%RAX

  (661) 0x475899 MOV	%R8,(%RBX,%RAX,8)

  (661) 0x47589d MOV	-0x30(%R11),%RAX

  (661) 0x4758a1 MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758a6 MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758aa MOV	-0x28(%R11),%RAX

  (661) 0x4758ae MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758b3 MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758b7 MOV	-0x20(%R11),%RAX

  (661) 0x4758bb MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758c0 MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758c4 MOV	-0x18(%R11),%RAX

  (661) 0x4758c8 MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758cd MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758d1 MOV	-0x10(%R11),%RAX

  (661) 0x4758d5 MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758da MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758de MOV	-0x8(%R11),%RAX

  (661) 0x4758e2 MOV	(%R13,%RAX,8),%RAX

  (661) 0x4758e7 MOV	%R8,(%RBX,%RAX,8)

  (661) 0x4758eb CMP	%R11,%RCX

  (661) 0x4758ee JNE	475880

(655) 0x4758f0 VMOVQ	%R15,%XMM13

(655) 0x4758f5 VMOVQ	%XMM13,%R11

(655) 0x4758fa MOV	(%R11),%RCX

(655) 0x4758fd MOV	0x68(%RSP),%R15

(655) 0x475902 MOV	(%R15,%R14,1),%RAX

(655) 0x475906 LEA	(%R15,%RDX,1),%RDX

(655) 0x47590a CMP	(%RDX),%RAX

(655) 0x47590d JGE	476020

(655) 0x475913 CMPQ	$0,0x30(%RSP)

(655) 0x475919 JE	475f20

(655) 0x47591f VMOVQ	%R10,%XMM14

(655) 0x475924 MOV	%R12,0x98(%RSP)

(655) 0x47592c MOV	%R8,%R10

(655) 0x47592f MOV	%RBX,%R12

(655) 0x475932 MOV	%RSI,0x90(%RSP)

(655) 0x47593a MOV	%RCX,%RBX

(655) 0x47593d MOV	0x28(%RSP),%R11

(655) 0x475942 MOV	0x40(%RSP),%RCX

(655) 0x475947 VMOVQ	%R13,%XMM10

(655) 0x47594c VMOVQ	%R9,%XMM9

(655) 0x475951 MOV	%R14,%R8

(655) 0x475954 MOV	%RDX,%RSI

(655) 0x475957 VMOVQ	%XMM13,%R15

(655) 0x47595c JMP	4759da

0x47595e XCHG	%AX,%AX

  (660) 0x475960 MOV	0xc0(%RSP),%R13

  (660) 0x475968 MOV	0xd8(%RSP),%R9

  (660) 0x475970 MOV	(%R13,%R14,1),%R13

  (660) 0x475975 CMP	%R13,(%R9,%R8,1)

  (660) 0x475979 JE	475a00

  (660) 0x47597f CMP	$-0x1,%RDX

  (660) 0x475983 JE	4759ce

  (660) 0x475985 CMP	(%R12,%R14,1),%R10

  (660) 0x475989 JNE	4759ce

  (660) 0x47598b MOV	0xf0(%RSP),%RDX

  (660) 0x475993 MOV	0xd0(%RSP),%R9

  (660) 0x47599b LEA	(,%RBX,8),%R13

  (660) 0x4759a3 INC	%RBX

  (660) 0x4759a6 VMOVSD	(%RDX,%RAX,8),%XMM15

  (660) 0x4759ab MOV	0xb0(%RSP),%RDX

  (660) 0x4759b3 VMOVSD	%XMM15,(%R9,%R13,1)

  (660) 0x4759b9 VADDSD	%XMM15,%XMM2,%XMM2

  (660) 0x4759be MOV	(%RDX,%R14,1),%R9

  (660) 0x4759c2 MOV	0xa8(%RSP),%R14

  (660) 0x4759ca MOV	%R9,(%R14,%R13,1)

  (660) 0x4759ce INC	%RAX

  (660) 0x4759d1 CMP	(%RSI),%RAX

  (660) 0x4759d4 JGE	475a90

  (660) 0x4759da MOV	(%RDI,%RAX,8),%R13

  (660) 0x4759de MOV	(%R11,%R13,8),%RDX

  (660) 0x4759e2 CMPQ	$-0x3,(%RCX,%RDX,8)

  (660) 0x4759e7 LEA	(,%RDX,8),%R14

  (660) 0x4759ef JE	47597f

  (660) 0x4759f1 CMPQ	$0x1,0xf8(%RSP)

  (660) 0x4759fa JNE	475960

  (660) 0x475a00 MOV	0xf0(%RSP),%R9

  (660) 0x475a08 VADDSD	(%R9,%RAX,8),%XMM0,%XMM0

  (660) 0x475a0e JMP	47597f

0x475a13 MOV	%RDI,0x20(%RSP)

0x475a18 MOV	$0x8,%ESI

0x475a1d MOV	%R11,%RDI

0x475a20 VMOVSD	%XMM1,0x58(%RSP)

0x475a26 MOV	%R11,0x90(%RSP)

0x475a2e CALL	5a6c20 <hypre_CAlloc>

0x475a33 MOV	0x90(%RSP),%R11

0x475a3b MOV	0x20(%RSP),%RDI

0x475a40 MOV	%RAX,%RBX

0x475a43 XOR	%R12D,%R12D

0x475a46 VMOVSD	0x58(%RSP),%XMM1

0x475a4c TEST	%R11,%R11

0x475a4f JLE	47545d

0x475a55 MOV	%RDI,0x58(%RSP)

0x475a5a LEA	(,%R11,8),%RDX

0x475a62 MOV	%RBX,%RDI

0x475a65 MOV	$0xff,%ESI

0x475a6a VMOVSD	%XMM1,0x90(%RSP)

0x475a73 CALL	4110a0 <memset@plt>

0x475a78 MOV	0x58(%RSP),%RDI

0x475a7d VMOVSD	0x90(%RSP),%XMM1

0x475a86 JMP	47545d

0x475a8b NOPL	(%RAX,%RAX,1)

(655) 0x475a90 VMOVQ	%XMM10,%R13

(655) 0x475a95 VMOVQ	%XMM14,%R10

(655) 0x475a9a VMOVQ	%XMM9,%R9

(655) 0x475a9f MOV	%RBX,%RCX

(655) 0x475aa2 MOV	0x90(%RSP),%RSI

(655) 0x475aaa MOV	%R12,%RBX

(655) 0x475aad MOV	0x98(%RSP),%R12

(655) 0x475ab5 VMOVQ	%R15,%XMM10

(655) 0x475aba VMOVQ	%XMM10,%RAX

(655) 0x475abf MOV	(%RAX),%R8

(655) 0x475ac2 VMOVQ	%XMM12,%R15

(655) 0x475ac7 MOV	0xe8(%RSP),%RDX

(655) 0x475acf MOV	(%R15),%R14

(655) 0x475ad2 VMULSD	(%RDX,%R14,8),%XMM2,%XMM12

(655) 0x475ad8 VCOMISD	%XMM6,%XMM12

(655) 0x475adc JE	475ae7

(655) 0x475ade VXORPD	%XMM7,%XMM0,%XMM1

(655) 0x475ae2 VDIVSD	%XMM12,%XMM1,%XMM1

(655) 0x475ae7 VMOVQ	%XMM11,%R11

(655) 0x475aec MOV	(%R11),%R11

(655) 0x475aef CMP	%RSI,%R11

(655) 0x475af2 JGE	475c85

(655) 0x475af8 MOV	%RSI,%R14

(655) 0x475afb SUB	%R11,%R14

(655) 0x475afe LEA	-0x1(%R14),%RAX

(655) 0x475b02 CMP	$0x2,%RAX

(655) 0x475b06 JBE	475c3d

(655) 0x475b0c MOV	0xc8(%RSP),%R15

(655) 0x475b14 MOV	%R14,%RDX

(655) 0x475b17 VBROADCASTSD	%XMM1,%YMM11

(655) 0x475b1c SHR	$0x2,%RDX

(655) 0x475b20 SAL	$0x5,%RDX

(655) 0x475b24 LEA	(%R15,%R11,8),%RAX

(655) 0x475b28 LEA	(%RDX,%RAX,1),%R15

(655) 0x475b2c SUB	$0x20,%RDX

(655) 0x475b30 SHR	$0x5,%RDX

(655) 0x475b34 INC	%RDX

(655) 0x475b37 AND	$0x7,%EDX

(655) 0x475b3a JE	475bc4

(655) 0x475b40 CMP	$0x1,%RDX

(655) 0x475b44 JE	475bb2

(655) 0x475b46 CMP	$0x2,%RDX

(655) 0x475b4a JE	475ba5

(655) 0x475b4c CMP	$0x3,%RDX

(655) 0x475b50 JE	475b98

(655) 0x475b52 CMP	$0x4,%RDX

(655) 0x475b56 JE	475b8b

(655) 0x475b58 CMP	$0x5,%RDX

(655) 0x475b5c JE	475b7e

(655) 0x475b5e CMP	$0x6,%RDX

(655) 0x475b62 JE	475b71

(655) 0x475b64 VMULPD	(%RAX),%YMM11,%YMM0

(655) 0x475b68 ADD	$0x20,%RAX

(655) 0x475b6c VMOVUPD	%YMM0,-0x20(%RAX)

(655) 0x475b71 VMULPD	(%RAX),%YMM11,%YMM2

(655) 0x475b75 ADD	$0x20,%RAX

(655) 0x475b79 VMOVUPD	%YMM2,-0x20(%RAX)

(655) 0x475b7e VMULPD	(%RAX),%YMM11,%YMM14

(655) 0x475b82 ADD	$0x20,%RAX

(655) 0x475b86 VMOVUPD	%YMM14,-0x20(%RAX)

(655) 0x475b8b VMULPD	(%RAX),%YMM11,%YMM9

(655) 0x475b8f ADD	$0x20,%RAX

(655) 0x475b93 VMOVUPD	%YMM9,-0x20(%RAX)

(655) 0x475b98 VMULPD	(%RAX),%YMM11,%YMM15

(655) 0x475b9c ADD	$0x20,%RAX

(655) 0x475ba0 VMOVUPD	%YMM15,-0x20(%RAX)

(655) 0x475ba5 VMULPD	(%RAX),%YMM11,%YMM4

(655) 0x475ba9 ADD	$0x20,%RAX

(655) 0x475bad VMOVUPD	%YMM4,-0x20(%RAX)

(655) 0x475bb2 VMULPD	(%RAX),%YMM11,%YMM5

(655) 0x475bb6 ADD	$0x20,%RAX

(655) 0x475bba VMOVUPD	%YMM5,-0x20(%RAX)

(655) 0x475bbf CMP	%RAX,%R15

(655) 0x475bc2 JE	475c30

  (657) 0x475bc4 VMULPD	(%RAX),%YMM11,%YMM8

  (657) 0x475bc8 VMULPD	0x20(%RAX),%YMM11,%YMM3

  (657) 0x475bcd ADD	$0x100,%RAX

  (657) 0x475bd3 VMULPD	-0xc0(%RAX),%YMM11,%YMM13

  (657) 0x475bdb VMULPD	-0xa0(%RAX),%YMM11,%YMM10

  (657) 0x475be3 VMULPD	-0x80(%RAX),%YMM11,%YMM12

  (657) 0x475be8 VMULPD	-0x60(%RAX),%YMM11,%YMM0

  (657) 0x475bed VMULPD	-0x40(%RAX),%YMM11,%YMM2

  (657) 0x475bf2 VMULPD	-0x20(%RAX),%YMM11,%YMM14

  (657) 0x475bf7 VMOVUPD	%YMM8,-0x100(%RAX)

  (657) 0x475bff VMOVUPD	%YMM3,-0xe0(%RAX)

  (657) 0x475c07 VMOVUPD	%YMM13,-0xc0(%RAX)

  (657) 0x475c0f VMOVUPD	%YMM10,-0xa0(%RAX)

  (657) 0x475c17 VMOVUPD	%YMM12,-0x80(%RAX)

  (657) 0x475c1c VMOVUPD	%YMM0,-0x60(%RAX)

  (657) 0x475c21 VMOVUPD	%YMM2,-0x40(%RAX)

  (657) 0x475c26 VMOVUPD	%YMM14,-0x20(%RAX)

  (657) 0x475c2b CMP	%RAX,%R15

  (657) 0x475c2e JNE	475bc4

(655) 0x475c30 TEST	$0x3,%R14B

(655) 0x475c34 JE	475c85

(655) 0x475c36 AND	$-0x4,%R14

(655) 0x475c3a ADD	%R14,%R11

(655) 0x475c3d MOV	0xc8(%RSP),%R15

(655) 0x475c45 LEA	(,%R11,8),%RAX

(655) 0x475c4d LEA	0x1(%R11),%R14

(655) 0x475c51 LEA	(%R15,%RAX,1),%RDX

(655) 0x475c55 VMULSD	(%RDX),%XMM1,%XMM11

(655) 0x475c59 VMOVSD	%XMM11,(%RDX)

(655) 0x475c5d CMP	%R14,%RSI

(655) 0x475c60 JLE	475c85

(655) 0x475c62 LEA	0x8(%R15,%RAX,1),%RDX

(655) 0x475c67 ADD	$0x2,%R11

(655) 0x475c6b VMULSD	(%RDX),%XMM1,%XMM9

(655) 0x475c6f VMOVSD	%XMM9,(%RDX)

(655) 0x475c73 CMP	%R11,%RSI

(655) 0x475c76 JLE	475c85

(655) 0x475c78 LEA	0x10(%R15,%RAX,1),%RSI

(655) 0x475c7d VMULSD	(%RSI),%XMM1,%XMM15

(655) 0x475c81 VMOVSD	%XMM15,(%RSI)

(655) 0x475c85 CMP	%R8,%RCX

(655) 0x475c88 JLE	475e3a

(655) 0x475c8e MOV	%RCX,%R15

(655) 0x475c91 SUB	%R8,%R15

(655) 0x475c94 LEA	-0x1(%R15),%R11

(655) 0x475c98 CMP	$0x2,%R11

(655) 0x475c9c JBE	475df2

(655) 0x475ca2 MOV	0xd0(%RSP),%RAX

(655) 0x475caa MOV	%R15,%RDX

(655) 0x475cad VBROADCASTSD	%XMM1,%YMM4

(655) 0x475cb2 SHR	$0x2,%RDX

(655) 0x475cb6 SAL	$0x5,%RDX

(655) 0x475cba LEA	(%RAX,%R8,8),%R14

(655) 0x475cbe LEA	(%RDX,%R14,1),%RSI

(655) 0x475cc2 SUB	$0x20,%RDX

(655) 0x475cc6 SHR	$0x5,%RDX

(655) 0x475cca INC	%RDX

(655) 0x475ccd AND	$0x7,%EDX

(655) 0x475cd0 JE	475d68

(655) 0x475cd6 CMP	$0x1,%RDX

(655) 0x475cda JE	475d54

(655) 0x475cdc CMP	$0x2,%RDX

(655) 0x475ce0 JE	475d45

(655) 0x475ce2 CMP	$0x3,%RDX

(655) 0x475ce6 JE	475d36

(655) 0x475ce8 CMP	$0x4,%RDX

(655) 0x475cec JE	475d27

(655) 0x475cee CMP	$0x5,%RDX

(655) 0x475cf2 JE	475d18

(655) 0x475cf4 CMP	$0x6,%RDX

(655) 0x475cf8 JE	475d09

(655) 0x475cfa VMULPD	(%R14),%YMM4,%YMM5

(655) 0x475cff ADD	$0x20,%R14

(655) 0x475d03 VMOVUPD	%YMM5,-0x20(%R14)

(655) 0x475d09 VMULPD	(%R14),%YMM4,%YMM8

(655) 0x475d0e ADD	$0x20,%R14

(655) 0x475d12 VMOVUPD	%YMM8,-0x20(%R14)

(655) 0x475d18 VMULPD	(%R14),%YMM4,%YMM3

(655) 0x475d1d ADD	$0x20,%R14

(655) 0x475d21 VMOVUPD	%YMM3,-0x20(%R14)

(655) 0x475d27 VMULPD	(%R14),%YMM4,%YMM13

(655) 0x475d2c ADD	$0x20,%R14

(655) 0x475d30 VMOVUPD	%YMM13,-0x20(%R14)

(655) 0x475d36 VMULPD	(%R14),%YMM4,%YMM10

(655) 0x475d3b ADD	$0x20,%R14

(655) 0x475d3f VMOVUPD	%YMM10,-0x20(%R14)

(655) 0x475d45 VMULPD	(%R14),%YMM4,%YMM12

(655) 0x475d4a ADD	$0x20,%R14

(655) 0x475d4e VMOVUPD	%YMM12,-0x20(%R14)

(655) 0x475d54 VMULPD	(%R14),%YMM4,%YMM0

(655) 0x475d59 ADD	$0x20,%R14

(655) 0x475d5d VMOVUPD	%YMM0,-0x20(%R14)

(655) 0x475d63 CMP	%RSI,%R14

(655) 0x475d66 JE	475de5

  (656) 0x475d68 VMULPD	(%R14),%YMM4,%YMM2

  (656) 0x475d6d VMULPD	0x20(%R14),%YMM4,%YMM14

  (656) 0x475d73 ADD	$0x100,%R14

  (656) 0x475d7a VMULPD	-0xc0(%R14),%YMM4,%YMM11

  (656) 0x475d83 VMULPD	-0xa0(%R14),%YMM4,%YMM9

  (656) 0x475d8c VMULPD	-0x80(%R14),%YMM4,%YMM15

  (656) 0x475d92 VMULPD	-0x60(%R14),%YMM4,%YMM5

  (656) 0x475d98 VMULPD	-0x40(%R14),%YMM4,%YMM8

  (656) 0x475d9e VMULPD	-0x20(%R14),%YMM4,%YMM3

  (656) 0x475da4 VMOVUPD	%YMM2,-0x100(%R14)

  (656) 0x475dad VMOVUPD	%YMM14,-0xe0(%R14)

  (656) 0x475db6 VMOVUPD	%YMM11,-0xc0(%R14)

  (656) 0x475dbf VMOVUPD	%YMM9,-0xa0(%R14)

  (656) 0x475dc8 VMOVUPD	%YMM15,-0x80(%R14)

  (656) 0x475dce VMOVUPD	%YMM5,-0x60(%R14)

  (656) 0x475dd4 VMOVUPD	%YMM8,-0x40(%R14)

  (656) 0x475dda VMOVUPD	%YMM3,-0x20(%R14)

  (656) 0x475de0 CMP	%RSI,%R14

  (656) 0x475de3 JNE	475d68

(655) 0x475de5 TEST	$0x3,%R15B

(655) 0x475de9 JE	475e3a

(655) 0x475deb AND	$-0x4,%R15

(655) 0x475def ADD	%R15,%R8

(655) 0x475df2 MOV	0xd0(%RSP),%R11

(655) 0x475dfa LEA	(,%R8,8),%R15

(655) 0x475e02 LEA	0x1(%R8),%R14

(655) 0x475e06 LEA	(%R11,%R15,1),%RAX

(655) 0x475e0a VMULSD	(%RAX),%XMM1,%XMM4

(655) 0x475e0e VMOVSD	%XMM4,(%RAX)

(655) 0x475e12 CMP	%R14,%RCX

(655) 0x475e15 JLE	475e3a

(655) 0x475e17 LEA	0x8(%R11,%R15,1),%RDX

(655) 0x475e1c LEA	0x2(%R8),%R8

(655) 0x475e20 VMULSD	(%RDX),%XMM1,%XMM13

(655) 0x475e24 VMOVSD	%XMM13,(%RDX)

(655) 0x475e28 CMP	%R8,%RCX

(655) 0x475e2b JLE	475e3a

(655) 0x475e2d LEA	0x10(%R11,%R15,1),%RCX

(655) 0x475e32 VMULSD	(%RCX),%XMM1,%XMM10

(655) 0x475e36 VMOVSD	%XMM10,(%RCX)

(655) 0x475e3a ADDQ	$0x8,0xe0(%RSP)

(655) 0x475e43 MOV	0xe0(%RSP),%RSI

(655) 0x475e4b CMP	%RSI,0x58(%RSP)

(655) 0x475e50 JNE	475510

0x475e56 VZEROUPPER

0x475e59 MOV	%R12,%RDI

0x475e5c CALL	5a6cb0 <hypre_Free>

0x475e61 LEA	-0x28(%RBP),%RSP

0x475e65 MOV	%RBX,%RDI

0x475e68 POP	%RBX

0x475e69 POP	%R12

0x475e6b POP	%R13

0x475e6d POP	%R14

0x475e6f POP	%R15

0x475e71 POP	%RBP

0x475e72 JMP	5a6cb0

0x475e77 NOPW	(%RAX,%RAX,1)

(655) 0x475e80 MOV	%RDX,0x90(%RSP)

(655) 0x475e88 MOV	0xe8(%RSP),%RBX

(655) 0x475e90 MOV	0x38(%RSP),%RDX

(655) 0x475e95 VMOVQ	%RDI,%XMM4

(655) 0x475e9a NOPW	(%RAX,%RAX,1)

  (662) 0x475ea0 MOV	(%RDX,%RAX,8),%RDI

  (662) 0x475ea4 CMPQ	$-0x3,(%R9,%RDI,8)

  (662) 0x475ea9 LEA	(,%RDI,8),%R11

  (662) 0x475eb1 JE	475eb8

  (662) 0x475eb3 VADDSD	(%RBX,%RAX,8),%XMM0,%XMM0

  (662) 0x475eb8 CMP	$-0x1,%RDI

  (662) 0x475ebc JE	475efd

  (662) 0x475ebe CMP	(%R12,%R11,1),%R8

  (662) 0x475ec2 JNE	475efd

  (662) 0x475ec4 MOV	0xc8(%RSP),%RDI

  (662) 0x475ecc LEA	(,%RSI,8),%RCX

  (662) 0x475ed4 VMOVSD	(%RBX,%RAX,8),%XMM5

  (662) 0x475ed9 INC	%RSI

  (662) 0x475edc VADDSD	%XMM5,%XMM2,%XMM2

  (662) 0x475ee0 VMOVSD	%XMM5,(%RDI,%RCX,1)

  (662) 0x475ee5 MOV	0xb8(%RSP),%RDI

  (662) 0x475eed MOV	(%RDI,%R11,1),%R11

  (662) 0x475ef1 MOV	0xa0(%RSP),%RDI

  (662) 0x475ef9 MOV	%R11,(%RDI,%RCX,1)

  (662) 0x475efd INC	%RAX

  (662) 0x475f00 CMP	(%R15),%RAX

  (662) 0x475f03 JL	475ea0

(655) 0x475f05 MOV	0x98(%RSP),%RBX

(655) 0x475f0d MOV	0x90(%RSP),%RDX

(655) 0x475f15 VMOVQ	%XMM4,%RDI

(655) 0x475f1a JMP	475787

0x475f1f NOP

(655) 0x475f20 CMPQ	$0x1,0xf8(%RSP)

(655) 0x475f29 JE	476028

(655) 0x475f2f MOV	%R12,0x98(%RSP)

(655) 0x475f37 MOV	%RBX,%R12

(655) 0x475f3a MOV	%RCX,%RBX

(655) 0x475f3d MOV	0x40(%RSP),%RCX

(655) 0x475f42 VMOVQ	%R9,%XMM3

(655) 0x475f47 MOV	%RSI,0x90(%RSP)

(655) 0x475f4f MOV	%R8,%R9

(655) 0x475f52 VMOVQ	%R10,%XMM8

(655) 0x475f57 MOV	%R14,%R8

(655) 0x475f5a VMOVQ	%XMM13,%R15

(655) 0x475f5f MOV	%RDX,%RSI

(655) 0x475f62 NOPW	%CS:(%RAX,%RAX,1)

(655) 0x475f6d NOPL	(%RAX)

  (659) 0x475f70 MOV	(%RDI,%RAX,8),%RDX

  (659) 0x475f74 CMPQ	$-0x3,(%RCX,%RDX,8)

  (659) 0x475f79 LEA	(,%RDX,8),%R11

  (659) 0x475f81 JE	475fab

  (659) 0x475f83 MOV	0xd8(%RSP),%R10

  (659) 0x475f8b MOV	0xc0(%RSP),%R14

  (659) 0x475f93 MOV	(%R10,%R8,1),%R10

  (659) 0x475f97 CMP	%R10,(%R14,%R11,1)

  (659) 0x475f9b JNE	475fab

  (659) 0x475f9d MOV	0xf0(%RSP),%R14

  (659) 0x475fa5 VADDSD	(%R14,%RAX,8),%XMM0,%XMM0

  (659) 0x475fab CMP	$-0x1,%RDX

  (659) 0x475faf JE	475ffa

  (659) 0x475fb1 CMP	(%R12,%R11,1),%R9

  (659) 0x475fb5 JNE	475ffa

  (659) 0x475fb7 MOV	0xf0(%RSP),%RDX

  (659) 0x475fbf MOV	0xd0(%RSP),%R10

  (659) 0x475fc7 LEA	(,%RBX,8),%R14

  (659) 0x475fcf INC	%RBX

  (659) 0x475fd2 VMOVSD	(%RDX,%RAX,8),%XMM13

  (659) 0x475fd7 MOV	0xb0(%RSP),%RDX

  (659) 0x475fdf VMOVSD	%XMM13,(%R10,%R14,1)

  (659) 0x475fe5 MOV	0xa8(%RSP),%R10

  (659) 0x475fed VADDSD	%XMM13,%XMM2,%XMM2

  (659) 0x475ff2 MOV	(%RDX,%R11,1),%R11

  (659) 0x475ff6 MOV	%R11,(%R10,%R14,1)

  (659) 0x475ffa INC	%RAX

  (659) 0x475ffd CMP	%RAX,(%RSI)

  (659) 0x476000 JG	475f70

(655) 0x476006 VMOVQ	%XMM8,%R10

(655) 0x47600b VMOVQ	%XMM3,%R9

(655) 0x476010 JMP	475a9f

0x476015 NOPW	%CS:(%RAX,%RAX,1)

(655) 0x476020 MOV	%RCX,%R8

(655) 0x476023 JMP	475ac2

(655) 0x476028 MOV	0x40(%RSP),%R11

(655) 0x47602d MOV	%RSI,0x98(%RSP)

(655) 0x476035 VMOVQ	%R9,%XMM4

(655) 0x47603a MOV	%RCX,%RSI

(655) 0x47603d VMOVQ	%XMM13,%R15

(655) 0x476042 MOV	%RDX,%RCX

(655) 0x476045 NOPW	%CS:(%RAX,%RAX,1)

  (658) 0x476050 MOV	(%RDI,%RAX,8),%RDX

  (658) 0x476054 CMPQ	$-0x3,(%R11,%RDX,8)

  (658) 0x476059 LEA	(,%RDX,8),%R14

  (658) 0x476061 JE	476071

  (658) 0x476063 MOV	0xf0(%RSP),%R9

  (658) 0x47606b VADDSD	(%R9,%RAX,8),%XMM0,%XMM0

  (658) 0x476071 CMP	$-0x1,%RDX

  (658) 0x476075 JE	4760c0

  (658) 0x476077 CMP	(%RBX,%R14,1),%R8

  (658) 0x47607b JNE	4760c0

  (658) 0x47607d MOV	0xf0(%RSP),%R9

  (658) 0x476085 LEA	(,%RSI,8),%RDX

  (658) 0x47608d INC	%RSI

  (658) 0x476090 VMOVSD	(%R9,%RAX,8),%XMM5

  (658) 0x476096 MOV	0xd0(%RSP),%R9

  (658) 0x47609e VADDSD	%XMM5,%XMM2,%XMM2

  (658) 0x4760a2 VMOVSD	%XMM5,(%R9,%RDX,1)

  (658) 0x4760a8 MOV	0xb0(%RSP),%R9

  (658) 0x4760b0 MOV	(%R9,%R14,1),%R14

  (658) 0x4760b4 MOV	0xa8(%RSP),%R9

  (658) 0x4760bc MOV	%R14,(%R9,%RDX,1)

  (658) 0x4760c0 INC	%RAX

  (658) 0x4760c3 CMP	%RAX,(%RCX)

  (658) 0x4760c6 JG	476050

(655) 0x4760c8 MOV	%RSI,%RCX

(655) 0x4760cb VMOVQ	%XMM4,%R9

(655) 0x4760d0 MOV	0x98(%RSP),%RSI

(655) 0x4760d8 VMOVQ	%R15,%XMM10

(655) 0x4760dd JMP	475aba

0x4760e2 MOV	%RDI,0x10(%RSP)

0x4760e7 MOV	$0x8,%ESI

0x4760ec MOV	%RBX,%RDI

0x4760ef VMOVSD	%XMM1,0x58(%RSP)

0x4760f5 MOV	%RBX,0x90(%RSP)

0x4760fd MOV	%R11,0x20(%RSP)

0x476102 CALL	5a6c20 <hypre_CAlloc>

0x476107 MOV	0x20(%RSP),%RBX

0x47610c MOV	0x90(%RSP),%RDX

0x476114 MOV	0x10(%RSP),%RDI

0x476119 MOV	%RAX,%R12

0x47611c VMOVSD	0x58(%RSP),%XMM1

0x476122 TEST	%RBX,%RBX

0x476125 JNE	476166

0x476127 XOR	%EBX,%EBX

0x476129 TEST	%RDX,%RDX

0x47612c JLE	47545d

0x476132 SAL	$0x3,%RDX

0x476136 MOV	%RDI,0x58(%RSP)

0x47613b VMOVSD	%XMM1,0x90(%RSP)

0x476144 MOV	%R12,%RDI

0x476147 MOV	$0xff,%ESI

0x47614c XOR	%EBX,%EBX

0x47614e CALL	4110a0 <memset@plt>

0x476153 MOV	0x58(%RSP),%RDI

0x476158 VMOVSD	0x90(%RSP),%XMM1

0x476161 JMP	47545d

0x476166 MOV	%RDI,0x10(%RSP)

0x47616b MOV	$0x8,%ESI

0x476170 MOV	%RBX,%RDI

0x476173 MOV	%RDX,0x20(%RSP)

0x476178 VMOVSD	%XMM1,0x58(%RSP)

0x47617e MOV	%RBX,0x90(%RSP)

0x476186 CALL	5a6c20 <hypre_CAlloc>

0x47618b MOV	0x20(%RSP),%RDX

0x476190 MOV	0x90(%RSP),%R11

0x476198 MOV	0x10(%RSP),%RDI

0x47619d MOV	%RAX,%RBX

0x4761a0 VMOVSD	0x58(%RSP),%XMM1

0x4761a6 TEST	%RDX,%RDX

0x4761a9 JLE	475a4c

0x4761af SAL	$0x3,%RDX

0x4761b3 MOV	%RDI,0x20(%RSP)

0x4761b8 MOV	%R11,0x58(%RSP)

0x4761bd VMOVSD	%XMM1,0x90(%RSP)

0x4761c6 MOV	%R12,%RDI

0x4761c9 MOV	$0xff,%ESI

0x4761ce CALL	4110a0 <memset@plt>

0x4761d3 MOV	0x58(%RSP),%R11

0x4761d8 MOV	0x20(%RSP),%RDI

0x4761dd VMOVSD	0x90(%RSP),%XMM1

0x4761e6 JMP	475a4c

0x4761eb NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.99+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.00+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1666	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.25 to 5.25 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 29.25 to 2.97 cycles (9.85x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 29.25 to 25.50 cycles (1.15x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
memset@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 392 bytes.

General properties

nb instructions	202
nb uops	204
loop length	1027
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.50 cycles
front end	25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	3.50	3.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.50
Dispatch	29.25
DIV/SQRT	7.00-12.00
Overall L1	29.25

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.25 cycles. At this rate:

6% of peak load performance is reached (16.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4752d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd0(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xc8(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x90(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x60(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x98(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x48(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 4760e2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe12>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R11,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 475a13 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x743>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9cd0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x20(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMOVNE %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 475e59 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x13a7d4(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R9,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R11,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %R11,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R11,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a6cb0 <hypre_Free>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a6cb0 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x90(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 476166 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe96>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 475a4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x77c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 475a4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x77c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_3

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.25 to 5.25 cycles (5.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 29.25 to 25.50 cycles (1.15x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597
memset@plt: 3 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 472 bytes. The binary function is storing 392 bytes.

General properties

nb instructions	202
nb uops	204
loop length	1027
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.50 cycles
front end	25.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.50	8.50	8.50	8.50	8.50	8.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	3.50	3.50
cycles	8.50	8.50	8.50	8.50	8.50	8.50	29.25	29.25	29.25	29.25	0.00	0.00	0.00	0.00	3.50	3.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	25.50
Dispatch	29.25
DIV/SQRT	7.00-12.00
Overall L1	29.25

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	4%

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.25 cycles. At this rate:

6% of peak load performance is reached (16.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4752d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xf8(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xd0(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0xc8(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xc0(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xb8(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe8(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x80(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x90(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x60(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x98(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RDI),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RDI),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RDI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RDI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x48(%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RDI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RDI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 4760e2 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe12>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R11,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 475a13 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x743>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9ce0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a9cd0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%RDX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
ADD %RCX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%R10	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%R10,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x20(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMOVNE %R10,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 475e59 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x13a7d4(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R9,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDI,%R11,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R11,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %R11,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (,%R11,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a6cb0 <hypre_Free>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a6cb0 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x90(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 476166 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe96>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 47545d <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x18d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5a6c20 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VMOVSD 0x58(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 475a4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x77c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD %XMM1,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4110a0 <memset@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD 0x90(%RSP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 475a4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x77c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.9–	0.43	0.22
▼Loop 655 - par_multi_interp.c:1593-1660 - exec–	0.12	0.06
○Loop 662 - par_multi_interp.c:1618-1628 - exec	0.30	0.14
○Loop 658 - par_multi_interp.c:1639-1652 - exec	0.00	0.01
○Loop 656 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 664 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 657 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 663 - par_multi_interp.c:1618-1628 - exec	0.00	0.00
○Loop 661 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 659 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 660 - par_multi_interp.c:1639-1652 - exec	0.00	0.00

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