OV - exec - Loop 6088

	Loop Id: 6088	Module: exec	Source: :0-0	Coverage: 1.75%

0x5b8da0 PREFETCHT0	0x200(%RSI)    [2]

0x5b8da7 PREFETCHT0	0x240(%RSI)    [2]

0x5b8dae PREFETCHT0	0x280(%RSI)    [2]

0x5b8db5 PREFETCHT0	0x2c0(%RSI)    [2]

0x5b8dbc VMOVDQU	(%RSI),%YMM1    [2]

0x5b8dc0 VMOVDQU	0x20(%RSI),%YMM2    [2]

0x5b8dc5 VMOVDQU	0x40(%RSI),%YMM3    [2]

0x5b8dca VMOVDQU	0x60(%RSI),%YMM4    [2]

0x5b8dcf VMOVDQU	0x80(%RSI),%YMM5    [2]

0x5b8dd7 VMOVDQU	0xa0(%RSI),%YMM6    [2]

0x5b8ddf VMOVDQU	0xc0(%RSI),%YMM7    [2]

0x5b8de7 VMOVDQU	0xe0(%RSI),%YMM8    [2]

0x5b8def SUB	$0x100,%RCX

0x5b8df6 VMOVNTDQ	%YMM1,(%RDI)    [1]

0x5b8dfa VMOVNTDQ	%YMM2,0x20(%RDI)    [1]

0x5b8dff VMOVNTDQ	%YMM3,0x40(%RDI)    [1]

0x5b8e04 VMOVNTDQ	%YMM4,0x60(%RDI)    [1]

0x5b8e09 VMOVNTDQ	%YMM5,0x80(%RDI)    [1]

0x5b8e11 VMOVNTDQ	%YMM6,0xa0(%RDI)    [1]

0x5b8e19 VMOVNTDQ	%YMM7,0xc0(%RDI)    [1]

0x5b8e21 VMOVNTDQ	%YMM8,0xe0(%RDI)    [1]

0x5b8e29 LEA	0x100(%RDI),%RDI

0x5b8e30 LEA	0x100(%RSI),%RSI

0x5b8e37 CMP	$0x300,%RCX

0x5b8e3e JGE	5b8da0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module
►92.79+	hypre_ParCSRRelaxThreads.extra[...]	ams.c:3659	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.82+	hypre_ParCSRRelaxThreads.extra[...]	ams.c:3659	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_ParCSRRelaxThreads	ams.c:3655	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:272	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.14+	hypre_IJVectorSetValuesPar.ext[...]	IJVector_parcsr.c:443	exec
○	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P6, P7, P8, P9,
Function	__intel_avx_rep_memcpy
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	2.50
Front-end cycles	3.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	24.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	102.40
Bytes prefetched	256.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P6, P7, P8, P9,
Function	__intel_avx_rep_memcpy
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	2.50
Front-end cycles	3.00
P0 cycles	0.67
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00
P15 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	25.00
Nb uops	24.00
Nb loads	8.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	102.40
Bytes prefetched	256.00
Bytes loaded	256.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__intel_avx_rep_memcpy
Source file and lines
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is prefetching 256 bytes. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	25
nb uops	24
loop length	164
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	4.00	4.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

20% of peak load performance is reached (51.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (51.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5b8da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PREFETCHT0 0x200(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x240(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x280(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x2c0(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
VMOVDQU (%RSI),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x20(%RSI),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x40(%RSI),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x60(%RSI),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x80(%RSI),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xa0(%RSI),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xc0(%RSI),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xe0(%RSI),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
SUB $0x100,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVNTDQ %YMM1,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM2,0x20(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM3,0x40(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM4,0x60(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM5,0x80(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM6,0xa0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM7,0xc0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM8,0xe0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
LEA 0x100(%RDI),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x100(%RSI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP $0x300,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JGE 5b8da0 <__intel_avx_rep_memcpy+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Function	__intel_avx_rep_memcpy
Source file and lines
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is prefetching 256 bytes. The binary loop is loading 256 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	25
nb uops	24
loop length	164
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	4.00	4.00
cycles	0.67	0.67	0.67	0.67	0.67	0.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	4.00	4.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	5.00
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

20% of peak load performance is reached (51.20 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
40% of peak store performance is reached (51.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 5b8da0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PREFETCHT0 0x200(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x240(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x280(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
PREFETCHT0 0x2c0(%RSI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.33	N/A
VMOVDQU (%RSI),%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x20(%RSI),%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x40(%RSI),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x60(%RSI),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0x80(%RSI),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xa0(%RSI),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xc0(%RSI),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVDQU 0xe0(%RSI),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
SUB $0x100,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
VMOVNTDQ %YMM1,(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM2,0x20(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM3,0x40(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM4,0x60(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM5,0x80(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM6,0xa0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM7,0xc0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
VMOVNTDQ %YMM8,0xe0(%RDI)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1000	0.50	vect (50.0%)
LEA 0x100(%RDI),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x100(%RSI),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
CMP $0x300,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JGE 5b8da0 <__intel_avx_rep_memcpy+0x150>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code