OV - exec - Loop 5348

	Loop Id: 5348	Module: exec	Source: IJMatrix_parcsr.c:3383-3454 [...]	Coverage: 0.88%

0x581552 MOV	%R13,%R9

0x581555 MOV	0x10(%RBP),%R11

0x581559 MOVSD	(%R11,%R13,8),%XMM0

0x58155f MOV	0x70(%RBP),%R11

0x581563 MOVSD	%XMM0,(%R11,%R10,8)

0x581569 MOV	-0x48(%RBP),%R11

0x58156d INC	%R9

0x581570 INC	%R8

0x581573 CMP	%R14,%R8

0x581576 JE	581841

0x58157c MOV	%R9,%R13

0x58157f MOV	(%RBX,%R9,8),%R9

0x581583 CMP	0x28(%RBP),%R9

0x581587 JL	5815f0

0x581589 CMP	0x30(%RBP),%R9

0x58158d JG	5815f0

0x58158f MOV	0x60(%RBP),%R10

0x581593 MOV	(%R10,%R11,8),%R10

0x581597 CMP	%RCX,%R10

0x58159a JGE	5815b2

0x58159c NOPL	(%RAX)

  (5350) 0x5815a0 MOV	0x68(%RBP),%R11

  (5350) 0x5815a4 CMP	%R9,(%R11,%R10,8)

  (5350) 0x5815a8 JE	581552

  (5350) 0x5815aa INC	%R10

  (5350) 0x5815ad CMP	%R10,%RCX

  (5350) 0x5815b0 JNE	5815a0

0x5815b2 MOV	-0x38(%RBP),%R11

0x5815b6 CMP	%RDX,%R11

0x5815b9 JGE	5818b0

0x5815bf MOV	0x68(%RBP),%R10

0x5815c3 MOV	%R9,(%R10,%R11,8)

0x5815c7 MOV	%R13,%R9

0x5815ca MOV	0x10(%RBP),%R10

0x5815ce MOVSD	(%R10,%R13,8),%XMM0

0x5815d4 MOV	0x70(%RBP),%R10

0x5815d8 MOVSD	%XMM0,(%R10,%R11,8)

0x5815de INC	%R11

0x5815e1 MOV	%R11,-0x38(%RBP)

0x5815e5 JMP	581569

0x5815f0 MOV	0x78(%RBP),%R10

0x5815f4 MOV	(%R10,%R11,8),%R10

0x5815f8 CMP	%RAX,%R10

0x5815fb JGE	581615

0x5815fd NOPL	(%RAX)

  (5349) 0x581600 MOV	0x80(%RBP),%R11

  (5349) 0x581607 CMP	%R9,(%R11,%R10,8)

  (5349) 0x58160b JE	581651

  (5349) 0x58160d INC	%R10

  (5349) 0x581610 CMP	%R10,%RAX

  (5349) 0x581613 JNE	581600

0x581615 CMP	%RDI,%R12

0x581618 JGE	5818e2

0x58161e MOV	%R12,%R11

0x581621 MOV	0x80(%RBP),%R10

0x581628 MOV	%R9,(%R10,%R12,8)

0x58162c MOV	%R13,%R9

0x58162f MOV	0x10(%RBP),%R10

0x581633 MOVSD	(%R10,%R13,8),%XMM0

0x581639 MOV	0x88(%RBP),%R10

0x581640 MOVSD	%XMM0,(%R10,%R12,8)

0x581646 INC	%R11

0x581649 MOV	%R11,%R12

0x58164c JMP	581569

0x581651 MOV	%R13,%R9

0x581654 MOV	0x10(%RBP),%R11

0x581658 MOVSD	(%R11,%R13,8),%XMM0

0x58165e MOV	0x88(%RBP),%R11

0x581665 JMP	581563

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3383 - 3454

--------------------------------------------------------------------------------

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

[...]

3454: 	             indx++;

Coverage (%)	Name	Source Location	Module
►96.76+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.97+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_IJMatrixSetValuesOMPParC[...]	IJMatrix_parcsr.c:3240	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.23
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7, P8, P9,
Function	hypre_IJMatrixSetValuesOMPParCSR.extracted.28
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3388,IJMatrix_parcsr.c:3392-3392,IJMatrix_parcsr.c:3399-3402,IJMatrix_parcsr.c:3422-3422,IJMatrix_parcsr.c:3426-3426,IJMatrix_parcsr.c:3433-3436,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	0.91
Front-end cycles	6.88
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	3.50
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	55.00
Nb loads	23.00
Nb stores	6.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.23
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7, P8, P9,
Function	hypre_IJMatrixSetValuesOMPParCSR.extracted.28
Source	IJMatrix_parcsr.c:3383-3385,IJMatrix_parcsr.c:3388-3388,IJMatrix_parcsr.c:3392-3392,IJMatrix_parcsr.c:3399-3402,IJMatrix_parcsr.c:3422-3422,IJMatrix_parcsr.c:3426-3426,IJMatrix_parcsr.c:3433-3436,IJMatrix_parcsr.c:3454-3454
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	3.25
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	0.91
Front-end cycles	6.88
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	3.50
P5 cycles	3.50
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.50
P15 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.00
Nb uops	55.00
Nb loads	23.00
Nb stores	6.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	48.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR.extracted.28
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3392,3399-3402,3422-3426,3433-3436,3454.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3383-3385,3388,3392,3399-3402,3422,3426,3433-3436,3454.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 3.25 cycles (2.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 0.91 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 6.88 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	57
nb uops	55
loop length	232
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.50	3.50	3.50	3.50	3.50	3.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	1.50	1.50
cycles	3.50	3.50	3.50	3.50	3.50	3.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	7.25
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

9% of peak load performance is reached (25.38 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 58157c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R11,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R11,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 581841 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x921>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JL 5815f0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP 0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JG 5815f0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R10,%R11,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5815b2 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x692>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5818b0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x990>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,(%R10,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R10,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R10,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 581569 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R10,%R11,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 581615 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5818e2 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x9c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R10,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 581569 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R11,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
JMP 581563 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x643>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR.extracted.28
Source file and lines	IJMatrix_parcsr.c:3383-3454
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 3.25 cycles (2.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 0.91 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 6.88 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 184 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	57
nb uops	55
loop length	232
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.50	3.50	3.50	3.50	3.50	3.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	1.50	1.50
cycles	3.50	3.50	3.50	3.50	3.50	3.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	1.50	1.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	7.25
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

9% of peak load performance is reached (25.38 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 58157c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R11,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R11,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
INC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R14,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 581841 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x921>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX,%R9,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP 0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JL 5815f0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP 0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JG 5815f0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R10,%R11,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5815b2 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x692>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RDX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5818b0 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x990>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,(%R10,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R10,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R10,%R11,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 581569 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R10,%R11,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 581615 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x6f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 5818e2 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x9c2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R10,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD %XMM0,(%R10,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 581569 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x649>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOVSD (%R11,%R13,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
JMP 581563 <hypre_IJMatrixSetValuesOMPParCSR.extracted.28+0x643>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code