OV - exec - Loop 3956

	Loop Id: 3956	Module: exec	Source: ams.c:3662-3682	Coverage: 16.02%

0x52bd89 MOV	-0x30(%RBP),%R9

0x52bd8d MOV	-0x40(%RBP),%RCX

0x52bd91 NOPW	%CS:(%RAX,%RAX,1)

0x52bda0 MULSD	%XMM0,%XMM2

0x52bda4 MOV	-0x70(%RBP),%RAX

0x52bda8 DIVSD	(%RAX,%RSI,8),%XMM2

0x52bdad MOV	-0x60(%RBP),%RAX

0x52bdb1 ADDSD	(%RAX,%RSI,8),%XMM2

0x52bdb6 MOVSD	%XMM2,(%RAX,%RSI,8)

  (3955) 0x52bdbb LEA	0x1(%RDX),%RAX

  (3955) 0x52bdbf CMP	-0x78(%RBP),%RDX

  (3955) 0x52bdc3 MOV	%RAX,%RDX

  (3955) 0x52bdc6 JE	52bd5d

  (3955) 0x52bdc8 LEA	(%RCX,%RDX,1),%RSI

  (3955) 0x52bdcc MOV	(%R9,%RSI,8),%RDI

  (3955) 0x52bdd0 UCOMISD	(%R14,%RDI,8),%XMM1

  (3955) 0x52bdd6 JE	52bdbb

0x52bdd8 MOV	-0x68(%RBP),%RAX

0x52bddc MOVSD	(%RAX,%RSI,8),%XMM2

0x52bde1 MOV	0x8(%R9,%RSI,8),%R8

0x52bde6 SUB	%RDI,%R8

0x52bde9 JLE	52bfc7

0x52bdef CMP	$0x8,%R8

0x52bdf3 JB	52becb

0x52bdf9 MOV	%R8,%R9

0x52bdfc SHR	$0x3,%R9

0x52be00 LEA	0x38(,%RDI,8),%R10

0x52be08 NOPL	(%RAX,%RAX,1)

  (3958) 0x52be10 MOV	-0x38(%R12,%R10,1),%R11

  (3958) 0x52be15 MOV	-0x30(%R12,%R10,1),%RAX

  (3958) 0x52be1a MOVSD	(%R15,%R11,8),%XMM3

  (3958) 0x52be20 MULSD	-0x38(%R14,%R10,1),%XMM3

  (3958) 0x52be27 MOVSD	(%R15,%RAX,8),%XMM4

  (3958) 0x52be2d MULSD	-0x30(%R14,%R10,1),%XMM4

  (3958) 0x52be34 ADDSD	%XMM3,%XMM4

  (3958) 0x52be38 MOV	-0x28(%R12,%R10,1),%RAX

  (3958) 0x52be3d MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be43 MULSD	-0x28(%R14,%R10,1),%XMM3

  (3958) 0x52be4a MOV	-0x20(%R12,%R10,1),%RAX

  (3958) 0x52be4f MOVSD	(%R15,%RAX,8),%XMM5

  (3958) 0x52be55 MULSD	-0x20(%R14,%R10,1),%XMM5

  (3958) 0x52be5c ADDSD	%XMM3,%XMM5

  (3958) 0x52be60 MOV	-0x18(%R12,%R10,1),%RAX

  (3958) 0x52be65 MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be6b MULSD	-0x18(%R14,%R10,1),%XMM3

  (3958) 0x52be72 MOV	-0x10(%R12,%R10,1),%RAX

  (3958) 0x52be77 MOVSD	(%R15,%RAX,8),%XMM6

  (3958) 0x52be7d MULSD	-0x10(%R14,%R10,1),%XMM6

  (3958) 0x52be84 ADDSD	%XMM4,%XMM5

  (3958) 0x52be88 ADDSD	%XMM3,%XMM6

  (3958) 0x52be8c MOV	-0x8(%R12,%R10,1),%RAX

  (3958) 0x52be91 MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be97 MULSD	-0x8(%R14,%R10,1),%XMM3

  (3958) 0x52be9e ADDSD	%XMM6,%XMM3

  (3958) 0x52bea2 ADDSD	%XMM5,%XMM3

  (3958) 0x52bea6 MOV	(%R12,%R10,1),%RAX

  (3958) 0x52beaa MOVSD	(%R15,%RAX,8),%XMM4

  (3958) 0x52beb0 MULSD	(%R14,%R10,1),%XMM4

  (3958) 0x52beb6 ADDSD	%XMM3,%XMM4

  (3958) 0x52beba SUBSD	%XMM4,%XMM2

  (3958) 0x52bebe ADD	$0x40,%R10

  (3958) 0x52bec2 DEC	%R9

  (3958) 0x52bec5 JNE	52be10

0x52becb MOV	%R8D,%R9D

0x52bece AND	$0x7,%R9D

0x52bed2 DEC	%R9

0x52bed5 CMP	$0x6,%R9

0x52bed9 JA	52bf11

0x52bf11 MOV	-0x30(%RBP),%R9

0x52bf15 JMP	52bfc7

0x52bfc7 MOV	-0x58(%RBP),%RAX

0x52bfcb MOV	(%RAX,%RSI,8),%RDI

0x52bfcf MOV	0x8(%RAX,%RSI,8),%R8

0x52bfd4 SUB	%RDI,%R8

0x52bfd7 JLE	52bda0

0x52bfdd CMP	$0x8,%R8

0x52bfe1 JB	52c0b5

0x52bfe7 MOV	%R8,%R9

0x52bfea SHR	$0x3,%R9

0x52bfee LEA	0x38(,%RDI,8),%R10

0x52bff6 MOV	-0x38(%RBP),%RCX

0x52bffa NOPW	(%RAX,%RAX,1)

  (3957) 0x52c000 MOV	-0x38(%R13,%R10,1),%RAX

  (3957) 0x52c005 MOV	-0x30(%R13,%R10,1),%R11

  (3957) 0x52c00a MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c00f MULSD	-0x38(%RBX,%R10,1),%XMM3

  (3957) 0x52c016 MOVSD	(%RCX,%R11,8),%XMM4

  (3957) 0x52c01c MULSD	-0x30(%RBX,%R10,1),%XMM4

  (3957) 0x52c023 ADDSD	%XMM3,%XMM4

  (3957) 0x52c027 MOV	-0x28(%R13,%R10,1),%RAX

  (3957) 0x52c02c MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c031 MULSD	-0x28(%RBX,%R10,1),%XMM3

  (3957) 0x52c038 MOV	-0x20(%R13,%R10,1),%RAX

  (3957) 0x52c03d MOVSD	(%RCX,%RAX,8),%XMM5

  (3957) 0x52c042 MULSD	-0x20(%RBX,%R10,1),%XMM5

  (3957) 0x52c049 ADDSD	%XMM3,%XMM5

  (3957) 0x52c04d MOV	-0x18(%R13,%R10,1),%RAX

  (3957) 0x52c052 MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c057 MULSD	-0x18(%RBX,%R10,1),%XMM3

  (3957) 0x52c05e MOV	-0x10(%R13,%R10,1),%RAX

  (3957) 0x52c063 MOVSD	(%RCX,%RAX,8),%XMM6

  (3957) 0x52c068 MULSD	-0x10(%RBX,%R10,1),%XMM6

  (3957) 0x52c06f ADDSD	%XMM4,%XMM5

  (3957) 0x52c073 ADDSD	%XMM3,%XMM6

  (3957) 0x52c077 MOV	-0x8(%R13,%R10,1),%RAX

  (3957) 0x52c07c MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c081 MULSD	-0x8(%RBX,%R10,1),%XMM3

  (3957) 0x52c088 ADDSD	%XMM6,%XMM3

  (3957) 0x52c08c ADDSD	%XMM5,%XMM3

  (3957) 0x52c090 MOV	(%R13,%R10,1),%RAX

  (3957) 0x52c095 MOVSD	(%RCX,%RAX,8),%XMM4

  (3957) 0x52c09a MULSD	(%RBX,%R10,1),%XMM4

  (3957) 0x52c0a0 ADDSD	%XMM3,%XMM4

  (3957) 0x52c0a4 SUBSD	%XMM4,%XMM2

  (3957) 0x52c0a8 ADD	$0x40,%R10

  (3957) 0x52c0ac DEC	%R9

  (3957) 0x52c0af JNE	52c000

0x52c0b5 MOV	%R8D,%R9D

0x52c0b8 AND	$0x7,%R9D

0x52c0bc DEC	%R9

0x52c0bf CMP	$0x6,%R9

0x52c0c3 JA	52bd89

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
►95.93+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.98+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_ParCSRRelaxThreads	ams.c:3866	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:272	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.extracted.57
Source	ams.c:3662-3662,ams.c:3669-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	2.22
CQA cycles if fully vectorized	0.63
Front-end cycles	5.00
P0 cycles	3.33
P1 cycles	3.33
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	40.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	7.00
FLOP/cycle	0.60
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.25
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.extracted.57
Source	ams.c:3662-3662,ams.c:3669-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	2.22
CQA cycles if fully vectorized	0.63
Front-end cycles	5.00
P0 cycles	3.33
P1 cycles	3.33
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	3.33
P5 cycles	3.33
P6 cycles	3.75
P7 cycles	3.75
P8 cycles	3.75
P9 cycles	3.75
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	40.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	7.00
FLOP/cycle	0.60
Nb FLOP add-sub	1.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads.extracted.57
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3677,3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction
1: multiply
1: divide

The binary loop is loading 112 bytes (14 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	40
loop length	208
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	3.75	3.75	3.75	3.75	1.00	1.00	0.50	0.50	0.50	0.50
cycles	3.33	3.33	3.33	3.33	3.33	3.33	3.75	3.75	3.75	3.75	1.00	1.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	5.00
Dispatch	3.75
DIV/SQRT	4.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

8% of peak load performance is reached (22.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 52bda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MULSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DIVSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM2,(%RAX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R9,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 52bfc7 <hypre_ParCSRRelaxThreads.extracted.57+0x317>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 52becb <hypre_ParCSRRelaxThreads.extracted.57+0x21b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 52bf11 <hypre_ParCSRRelaxThreads.extracted.57+0x261>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 52bfc7 <hypre_ParCSRRelaxThreads.extracted.57+0x317>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 52bda0 <hypre_ParCSRRelaxThreads.extracted.57+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 52c0b5 <hypre_ParCSRRelaxThreads.extracted.57+0x405>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 52bd89 <hypre_ParCSRRelaxThreads.extracted.57+0xd9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_ParCSRRelaxThreads.extracted.57
Source file and lines	ams.c:3662-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction
1: multiply
1: divide

The binary loop is loading 112 bytes (14 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	44
nb uops	40
loop length	208
used x86 registers	8
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	7
ADD-SUB / MUL ratio	1.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	3.75	3.75	3.75	3.75	1.00	1.00	0.50	0.50	0.50	0.50
cycles	3.33	3.33	3.33	3.33	3.33	3.33	3.75	3.75	3.75	3.75	1.00	1.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	5.00
Dispatch	3.75
DIV/SQRT	4.00
Overall L1	5.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

8% of peak load performance is reached (22.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 52bda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MULSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
DIVSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADDSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOVSD %XMM2,(%RAX,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD (%RAX,%RSI,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R9,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 52bfc7 <hypre_ParCSRRelaxThreads.extracted.57+0x317>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 52becb <hypre_ParCSRRelaxThreads.extracted.57+0x21b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JA 52bf11 <hypre_ParCSRRelaxThreads.extracted.57+0x261>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 52bfc7 <hypre_ParCSRRelaxThreads.extracted.57+0x317>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 52bda0 <hypre_ParCSRRelaxThreads.extracted.57+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 52c0b5 <hypre_ParCSRRelaxThreads.extracted.57+0x405>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA 0x38(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 52bd89 <hypre_ParCSRRelaxThreads.extracted.57+0xd9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code