OV - exec - Loop 3894

	Loop Id: 3894	Module: exec	Source: ams.c:3388-3389	Coverage: 0.21%

0x529870 MOVSD	-0x38(%R8),%XMM0    [1]

0x529876 MOVSD	-0x30(%R8),%XMM2    [1]

0x52987c MOVSD	-0x28(%R8),%XMM3    [1]

0x529882 MOVSD	-0x20(%R8),%XMM4    [1]

0x529888 ANDPD	%XMM8,%XMM0

0x52988d ADDSD	%XMM1,%XMM0

0x529891 ANDPD	%XMM8,%XMM2

0x529896 ANDPD	%XMM8,%XMM3

0x52989b ADDSD	%XMM2,%XMM3

0x52989f ADDSD	%XMM0,%XMM3

0x5298a3 ANDPD	%XMM8,%XMM4

0x5298a8 MOVSD	-0x18(%R8),%XMM0    [1]

0x5298ae ANDPD	%XMM8,%XMM0

0x5298b3 ADDSD	%XMM4,%XMM0

0x5298b7 MOVSD	-0x10(%R8),%XMM2    [1]

0x5298bd ANDPD	%XMM8,%XMM2

0x5298c2 ADDSD	%XMM0,%XMM2

0x5298c6 ADDSD	%XMM3,%XMM2

0x5298ca MOVSD	-0x8(%R8),%XMM0    [1]

0x5298d0 ANDPD	%XMM8,%XMM0

0x5298d5 MOVSD	(%R8),%XMM1    [1]

0x5298da ANDPD	%XMM8,%XMM1

0x5298df ADDSD	%XMM0,%XMM1

0x5298e3 ADDSD	%XMM2,%XMM1

0x5298e7 ADD	$0x40,%R8

0x5298eb DEC	%RDI

0x5298ee JNE	529870

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3388 - 3389

--------------------------------------------------------------------------------

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

Coverage (%)	Name	Source Location	Module
►96.85+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.15+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_ParCSRComputeL1NormsThre[...]	ams.c:3363	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1407	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.60
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	hypre_ParCSRComputeL1NormsThreads.extracted
Source	ams.c:3388-3389
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	3.07
CQA cycles if fully vectorized	1.00
Front-end cycles	3.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.60
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.00
Bottlenecks
Function	hypre_ParCSRComputeL1NormsThreads.extracted
Source	ams.c:3388-3389
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	3.07
CQA cycles if fully vectorized	1.00
Front-end cycles	3.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	26.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.00
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	33.33
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads.extracted
Source file and lines	ams.c:3388-3389
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3388-3389.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	128
used x86 registers	2
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.00	2.00	2.00	2.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.00	2.00	2.00	2.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	3.25
Dispatch	4.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

3% of peak load performance is reached (8.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 529870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOVSD -0x38(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x30(%R8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x28(%R8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x20(%R8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDPD %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOVSD -0x18(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD -0x10(%R8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD -0x8(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 529870 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1c90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_ParCSRComputeL1NormsThreads.extracted
Source file and lines	ams.c:3388-3389
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	26
loop length	128
used x86 registers	2
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	2.00	2.00	2.00	2.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	2.00	2.00	2.00	2.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	3.25
Dispatch	4.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

3% of peak load performance is reached (8.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 529870

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOVSD -0x38(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x30(%R8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x28(%R8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVSD -0x20(%R8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDPD %XMM8,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM0,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM8,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOVSD -0x18(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM4,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD -0x10(%R8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOVSD -0x8(%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
MOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
ANDPD %XMM8,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADDSD %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ADD $0x40,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 529870 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1c90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code