OV - exec - Loop 3264

	Loop Id: 3264	Module: exec	Source: par_strength.c:2011-2048	Coverage: 0.07%

0x501110 INC	%RSI

0x501113 MOV	-0x40(%RBP),%RDI

0x501117 CMP	0x8(%RDI,%RAX,8),%RSI

0x50111c JGE	5010f6

0x50111e MOV	(%R15,%RSI,8),%RDI

0x501122 MOV	-0x70(%RBP),%R8

0x501126 CMPQ	$0,(%R8,%RDI,8)

0x50112b JLE	501152

0x50112d MOV	0x78(%RBP),%R8

0x501131 MOV	(%R8,%RDI,8),%R8

0x501135 CMP	%RCX,(%R14,%R8,8)

0x501139 JGE	501152

0x50113b MOV	-0x30(%RBP),%R9

0x50113f MOV	%R9,(%R14,%R8,8)

0x501143 MOV	0x30(%RBP),%R10

0x501147 MOV	(%R10),%R10

0x50114a MOV	%R8,(%R10,%R9,8)

0x50114e INCQ	-0x30(%RBP)

0x501152 MOV	-0x40(%RBP),%R9

0x501156 MOV	(%R9,%RDI,8),%R8

0x50115a MOV	0x8(%R9,%RDI,8),%R9

0x50115f JMP	501173

  (3266) 0x501170 INC	%R8

  (3266) 0x501173 CMP	%R9,%R8

  (3266) 0x501176 JGE	5011c0

  (3266) 0x501178 MOV	(%R15,%R8,8),%R10

  (3266) 0x50117c MOV	-0x70(%RBP),%R11

  (3266) 0x501180 CMPQ	$0,(%R11,%R10,8)

  (3266) 0x501185 JLE	501170

  (3266) 0x501187 MOV	0x78(%RBP),%R11

  (3266) 0x50118b MOV	(%R11,%R10,8),%R10

  (3266) 0x50118f CMP	%RBX,%R10

  (3266) 0x501192 JE	501170

  (3266) 0x501194 CMP	%RCX,(%R14,%R10,8)

  (3266) 0x501198 JGE	501170

  (3266) 0x50119a MOV	-0x30(%RBP),%R9

  (3266) 0x50119e MOV	%R9,(%R14,%R10,8)

  (3266) 0x5011a2 MOV	0x30(%RBP),%R11

  (3266) 0x5011a6 MOV	(%R11),%R11

  (3266) 0x5011a9 MOV	%R10,(%R11,%R9,8)

  (3266) 0x5011ad INCQ	-0x30(%RBP)

  (3266) 0x5011b1 MOV	-0x40(%RBP),%R9

  (3266) 0x5011b5 MOV	0x8(%R9,%RDI,8),%R9

  (3266) 0x5011ba JMP	501170

0x5011c0 MOV	0x10(%RBP),%R9

0x5011c4 MOV	(%R9,%RDI,8),%R8

0x5011c8 MOV	0x8(%R9,%RDI,8),%R9

0x5011cd JMP	5011d3

  (3265) 0x5011d0 INC	%R8

  (3265) 0x5011d3 CMP	%R9,%R8

  (3265) 0x5011d6 JGE	501110

  (3265) 0x5011dc MOV	0x18(%RBP),%R10

  (3265) 0x5011e0 MOV	(%R10,%R8,8),%R10

  (3265) 0x5011e4 MOV	0x70(%RBP),%R11

  (3265) 0x5011e8 CMPQ	$0,(%R11,%R10,8)

  (3265) 0x5011ed JLE	5011d0

  (3265) 0x5011ef MOV	0x80(%RBP),%R11

  (3265) 0x5011f6 MOV	(%R11,%R10,8),%R10

  (3265) 0x5011fa CMP	%RDX,(%R13,%R10,8)

  (3265) 0x5011ff JGE	5011d0

  (3265) 0x501201 MOV	-0x38(%RBP),%R9

  (3265) 0x501205 MOV	%R9,(%R13,%R10,8)

  (3265) 0x50120a MOV	(%R12),%R11

  (3265) 0x50120e MOV	%R10,(%R11,%R9,8)

  (3265) 0x501212 INCQ	-0x38(%RBP)

  (3265) 0x501216 MOV	0x10(%RBP),%R9

  (3265) 0x50121a MOV	0x8(%R9,%RDI,8),%R9

  (3265) 0x50121f JMP	5011d0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048

--------------------------------------------------------------------------------

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module
►97.37+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.41+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1668	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:617	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.63
Front-end cycles	3.25
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	18.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.60
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.63
Front-end cycles	3.25
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	18.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	33.60
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 24 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.25 cycles (1.54x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26
nb uops	26
loop length	96
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

11% of peak load performance is reached (28.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 50111e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP 0x8(%RDI,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 5010f6 <hypre_BoomerAMGCreate2ndS.extracted.17+0xce6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R15,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%R8,%RDI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 501152 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,(%R14,%R8,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 501152 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,(%R14,%R8,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,(%R10,%R9,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INCQ -0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	N/A
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 501173 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd63>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 5011d3 <hypre_BoomerAMGCreate2ndS.extracted.17+0xdc3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGCreate2ndS.extracted.17
Source file and lines	par_strength.c:2011-2048
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=24
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.62 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.25 cycles (1.54x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	26
nb uops	26
loop length	96
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.25 cycles
front end	3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.25
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

11% of peak load performance is reached (28.80 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 50111e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP 0x8(%RDI,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 5010f6 <hypre_BoomerAMGCreate2ndS.extracted.17+0xce6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R15,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%R8,%RDI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 501152 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x78(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,(%R14,%R8,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 501152 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd42>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,(%R14,%R8,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,(%R10,%R9,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INCQ -0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	N/A
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 501173 <hypre_BoomerAMGCreate2ndS.extracted.17+0xd63>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%R9,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 5011d3 <hypre_BoomerAMGCreate2ndS.extracted.17+0xdc3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code