OV - exec - Loop 1502

	Loop Id: 1502	Module: exec	Source: par_lr_interp.c:1624-1627	Coverage: 0.10%

0x4846f0 ADD	$0x20,%RSI

0x4846f4 DEC	%R15

0x4846f7 JE	48462f

0x4846fd MOV	-0xa8(%RBP),%RAX    [3]

0x484704 MOV	-0x18(%RAX,%RSI,1),%R12    [1]

0x484709 XOR	%R11D,%R11D

0x48470c CMP	%RDI,(%RBX,%R12,8)    [10]

0x484710 SETGE	%R11B

0x484714 XOR	%EAX,%EAX

0x484716 CMP	%R13,%R12

0x484719 SETE	%AL

0x48471c CMP	%R11B,%AL

0x48471f CMOVA	%EAX,%R11D

0x484723 CMP	$0x1,%R11B

0x484727 JNE	484758

0x484729 MOV	-0x60(%RBP),%RAX    [3]

0x48472d MOVSD	-0x18(%RAX,%RSI,1),%XMM9    [9]

0x484734 MOVAPD	%XMM9,%XMM10

0x484739 MULSD	%XMM7,%XMM10

0x48473e CMPSD	$0x1,%XMM8,%XMM10

0x484744 ANDPD	%XMM10,%XMM9

0x484749 ANDNPD	%XMM1,%XMM10

0x48474e ORPD	%XMM9,%XMM10

0x484753 ADDSD	%XMM10,%XMM6

0x484758 MOV	-0xa8(%RBP),%RAX    [3]

0x48475f MOV	-0x10(%RAX,%RSI,1),%RAX    [8]

0x484764 XOR	%R11D,%R11D

0x484767 CMP	%RDI,(%RBX,%RAX,8)    [10]

0x48476b SETGE	%R11B

0x48476f XOR	%R12D,%R12D

0x484772 CMP	%R13,%RAX

0x484775 SETE	%R12B

0x484779 CMP	%R11B,%R12B

0x48477c CMOVA	%R12D,%R11D

0x484780 CMP	$0x1,%R11B

0x484784 JNE	4847b5

0x484786 MOV	-0x60(%RBP),%RAX    [3]

0x48478a MOVSD	-0x10(%RAX,%RSI,1),%XMM9    [7]

0x484791 MOVAPD	%XMM9,%XMM10

0x484796 MULSD	%XMM7,%XMM10

0x48479b CMPSD	$0x1,%XMM8,%XMM10

0x4847a1 ANDPD	%XMM10,%XMM9

0x4847a6 ANDNPD	%XMM1,%XMM10

0x4847ab ORPD	%XMM9,%XMM10

0x4847b0 ADDSD	%XMM10,%XMM6

0x4847b5 MOV	-0xa8(%RBP),%RAX    [3]

0x4847bc MOV	-0x8(%RAX,%RSI,1),%RAX    [6]

0x4847c1 XOR	%R11D,%R11D

0x4847c4 CMP	%RDI,(%RBX,%RAX,8)    [10]

0x4847c8 SETGE	%R11B

0x4847cc XOR	%R12D,%R12D

0x4847cf CMP	%R13,%RAX

0x4847d2 SETE	%R12B

0x4847d6 CMP	%R11B,%R12B

0x4847d9 CMOVA	%R12D,%R11D

0x4847dd CMP	$0x1,%R11B

0x4847e1 JNE	484812

0x4847e3 MOV	-0x60(%RBP),%RAX    [3]

0x4847e7 MOVSD	-0x8(%RAX,%RSI,1),%XMM9    [5]

0x4847ee MOVAPD	%XMM9,%XMM10

0x4847f3 MULSD	%XMM7,%XMM10

0x4847f8 CMPSD	$0x1,%XMM8,%XMM10

0x4847fe ANDPD	%XMM10,%XMM9

0x484803 ANDNPD	%XMM1,%XMM10

0x484808 ORPD	%XMM9,%XMM10

0x48480d ADDSD	%XMM10,%XMM6

0x484812 MOV	-0xa8(%RBP),%RAX    [3]

0x484819 MOV	(%RAX,%RSI,1),%RAX    [4]

0x48481d XOR	%R11D,%R11D

0x484820 CMP	%RDI,(%RBX,%RAX,8)    [10]

0x484824 SETGE	%R11B

0x484828 XOR	%R12D,%R12D

0x48482b CMP	%R13,%RAX

0x48482e SETE	%R12B

0x484832 CMP	%R11B,%R12B

0x484835 CMOVA	%R12D,%R11D

0x484839 CMP	$0x1,%R11B

0x48483d JNE	4846f0

0x484843 MOV	-0x60(%RBP),%RAX    [3]

0x484847 MOVSD	(%RAX,%RSI,1),%XMM9    [2]

0x48484d MOVAPD	%XMM9,%XMM10

0x484852 MULSD	%XMM7,%XMM10

0x484857 CMPSD	$0x1,%XMM8,%XMM10

0x48485d ANDPD	%XMM10,%XMM9

0x484862 ANDNPD	%XMM1,%XMM10

0x484867 ORPD	%XMM9,%XMM10

0x48486c ADDSD	%XMM10,%XMM6

0x484871 JMP	4846f0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1624 - 1627

--------------------------------------------------------------------------------

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

Coverage (%)	Name	Source Location	Module
►95.08+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.21+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:847	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.92
CQA speedup if FP arith vectorized	2.68
CQA speedup if fully vectorized	7.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1624-1627
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.30
CQA cycles if fully vectorized	1.57
Front-end cycles	11.50
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	92.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.70
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.91
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.02
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.14
Vector-efficiency ratio all	17.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.64

Metric	Value
CQA speedup if no scalar integer	1.92
CQA speedup if FP arith vectorized	2.68
CQA speedup if fully vectorized	7.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.72
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source	par_lr_interp.c:1624-1627
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	4.30
CQA cycles if fully vectorized	1.57
Front-end cycles	11.50
P0 cycles	6.67
P1 cycles	6.67
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	5.00
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	6.00
P11 cycles	6.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	92.00
Nb loads	20.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.70
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.91
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.02
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.14
Vector-efficiency ratio all	17.38
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.64

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1624-1627
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624-1627.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 6.00 cycles (1.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.50 to 1.57 cycles (7.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	88
nb uops	92
loop length	390
used x86 registers	9
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	5.00	5.00	5.00	5.00	6.00	6.00	6.00	6.00	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	5.00	5.00	5.00	5.00	6.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	6.67
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	39%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

5% of peak load performance is reached (13.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 6.67 cycles (1.72x speedup).

ASM code

In the binary file, the address of the loop is: 4846fd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 48462f <hypre_BoomerAMGBuildExtPIInterp.extracted+0x169f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x18(%RAX,%RSI,1),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%R12,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %EAX,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 484758 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x17c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x18(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x10(%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4847b5 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1825>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x10(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 484812 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1882>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x8(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4846f0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1760>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
JMP 4846f0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1760>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildExtPIInterp.extracted
Source file and lines	par_lr_interp.c:1624-1627
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 6.00 cycles (1.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVA: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1627

Type of elements and instruction set

12 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: multiply

The binary loop is loading 160 bytes (20 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	88
nb uops	92
loop length	390
used x86 registers	9
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	5.00	5.00	5.00	5.00	6.00	6.00	6.00	6.00	0.00	0.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	5.00	5.00	5.00	5.00	6.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.50
Dispatch	6.67
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	39%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

INT+FP

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

5% of peak load performance is reached (13.91 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4846fd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
ADD $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 48462f <hypre_BoomerAMGBuildExtPIInterp.extracted+0x169f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x18(%RAX,%RSI,1),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%R12,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%AL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %EAX,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 484758 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x17c8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x18(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x10(%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4847b5 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1825>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x10(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 484812 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1882>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD -0x8(%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RSI,1),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %RDI,(%RBX,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
SETGE %R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SETE %R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11B,%R12B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVA %R12D,%R11D	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CMP $0x1,%R11B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4846f0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1760>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RAX,%RSI,1),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOVAPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MULSD %XMM7,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50	scal (12.5%)
CMPSD $0x1,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
ANDPD %XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ANDNPD %XMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ORPD %XMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADDSD %XMM10,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
JMP 4846f0 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1760>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code