OV - exec - Loop 1158

0x46ed90 MOV	-0x150(%RBP),%RSI

0x46ed97 INC	%RSI

0x46ed9a CMP	-0xd0(%RBP),%RSI

0x46eda1 JGE	46f1b1

0x46eda7 MOV	-0x90(%RBP),%RDX

0x46edae MOV	%RSI,-0x150(%RBP)

0x46edb5 MOV	(%RDX,%RSI,8),%RDI

0x46edb9 MOV	-0x98(%RBP),%RDX

0x46edc0 MOV	%RAX,(%RDX,%RDI,8)

0x46edc4 MOV	-0x40(%RBP),%RDX

0x46edc8 MOV	%RCX,(%RDX,%RDI,8)

0x46edcc MOV	-0xa8(%RBP),%RDX

0x46edd3 MOV	(%RDX,%RDI,8),%R8

0x46edd7 JMP	46edea

  (1161) 0x46edd9 MOV	-0x58(%RBP),%R14

  (1161) 0x46eddd NOPL	(%RAX)

  (1161) 0x46ede0 INC	%R8

  (1161) 0x46ede3 MOV	-0xa8(%RBP),%RDX

  (1161) 0x46edea CMP	0x8(%RDX,%RDI,8),%R8

  (1161) 0x46edef JGE	46f0c0

  (1161) 0x46edf5 MOV	-0x118(%RBP),%RDX

  (1161) 0x46edfc MOV	(%RDX,%R8,8),%R13

  (1161) 0x46ee00 MOV	-0x108(%RBP),%RDX

  (1161) 0x46ee07 CMP	%R14,(%RDX,%R13,8)

  (1161) 0x46ee0b JNE	46ede0

  (1161) 0x46ee0d MOV	-0x60(%RBP),%RDX

  (1161) 0x46ee11 MOV	0x8(%RDX,%R13,8),%R10

  (1161) 0x46ee16 TEST	%R10,%R10

  (1161) 0x46ee19 JLE	46ef6f

  (1161) 0x46ee1f MOV	-0x98(%RBP),%RDX

  (1161) 0x46ee26 MOV	%R13,-0x38(%RBP)

  (1161) 0x46ee2a MOV	(%RDX,%R13,8),%R11

  (1161) 0x46ee2e ADD	%R11,%R10

  (1161) 0x46ee31 LEA	0x1(%R11),%RDX

  (1161) 0x46ee35 CMP	%RDX,%R10

  (1161) 0x46ee38 CMOVLE	%RDX,%R10

  (1161) 0x46ee3c MOV	-0x48(%RBP),%RDX

  (1161) 0x46ee40 MOV	-0x8(%RDX,%R12,8),%RSI

  (1161) 0x46ee45 MOV	%R10,%RDX

  (1161) 0x46ee48 SUB	%R11,%RDX

  (1161) 0x46ee4b CMP	$0x4,%RDX

  (1161) 0x46ee4f MOV	%RDX,-0x78(%RBP)

  (1161) 0x46ee53 JAE	46eea8

  (1161) 0x46ee55 MOV	-0x78(%RBP),%R9

  (1161) 0x46ee59 MOV	%R9,%RDX

  (1161) 0x46ee5c AND	$-0x4,%RDX

  (1161) 0x46ee60 CMP	%R9,%RDX

  (1161) 0x46ee63 JAE	46ef67

  (1161) 0x46ee69 ADD	%RDX,%R11

  (1161) 0x46ee6c MOV	-0x58(%RBP),%R14

  (1161) 0x46ee70 MOV	-0x38(%RBP),%R13

  (1161) 0x46ee74 JMP	46ee8c

    (1164) 0x46ee80 INC	%R11

    (1164) 0x46ee83 CMP	%R11,%R10

    (1164) 0x46ee86 JE	46ef6f

    (1164) 0x46ee8c MOV	(%RSI,%R11,8),%RDX

    (1164) 0x46ee90 CMP	%RDI,(%RBX,%RDX,8)

    (1164) 0x46ee94 JE	46ee80

    (1164) 0x46ee96 INC	%RAX

    (1164) 0x46ee99 MOV	-0x60(%RBP),%R9

    (1164) 0x46ee9d INCQ	0x8(%R9,%RDI,8)

    (1164) 0x46eea2 MOV	%RDI,(%RBX,%RDX,8)

    (1164) 0x46eea6 JMP	46ee80

  (1161) 0x46eea8 MOV	%RDX,%R14

  (1161) 0x46eeab SHR	$0x2,%R14

  (1161) 0x46eeaf LEA	(%RSI,%R11,8),%R13

  (1161) 0x46eeb3 ADD	$0x18,%R13

  (1161) 0x46eeb7 JMP	46eec9

    (1165) 0x46eec0 ADD	$0x20,%R13

    (1165) 0x46eec4 DEC	%R14

    (1165) 0x46eec7 JE	46ee55

    (1165) 0x46eec9 MOV	-0x18(%R13),%RDX

    (1165) 0x46eecd CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46eed1 JNE	46ef00

    (1165) 0x46eed3 MOV	-0x10(%R13),%RDX

    (1165) 0x46eed7 CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46eedb JNE	46ef1a

    (1165) 0x46eedd MOV	-0x8(%R13),%RDX

    (1165) 0x46eee1 CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46eee5 JNE	46ef34

    (1165) 0x46eee7 MOV	(%R13),%RDX

    (1165) 0x46eeeb CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46eeef JE	46eec0

    (1165) 0x46eef1 JMP	46ef52

    (1165) 0x46ef00 INC	%RAX

    (1165) 0x46ef03 MOV	-0x60(%RBP),%R9

    (1165) 0x46ef07 INCQ	0x8(%R9,%RDI,8)

    (1165) 0x46ef0c MOV	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef10 MOV	-0x10(%R13),%RDX

    (1165) 0x46ef14 CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef18 JE	46eedd

    (1165) 0x46ef1a INC	%RAX

    (1165) 0x46ef1d MOV	-0x60(%RBP),%R9

    (1165) 0x46ef21 INCQ	0x8(%R9,%RDI,8)

    (1165) 0x46ef26 MOV	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef2a MOV	-0x8(%R13),%RDX

    (1165) 0x46ef2e CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef32 JE	46eee7

    (1165) 0x46ef34 INC	%RAX

    (1165) 0x46ef37 MOV	-0x60(%RBP),%R9

    (1165) 0x46ef3b INCQ	0x8(%R9,%RDI,8)

    (1165) 0x46ef40 MOV	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef44 MOV	(%R13),%RDX

    (1165) 0x46ef48 CMP	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef4c JE	46eec0

    (1165) 0x46ef52 INC	%RAX

    (1165) 0x46ef55 MOV	-0x60(%RBP),%R9

    (1165) 0x46ef59 INCQ	0x8(%R9,%RDI,8)

    (1165) 0x46ef5e MOV	%RDI,(%RBX,%RDX,8)

    (1165) 0x46ef62 JMP	46eec0

  (1161) 0x46ef67 MOV	-0x58(%RBP),%R14

  (1161) 0x46ef6b MOV	-0x38(%RBP),%R13

  (1161) 0x46ef6f MOV	-0x68(%RBP),%RDX

  (1161) 0x46ef73 MOV	0x8(%RDX,%R13,8),%R10

  (1161) 0x46ef78 TEST	%R10,%R10

  (1161) 0x46ef7b JLE	46ede0

  (1161) 0x46ef81 MOV	-0x40(%RBP),%RDX

  (1161) 0x46ef85 MOV	(%RDX,%R13,8),%R9

  (1161) 0x46ef89 ADD	%R9,%R10

  (1161) 0x46ef8c LEA	0x1(%R9),%RDX

  (1161) 0x46ef90 CMP	%RDX,%R10

  (1161) 0x46ef93 CMOVLE	%RDX,%R10

  (1161) 0x46ef97 MOV	-0x50(%RBP),%RDX

  (1161) 0x46ef9b MOV	-0x8(%RDX,%R12,8),%RSI

  (1161) 0x46efa0 MOV	%R10,%R11

  (1161) 0x46efa3 SUB	%R9,%R11

  (1161) 0x46efa6 CMP	$0x4,%R11

  (1161) 0x46efaa MOV	%R11,-0x38(%RBP)

  (1161) 0x46efae JAE	46eff8

  (1161) 0x46efb0 MOV	-0x38(%RBP),%RDX

  (1161) 0x46efb4 MOV	%RDX,%R11

  (1161) 0x46efb7 AND	$-0x4,%R11

  (1161) 0x46efbb CMP	%RDX,%R11

  (1161) 0x46efbe JAE	46edd9

  (1161) 0x46efc4 ADD	%R11,%R9

  (1161) 0x46efc7 MOV	-0x58(%RBP),%R14

  (1161) 0x46efcb JMP	46efdc

    (1162) 0x46efd0 INC	%R9

    (1162) 0x46efd3 CMP	%R9,%R10

    (1162) 0x46efd6 JE	46ede0

    (1162) 0x46efdc MOV	(%RSI,%R9,8),%RDX

    (1162) 0x46efe0 CMP	%RDI,(%R15,%RDX,8)

    (1162) 0x46efe4 JE	46efd0

    (1162) 0x46efe6 INC	%RCX

    (1162) 0x46efe9 MOV	-0x68(%RBP),%R11

    (1162) 0x46efed INCQ	0x8(%R11,%RDI,8)

    (1162) 0x46eff2 MOV	%RDI,(%R15,%RDX,8)

    (1162) 0x46eff6 JMP	46efd0

  (1161) 0x46eff8 SHR	$0x2,%R11

  (1161) 0x46effc LEA	(%RSI,%R9,8),%R14

  (1161) 0x46f000 ADD	$0x18,%R14

  (1161) 0x46f004 JMP	46f019

    (1163) 0x46f010 ADD	$0x20,%R14

    (1163) 0x46f014 DEC	%R11

    (1163) 0x46f017 JE	46efb0

    (1163) 0x46f019 MOV	-0x18(%R14),%R13

    (1163) 0x46f01d CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f021 JNE	46f050

    (1163) 0x46f023 MOV	-0x10(%R14),%R13

    (1163) 0x46f027 CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f02b JNE	46f06a

    (1163) 0x46f02d MOV	-0x8(%R14),%R13

    (1163) 0x46f031 CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f035 JNE	46f084

    (1163) 0x46f037 MOV	(%R14),%R13

    (1163) 0x46f03a CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f03e JE	46f010

    (1163) 0x46f040 JMP	46f0a1

    (1163) 0x46f050 INC	%RCX

    (1163) 0x46f053 MOV	-0x68(%RBP),%RDX

    (1163) 0x46f057 INCQ	0x8(%RDX,%RDI,8)

    (1163) 0x46f05c MOV	%RDI,(%R15,%R13,8)

    (1163) 0x46f060 MOV	-0x10(%R14),%R13

    (1163) 0x46f064 CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f068 JE	46f02d

    (1163) 0x46f06a INC	%RCX

    (1163) 0x46f06d MOV	-0x68(%RBP),%RDX

    (1163) 0x46f071 INCQ	0x8(%RDX,%RDI,8)

    (1163) 0x46f076 MOV	%RDI,(%R15,%R13,8)

    (1163) 0x46f07a MOV	-0x8(%R14),%R13

    (1163) 0x46f07e CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f082 JE	46f037

    (1163) 0x46f084 INC	%RCX

    (1163) 0x46f087 MOV	-0x68(%RBP),%RDX

    (1163) 0x46f08b INCQ	0x8(%RDX,%RDI,8)

    (1163) 0x46f090 MOV	%RDI,(%R15,%R13,8)

    (1163) 0x46f094 MOV	(%R14),%R13

    (1163) 0x46f097 CMP	%RDI,(%R15,%R13,8)

    (1163) 0x46f09b JE	46f010

    (1163) 0x46f0a1 INC	%RCX

    (1163) 0x46f0a4 MOV	-0x68(%RBP),%RDX

    (1163) 0x46f0a8 INCQ	0x8(%RDX,%RDI,8)

    (1163) 0x46f0ad MOV	%RDI,(%R15,%R13,8)

    (1163) 0x46f0b1 JMP	46f010

0x46f0c0 MOV	-0xa0(%RBP),%RDX

0x46f0c7 MOV	(%RDX,%RDI,8),%R8

0x46f0cb MOV	0x8(%RDX,%RDI,8),%RSI

0x46f0d0 CMP	%RSI,%R8

0x46f0d3 JL	46f0ec

0x46f0d5 JMP	46ed90

  (1159) 0x46f0e0 INC	%R8

  (1159) 0x46f0e3 CMP	%RSI,%R8

  (1159) 0x46f0e6 JGE	46ed90

  (1159) 0x46f0ec MOV	-0x120(%RBP),%RDX

  (1159) 0x46f0f3 MOV	(%RDX,%R8,8),%R9

  (1159) 0x46f0f7 MOV	-0x110(%RBP),%RDX

  (1159) 0x46f0fe CMP	%R14,(%RDX,%R9,8)

  (1159) 0x46f102 JNE	46f0e0

  (1159) 0x46f104 MOV	-0x100(%RBP),%RDX

  (1159) 0x46f10b MOV	0x8(%RDX,%R9,8),%RDX

  (1159) 0x46f110 TEST	%RDX,%RDX

  (1159) 0x46f113 JLE	46f0e0

  (1159) 0x46f115 MOV	-0xf0(%RBP),%RSI

  (1159) 0x46f11c MOV	(%RSI,%R9,8),%RSI

  (1159) 0x46f120 ADD	%RSI,%RDX

  (1159) 0x46f123 MOV	-0xf8(%RBP),%R9

  (1159) 0x46f12a MOV	(%R9,%R12,8),%R9

  (1159) 0x46f12e LEA	0x1(%RSI),%R10

  (1159) 0x46f132 CMP	%R10,%RDX

  (1159) 0x46f135 CMOVLE	%R10,%RDX

  (1159) 0x46f139 JMP	46f150

    (1160) 0x46f140 INCQ	0x8(%R11,%RDI,8)

    (1160) 0x46f145 MOV	%RDI,(%R10)

    (1160) 0x46f148 INC	%RSI

    (1160) 0x46f14b CMP	%RSI,%RDX

    (1160) 0x46f14e JE	46f190

    (1160) 0x46f150 MOV	(%R9,%RSI,8),%R10

    (1160) 0x46f154 TEST	%R10,%R10

    (1160) 0x46f157 JS	46f170

    (1160) 0x46f159 CMP	%RDI,(%R15,%R10,8)

    (1160) 0x46f15d JE	46f148

    (1160) 0x46f15f LEA	(%R15,%R10,8),%R10

    (1160) 0x46f163 INC	%RCX

    (1160) 0x46f166 MOV	-0x68(%RBP),%R11

    (1160) 0x46f16a JMP	46f140

    (1160) 0x46f170 NOT	%R10

    (1160) 0x46f173 CMP	%RDI,(%RBX,%R10,8)

    (1160) 0x46f177 JE	46f148

    (1160) 0x46f179 LEA	(%RBX,%R10,8),%R10

    (1160) 0x46f17d INC	%RAX

    (1160) 0x46f180 MOV	-0x60(%RBP),%R11

    (1160) 0x46f184 JMP	46f140

  (1159) 0x46f190 MOV	-0xa0(%RBP),%RDX

  (1159) 0x46f197 MOV	0x8(%RDX,%RDI,8),%RSI

  (1159) 0x46f19c INC	%R8

  (1159) 0x46f19f CMP	%RSI,%R8

  (1159) 0x46f1a2 JL	46f0ec

0x46f1a8 JMP	46ed90

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 997

--------------------------------------------------------------------------------

917:           for (i=0; i < n_coarse; i++)

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

Coverage (%)	Name	Source Location	Module
►96.66+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.70+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.44
Front-end cycles	2.63
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	11.00
Nb stores	3.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	0.44
Front-end cycles	2.63
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	11.00
Nb stores	3.00
Nb stack references	7.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-997
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,939-970,976-997.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,947,970,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2712 paths individually, rerun with max-paths=2712
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2712 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.44 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.63 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	21
nb uops	21
loop length	104
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.67	1.67	1.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.67	1.67	1.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Dispatch	3.50
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

9% of peak load performance is reached (25.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46eda7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x150(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0xd0(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 46f1b1 <hypre_BoomerAMGBuildMultipass.extracted.34+0x691>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x150(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x98(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,(%RDX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,(%RDX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 46edea <hypre_BoomerAMGBuildMultipass.extracted.34+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%RDI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 46f0ec <hypre_BoomerAMGBuildMultipass.extracted.34+0x5cc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 46ed90 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 46ed90 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-997
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,939-970,976-997.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,947,970,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2712 paths individually, rerun with max-paths=2712
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2712 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 0.44 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.63 cycles (1.33x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	21
nb uops	21
loop length	104
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.67	1.67	1.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.67	1.67	1.67	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Dispatch	3.50
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

9% of peak load performance is reached (25.14 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46eda7

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x150(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0xd0(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 46f1b1 <hypre_BoomerAMGBuildMultipass.extracted.34+0x691>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x150(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x98(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,(%RDX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,(%RDX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xa8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 46edea <hypre_BoomerAMGBuildMultipass.extracted.34+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%RDI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RSI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 46f0ec <hypre_BoomerAMGBuildMultipass.extracted.34+0x5cc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 46ed90 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 46ed90 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code