OV - exec - Loop 1147

0x46f490 MOV	-0x70(%RBP),%RSI

0x46f494 INC	%RSI

0x46f497 CMP	-0xd0(%RBP),%RSI

0x46f49e JGE	46f8c1

0x46f4a4 MOV	-0x90(%RBP),%RDX

0x46f4ab MOV	%RSI,-0x70(%RBP)

0x46f4af MOV	(%RDX,%RSI,8),%RSI

0x46f4b3 MOV	-0xa8(%RBP),%RDX

0x46f4ba MOV	(%RDX,%RSI,8),%R8

0x46f4be MOV	%RSI,%RDI

0x46f4c1 NOT	%RDI

0x46f4c4 MOV	%RSI,-0x58(%RBP)

0x46f4c8 JMP	46f4de

  (1150) 0x46f4ca MOV	-0x38(%RBP),%R14

  (1150) 0x46f4ce XCHG	%AX,%AX

  (1150) 0x46f4d0 INC	%R8

  (1150) 0x46f4d3 MOV	-0xa8(%RBP),%RDX

  (1150) 0x46f4da MOV	-0x58(%RBP),%RSI

  (1150) 0x46f4de CMP	0x8(%RDX,%RSI,8),%R8

  (1150) 0x46f4e3 JGE	46f7d0

  (1150) 0x46f4e9 MOV	-0x118(%RBP),%RDX

  (1150) 0x46f4f0 MOV	(%RDX,%R8,8),%R13

  (1150) 0x46f4f4 MOV	-0x108(%RBP),%RDX

  (1150) 0x46f4fb CMP	%R14,(%RDX,%R13,8)

  (1150) 0x46f4ff JNE	46f4d0

  (1150) 0x46f501 MOV	-0x60(%RBP),%RDX

  (1150) 0x46f505 MOV	0x8(%RDX,%R13,8),%R10

  (1150) 0x46f50a TEST	%R10,%R10

  (1150) 0x46f50d JLE	46f66b

  (1150) 0x46f513 MOV	-0x98(%RBP),%RDX

  (1150) 0x46f51a MOV	%R13,-0x78(%RBP)

  (1150) 0x46f51e MOV	(%RDX,%R13,8),%R11

  (1150) 0x46f522 ADD	%R11,%R10

  (1150) 0x46f525 LEA	0x1(%R11),%RDX

  (1150) 0x46f529 CMP	%RDX,%R10

  (1150) 0x46f52c CMOVLE	%RDX,%R10

  (1150) 0x46f530 MOV	-0x48(%RBP),%RDX

  (1150) 0x46f534 MOV	-0x8(%RDX,%R12,8),%RSI

  (1150) 0x46f539 MOV	%R10,%RDX

  (1150) 0x46f53c SUB	%R11,%RDX

  (1150) 0x46f53f CMP	$0x4,%RDX

  (1150) 0x46f543 MOV	%RDX,-0x30(%RBP)

  (1150) 0x46f547 JAE	46f59b

  (1150) 0x46f549 MOV	-0x30(%RBP),%R9

  (1150) 0x46f54d MOV	%R9,%RDX

  (1150) 0x46f550 AND	$-0x4,%RDX

  (1150) 0x46f554 CMP	%R9,%RDX

  (1150) 0x46f557 JAE	46f663

  (1150) 0x46f55d ADD	%RDX,%R11

  (1150) 0x46f560 MOV	-0x38(%RBP),%R14

  (1150) 0x46f564 MOV	-0x78(%RBP),%R13

  (1150) 0x46f568 JMP	46f57c

    (1153) 0x46f570 INC	%R11

    (1153) 0x46f573 CMP	%R11,%R10

    (1153) 0x46f576 JE	46f66b

    (1153) 0x46f57c MOV	(%RSI,%R11,8),%RDX

    (1153) 0x46f580 CMP	%RDI,(%RBX,%RDX,8)

    (1153) 0x46f584 JE	46f570

    (1153) 0x46f586 MOV	-0x48(%RBP),%R9

    (1153) 0x46f58a MOV	(%R9,%R12,8),%R9

    (1153) 0x46f58e MOV	%RDX,(%R9,%RAX,8)

    (1153) 0x46f592 INC	%RAX

    (1153) 0x46f595 MOV	%RDI,(%RBX,%RDX,8)

    (1153) 0x46f599 JMP	46f570

  (1150) 0x46f59b SHR	$0x2,%RDX

  (1150) 0x46f59f LEA	(%RSI,%R11,8),%R13

  (1150) 0x46f5a3 ADD	$0x18,%R13

  (1150) 0x46f5a7 JMP	46f5b9

    (1154) 0x46f5b0 ADD	$0x20,%R13

    (1154) 0x46f5b4 DEC	%RDX

    (1154) 0x46f5b7 JE	46f549

    (1154) 0x46f5b9 MOV	-0x18(%R13),%R14

    (1154) 0x46f5bd CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f5c1 JNE	46f5f0

    (1154) 0x46f5c3 MOV	-0x10(%R13),%R14

    (1154) 0x46f5c7 CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f5cb JNE	46f60d

    (1154) 0x46f5cd MOV	-0x8(%R13),%R14

    (1154) 0x46f5d1 CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f5d5 JNE	46f62a

    (1154) 0x46f5d7 MOV	(%R13),%R14

    (1154) 0x46f5db CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f5df JE	46f5b0

    (1154) 0x46f5e1 JMP	46f64b

    (1154) 0x46f5f0 MOV	-0x48(%RBP),%R9

    (1154) 0x46f5f4 MOV	(%R9,%R12,8),%R9

    (1154) 0x46f5f8 MOV	%R14,(%R9,%RAX,8)

    (1154) 0x46f5fc INC	%RAX

    (1154) 0x46f5ff MOV	%RDI,(%RBX,%R14,8)

    (1154) 0x46f603 MOV	-0x10(%R13),%R14

    (1154) 0x46f607 CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f60b JE	46f5cd

    (1154) 0x46f60d MOV	-0x48(%RBP),%R9

    (1154) 0x46f611 MOV	(%R9,%R12,8),%R9

    (1154) 0x46f615 MOV	%R14,(%R9,%RAX,8)

    (1154) 0x46f619 INC	%RAX

    (1154) 0x46f61c MOV	%RDI,(%RBX,%R14,8)

    (1154) 0x46f620 MOV	-0x8(%R13),%R14

    (1154) 0x46f624 CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f628 JE	46f5d7

    (1154) 0x46f62a MOV	-0x48(%RBP),%R9

    (1154) 0x46f62e MOV	(%R9,%R12,8),%R9

    (1154) 0x46f632 MOV	%R14,(%R9,%RAX,8)

    (1154) 0x46f636 INC	%RAX

    (1154) 0x46f639 MOV	%RDI,(%RBX,%R14,8)

    (1154) 0x46f63d MOV	(%R13),%R14

    (1154) 0x46f641 CMP	%RDI,(%RBX,%R14,8)

    (1154) 0x46f645 JE	46f5b0

    (1154) 0x46f64b MOV	-0x48(%RBP),%R9

    (1154) 0x46f64f MOV	(%R9,%R12,8),%R9

    (1154) 0x46f653 MOV	%R14,(%R9,%RAX,8)

    (1154) 0x46f657 INC	%RAX

    (1154) 0x46f65a MOV	%RDI,(%RBX,%R14,8)

    (1154) 0x46f65e JMP	46f5b0

  (1150) 0x46f663 MOV	-0x38(%RBP),%R14

  (1150) 0x46f667 MOV	-0x78(%RBP),%R13

  (1150) 0x46f66b MOV	-0x68(%RBP),%RDX

  (1150) 0x46f66f MOV	0x8(%RDX,%R13,8),%R10

  (1150) 0x46f674 TEST	%R10,%R10

  (1150) 0x46f677 JLE	46f4d0

  (1150) 0x46f67d MOV	-0x40(%RBP),%RDX

  (1150) 0x46f681 MOV	(%RDX,%R13,8),%R9

  (1150) 0x46f685 ADD	%R9,%R10

  (1150) 0x46f688 LEA	0x1(%R9),%RDX

  (1150) 0x46f68c CMP	%RDX,%R10

  (1150) 0x46f68f CMOVLE	%RDX,%R10

  (1150) 0x46f693 MOV	-0x50(%RBP),%RDX

  (1150) 0x46f697 MOV	-0x8(%RDX,%R12,8),%RSI

  (1150) 0x46f69c MOV	%R10,%R11

  (1150) 0x46f69f SUB	%R9,%R11

  (1150) 0x46f6a2 CMP	$0x4,%R11

  (1150) 0x46f6a6 MOV	%R11,-0x78(%RBP)

  (1150) 0x46f6aa JAE	46f6fb

  (1150) 0x46f6ac MOV	-0x78(%RBP),%RDX

  (1150) 0x46f6b0 MOV	%RDX,%R11

  (1150) 0x46f6b3 AND	$-0x4,%R11

  (1150) 0x46f6b7 CMP	%RDX,%R11

  (1150) 0x46f6ba JAE	46f4ca

  (1150) 0x46f6c0 ADD	%R11,%R9

  (1150) 0x46f6c3 MOV	-0x38(%RBP),%R14

  (1150) 0x46f6c7 JMP	46f6dc

    (1151) 0x46f6d0 INC	%R9

    (1151) 0x46f6d3 CMP	%R9,%R10

    (1151) 0x46f6d6 JE	46f4d0

    (1151) 0x46f6dc MOV	(%RSI,%R9,8),%RDX

    (1151) 0x46f6e0 CMP	%RDI,(%R15,%RDX,8)

    (1151) 0x46f6e4 JE	46f6d0

    (1151) 0x46f6e6 MOV	-0x50(%RBP),%R11

    (1151) 0x46f6ea MOV	(%R11,%R12,8),%R11

    (1151) 0x46f6ee MOV	%RDX,(%R11,%RCX,8)

    (1151) 0x46f6f2 INC	%RCX

    (1151) 0x46f6f5 MOV	%RDI,(%R15,%RDX,8)

    (1151) 0x46f6f9 JMP	46f6d0

  (1150) 0x46f6fb SHR	$0x2,%R11

  (1150) 0x46f6ff LEA	(%RSI,%R9,8),%R14

  (1150) 0x46f703 ADD	$0x18,%R14

  (1150) 0x46f707 JMP	46f719

    (1152) 0x46f710 ADD	$0x20,%R14

    (1152) 0x46f714 DEC	%R11

    (1152) 0x46f717 JE	46f6ac

    (1152) 0x46f719 MOV	-0x18(%R14),%R13

    (1152) 0x46f71d CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f721 JNE	46f750

    (1152) 0x46f723 MOV	-0x10(%R14),%R13

    (1152) 0x46f727 CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f72b JNE	46f76d

    (1152) 0x46f72d MOV	-0x8(%R14),%R13

    (1152) 0x46f731 CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f735 JNE	46f78a

    (1152) 0x46f737 MOV	(%R14),%R13

    (1152) 0x46f73a CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f73e JE	46f710

    (1152) 0x46f740 JMP	46f7aa

    (1152) 0x46f750 MOV	-0x50(%RBP),%RDX

    (1152) 0x46f754 MOV	(%RDX,%R12,8),%RDX

    (1152) 0x46f758 MOV	%R13,(%RDX,%RCX,8)

    (1152) 0x46f75c INC	%RCX

    (1152) 0x46f75f MOV	%RDI,(%R15,%R13,8)

    (1152) 0x46f763 MOV	-0x10(%R14),%R13

    (1152) 0x46f767 CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f76b JE	46f72d

    (1152) 0x46f76d MOV	-0x50(%RBP),%RDX

    (1152) 0x46f771 MOV	(%RDX,%R12,8),%RDX

    (1152) 0x46f775 MOV	%R13,(%RDX,%RCX,8)

    (1152) 0x46f779 INC	%RCX

    (1152) 0x46f77c MOV	%RDI,(%R15,%R13,8)

    (1152) 0x46f780 MOV	-0x8(%R14),%R13

    (1152) 0x46f784 CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f788 JE	46f737

    (1152) 0x46f78a MOV	-0x50(%RBP),%RDX

    (1152) 0x46f78e MOV	(%RDX,%R12,8),%RDX

    (1152) 0x46f792 MOV	%R13,(%RDX,%RCX,8)

    (1152) 0x46f796 INC	%RCX

    (1152) 0x46f799 MOV	%RDI,(%R15,%R13,8)

    (1152) 0x46f79d MOV	(%R14),%R13

    (1152) 0x46f7a0 CMP	%RDI,(%R15,%R13,8)

    (1152) 0x46f7a4 JE	46f710

    (1152) 0x46f7aa MOV	-0x50(%RBP),%RDX

    (1152) 0x46f7ae MOV	(%RDX,%R12,8),%RDX

    (1152) 0x46f7b2 MOV	%R13,(%RDX,%RCX,8)

    (1152) 0x46f7b6 INC	%RCX

    (1152) 0x46f7b9 MOV	%RDI,(%R15,%R13,8)

    (1152) 0x46f7bd JMP	46f710

0x46f7d0 MOV	-0xa0(%RBP),%RDX

0x46f7d7 MOV	-0x58(%RBP),%R8

0x46f7db MOV	(%RDX,%R8,8),%RSI

0x46f7df MOV	0x8(%RDX,%R8,8),%R8

0x46f7e4 CMP	%R8,%RSI

0x46f7e7 JL	46f7fc

0x46f7e9 JMP	46f490

  (1148) 0x46f7f0 INC	%RSI

  (1148) 0x46f7f3 CMP	%R8,%RSI

  (1148) 0x46f7f6 JGE	46f490

  (1148) 0x46f7fc MOV	-0x120(%RBP),%RDX

  (1148) 0x46f803 MOV	(%RDX,%RSI,8),%R9

  (1148) 0x46f807 MOV	-0x110(%RBP),%RDX

  (1148) 0x46f80e CMP	%R14,(%RDX,%R9,8)

  (1148) 0x46f812 JNE	46f7f0

  (1148) 0x46f814 MOV	-0x100(%RBP),%RDX

  (1148) 0x46f81b MOV	0x8(%RDX,%R9,8),%RDX

  (1148) 0x46f820 TEST	%RDX,%RDX

  (1148) 0x46f823 JLE	46f7f0

  (1148) 0x46f825 MOV	-0xf0(%RBP),%R8

  (1148) 0x46f82c MOV	(%R8,%R9,8),%R8

  (1148) 0x46f830 ADD	%R8,%RDX

  (1148) 0x46f833 MOV	-0xf8(%RBP),%R9

  (1148) 0x46f83a MOV	(%R9,%R12,8),%R9

  (1148) 0x46f83e LEA	0x1(%R8),%R10

  (1148) 0x46f842 CMP	%R10,%RDX

  (1148) 0x46f845 CMOVLE	%R10,%RDX

  (1148) 0x46f849 JMP	46f858

    (1149) 0x46f850 INC	%R8

    (1149) 0x46f853 CMP	%R8,%RDX

    (1149) 0x46f856 JE	46f8a0

    (1149) 0x46f858 MOV	(%R9,%R8,8),%R10

    (1149) 0x46f85c TEST	%R10,%R10

    (1149) 0x46f85f JS	46f880

    (1149) 0x46f861 CMP	%RDI,(%R15,%R10,8)

    (1149) 0x46f865 JE	46f850

    (1149) 0x46f867 MOV	-0x50(%RBP),%R11

    (1149) 0x46f86b MOV	(%R11,%R12,8),%R11

    (1149) 0x46f86f MOV	%R10,(%R11,%RCX,8)

    (1149) 0x46f873 INC	%RCX

    (1149) 0x46f876 MOV	%RDI,(%R15,%R10,8)

    (1149) 0x46f87a JMP	46f850

    (1149) 0x46f880 NOT	%R10

    (1149) 0x46f883 CMP	%RDI,(%RBX,%R10,8)

    (1149) 0x46f887 JE	46f850

    (1149) 0x46f889 MOV	-0x48(%RBP),%R11

    (1149) 0x46f88d MOV	(%R11,%R12,8),%R11

    (1149) 0x46f891 MOV	%R10,(%R11,%RAX,8)

    (1149) 0x46f895 INC	%RAX

    (1149) 0x46f898 MOV	%RDI,(%RBX,%R10,8)

    (1149) 0x46f89c JMP	46f850

  (1148) 0x46f8a0 MOV	-0xa0(%RBP),%RDX

  (1148) 0x46f8a7 MOV	-0x58(%RBP),%R8

  (1148) 0x46f8ab MOV	0x8(%RDX,%R8,8),%R8

  (1148) 0x46f8b0 INC	%RSI

  (1148) 0x46f8b3 CMP	%R8,%RSI

  (1148) 0x46f8b6 JL	46f7fc

0x46f8bc JMP	46f490

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 1125

--------------------------------------------------------------------------------

917:           for (i=0; i < n_coarse; i++)

[...]

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►97.73+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.27+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.38
Front-end cycles	2.63
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.38
Front-end cycles	2.63
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	3.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	10.00
Nb stores	2.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1078,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2712 paths individually, rerun with max-paths=2712
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2712 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.37 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.63 cycles (1.14x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.67	1.67	1.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.67	1.67	1.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

10% of peak load performance is reached (26.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46f4a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0xd0(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 46f8c1 <hypre_BoomerAMGBuildMultipass.extracted.34+0xda1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 46f4de <hypre_BoomerAMGBuildMultipass.extracted.34+0x9be>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 46f7fc <hypre_BoomerAMGBuildMultipass.extracted.34+0xcdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 46f490 <hypre_BoomerAMGBuildMultipass.extracted.34+0x970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 46f490 <hypre_BoomerAMGBuildMultipass.extracted.34+0x970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.34
Source file and lines	par_multi_interp.c:917-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:917,1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1078,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 2712 paths individually, rerun with max-paths=2712
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 2712 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.37 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.63 cycles (1.14x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	21
nb uops	21
loop length	93
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.63 cycles
front end	2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.67	1.67	1.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.67	1.67	1.67	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Dispatch	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

10% of peak load performance is reached (26.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46f4a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP -0xd0(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 46f8c1 <hypre_BoomerAMGBuildMultipass.extracted.34+0xda1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 46f4de <hypre_BoomerAMGBuildMultipass.extracted.34+0x9be>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JL 46f7fc <hypre_BoomerAMGBuildMultipass.extracted.34+0xcdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 46f490 <hypre_BoomerAMGBuildMultipass.extracted.34+0x970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 46f490 <hypre_BoomerAMGBuildMultipass.extracted.34+0x970>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code