OV - exec - Loop 1132

	Loop Id: 1132	Module: exec	Source: par_multi_interp.c:1747-1837 [...]	Coverage: 0.47%

0x46e23f ADDSD	(%RBX,%RDX,8),%XMM0

0x46e244 NOPW	%CS:(%RAX,%RAX,1)

0x46e250 INC	%RDX

0x46e253 CMP	%RCX,%RDX

0x46e256 JE	46e590

0x46e25c MOV	-0x170(%RBP),%RSI

0x46e263 MOV	(%RSI,%RDX,8),%RSI

0x46e267 MOV	-0x78(%RBP),%RDI

0x46e26b CMP	%R9,(%RDI,%RSI,8)

0x46e26f JNE	46e2a0

0x46e271 MOV	-0xa8(%RBP),%R8

0x46e278 MOV	(%R8,%RSI,8),%RDI

0x46e27c MOV	0x8(%R8,%RSI,8),%R8

0x46e281 MOV	%R8,%R9

0x46e284 SUB	%RDI,%R9

0x46e287 JLE	46e410

0x46e28d CMP	$0x4,%R9

0x46e291 JAE	46e2ce

0x46e293 JMP	46e3a3

0x46e2a0 MOV	-0x158(%RBP),%RDI

0x46e2a7 CMPQ	$-0x3,(%RDI,%RSI,8)

0x46e2ac JE	46e250

0x46e2ae CMPQ	$0x1,-0xe8(%RBP)

0x46e2b6 JE	46e23f

0x46e2b8 MOV	-0xc8(%RBP),%R8

0x46e2bf MOV	(%R8,%R9,8),%RDI

0x46e2c3 CMP	(%R8,%RSI,8),%RDI

0x46e2c7 JNE	46e250

0x46e2c9 JMP	46e23f

0x46e2ce MOV	%R9,%R10

0x46e2d1 SHR	$0x2,%R10

0x46e2d5 LEA	0x18(,%RDI,8),%R11

0x46e2dd MOV	-0x48(%RBP),%R12

0x46e2e1 NOPW	%CS:(%RAX,%RAX,1)

  (1135) 0x46e2f0 MOVSD	-0x18(%R14,%R11,1),%XMM2

  (1135) 0x46e2f7 MULSD	(%RBX,%RDX,8),%XMM2

  (1135) 0x46e2fc MOV	-0x18(%RAX,%R11,1),%R15

  (1135) 0x46e301 MOV	(%R12,%R15,8),%R15

  (1135) 0x46e305 MOVSD	(%R14,%R15,8),%XMM3

  (1135) 0x46e30b ADDSD	%XMM2,%XMM3

  (1135) 0x46e30f MOVSD	%XMM3,(%R14,%R15,8)

  (1135) 0x46e315 MOVSD	-0x10(%R14,%R11,1),%XMM3

  (1135) 0x46e31c MULSD	(%RBX,%RDX,8),%XMM3

  (1135) 0x46e321 MOV	-0x10(%RAX,%R11,1),%R15

  (1135) 0x46e326 MOV	(%R12,%R15,8),%R15

  (1135) 0x46e32a MOVSD	(%R14,%R15,8),%XMM4

  (1135) 0x46e330 ADDSD	%XMM3,%XMM4

  (1135) 0x46e334 MOVSD	%XMM4,(%R14,%R15,8)

  (1135) 0x46e33a MOVSD	-0x8(%R14,%R11,1),%XMM4

  (1135) 0x46e341 MULSD	(%RBX,%RDX,8),%XMM4

  (1135) 0x46e346 MOV	-0x8(%RAX,%R11,1),%R15

  (1135) 0x46e34b MOV	(%R12,%R15,8),%R15

  (1135) 0x46e34f MOVSD	(%R14,%R15,8),%XMM5

  (1135) 0x46e355 ADDSD	%XMM4,%XMM5

  (1135) 0x46e359 MOVSD	%XMM5,(%R14,%R15,8)

  (1135) 0x46e35f MOVSD	(%R14,%R11,1),%XMM7

  (1135) 0x46e365 MULSD	(%RBX,%RDX,8),%XMM7

  (1135) 0x46e36a MOV	(%RAX,%R11,1),%R15

  (1135) 0x46e36e MOV	(%R12,%R15,8),%R15

  (1135) 0x46e372 MOVSD	(%R14,%R15,8),%XMM5

  (1135) 0x46e378 ADDSD	%XMM7,%XMM5

  (1135) 0x46e37c MOVSD	%XMM5,(%R14,%R15,8)

  (1135) 0x46e382 ADDSD	%XMM7,%XMM4

  (1135) 0x46e386 ADDSD	%XMM2,%XMM3

  (1135) 0x46e38a ADDSD	%XMM4,%XMM3

  (1135) 0x46e38e ADDSD	%XMM3,%XMM1

  (1135) 0x46e392 ADDSD	%XMM3,%XMM0

  (1135) 0x46e396 ADD	$0x20,%R11

  (1135) 0x46e39a DEC	%R10

  (1135) 0x46e39d JNE	46e2f0

0x46e3a3 MOV	%R9,%R10

0x46e3a6 AND	$-0x4,%R10

0x46e3aa CMP	%R9,%R10

0x46e3ad JAE	46e405

0x46e3af ADD	%R10,%RDI

0x46e3b2 MOV	-0xa0(%RBP),%R15

0x46e3b9 MOV	-0x30(%RBP),%R10

0x46e3bd MOV	-0x48(%RBP),%R12

0x46e3c1 NOPW	%CS:(%RAX,%RAX,1)

  (1136) 0x46e3d0 MOV	(%RAX,%RDI,8),%R9

  (1136) 0x46e3d4 MOVSD	(%R14,%RDI,8),%XMM7

  (1136) 0x46e3da MULSD	(%RBX,%RDX,8),%XMM7

  (1136) 0x46e3df MOV	(%R12,%R9,8),%R9

  (1136) 0x46e3e3 MOVSD	(%R14,%R9,8),%XMM2

  (1136) 0x46e3e9 ADDSD	%XMM7,%XMM2

  (1136) 0x46e3ed MOVSD	%XMM2,(%R14,%R9,8)

  (1136) 0x46e3f3 ADDSD	%XMM7,%XMM1

  (1136) 0x46e3f7 ADDSD	%XMM7,%XMM0

  (1136) 0x46e3fb INC	%RDI

  (1136) 0x46e3fe CMP	%RDI,%R8

  (1136) 0x46e401 JNE	46e3d0

0x46e403 JMP	46e410

0x46e405 MOV	-0xa0(%RBP),%R15

0x46e40c MOV	-0x30(%RBP),%R10

0x46e410 MOV	-0xb0(%RBP),%RAX

0x46e417 MOV	(%RAX,%RSI,8),%RDI

0x46e41b MOV	0x8(%RAX,%RSI,8),%RSI

0x46e420 MOV	%RSI,%R8

0x46e423 SUB	%RDI,%R8

0x46e426 JLE	46e440

0x46e428 CMP	$0x4,%R8

0x46e42c MOV	-0x58(%RBP),%R12

0x46e430 JAE	46e44d

0x46e432 JMP	46e51c

0x46e440 MOV	-0x50(%RBP),%RAX

0x46e444 MOV	-0x58(%RBP),%R12

0x46e448 JMP	46e583

0x46e44d MOV	%R8,%R9

0x46e450 SHR	$0x2,%R9

0x46e454 MOV	%R10,%RAX

0x46e457 LEA	0x18(,%RDI,8),%R10

0x46e45f NOP

  (1133) 0x46e460 MOVSD	-0x18(%R13,%R10,1),%XMM2

  (1133) 0x46e467 MULSD	(%RBX,%RDX,8),%XMM2

  (1133) 0x46e46c MOV	-0x18(%RAX,%R10,1),%R11

  (1133) 0x46e471 MOV	(%R12,%R11,8),%R11

  (1133) 0x46e475 MOVSD	(%R13,%R11,8),%XMM3

  (1133) 0x46e47c ADDSD	%XMM2,%XMM3

  (1133) 0x46e480 MOVSD	%XMM3,(%R13,%R11,8)

  (1133) 0x46e487 MOVSD	-0x10(%R13,%R10,1),%XMM3

  (1133) 0x46e48e MULSD	(%RBX,%RDX,8),%XMM3

  (1133) 0x46e493 MOV	-0x10(%RAX,%R10,1),%R11

  (1133) 0x46e498 MOV	(%R12,%R11,8),%R11

  (1133) 0x46e49c MOVSD	(%R13,%R11,8),%XMM4

  (1133) 0x46e4a3 ADDSD	%XMM3,%XMM4

  (1133) 0x46e4a7 MOVSD	%XMM4,(%R13,%R11,8)

  (1133) 0x46e4ae MOVSD	-0x8(%R13,%R10,1),%XMM4

  (1133) 0x46e4b5 MULSD	(%RBX,%RDX,8),%XMM4

  (1133) 0x46e4ba MOV	-0x8(%RAX,%R10,1),%R11

  (1133) 0x46e4bf MOV	(%R12,%R11,8),%R11

  (1133) 0x46e4c3 MOVSD	(%R13,%R11,8),%XMM5

  (1133) 0x46e4ca ADDSD	%XMM4,%XMM5

  (1133) 0x46e4ce MOVSD	%XMM5,(%R13,%R11,8)

  (1133) 0x46e4d5 MOVSD	(%R13,%R10,1),%XMM7

  (1133) 0x46e4dc MULSD	(%RBX,%RDX,8),%XMM7

  (1133) 0x46e4e1 MOV	(%RAX,%R10,1),%R11

  (1133) 0x46e4e5 MOV	(%R12,%R11,8),%R11

  (1133) 0x46e4e9 MOVSD	(%R13,%R11,8),%XMM5

  (1133) 0x46e4f0 ADDSD	%XMM7,%XMM5

  (1133) 0x46e4f4 MOVSD	%XMM5,(%R13,%R11,8)

  (1133) 0x46e4fb ADDSD	%XMM7,%XMM4

  (1133) 0x46e4ff ADDSD	%XMM2,%XMM3

  (1133) 0x46e503 ADDSD	%XMM4,%XMM3

  (1133) 0x46e507 ADDSD	%XMM3,%XMM1

  (1133) 0x46e50b ADDSD	%XMM3,%XMM0

  (1133) 0x46e50f ADD	$0x20,%R10

  (1133) 0x46e513 DEC	%R9

  (1133) 0x46e516 JNE	46e460

0x46e51c MOV	%R8,%R9

0x46e51f AND	$-0x4,%R9

0x46e523 CMP	%R8,%R9

0x46e526 JAE	46e57b

0x46e528 ADD	%R9,%RDI

0x46e52b MOV	-0x30(%RBP),%R10

0x46e52f MOV	-0x50(%RBP),%RAX

0x46e533 MOV	-0x38(%RBP),%R9

0x46e537 NOPW	(%RAX,%RAX,1)

  (1134) 0x46e540 MOV	(%R10,%RDI,8),%R8

  (1134) 0x46e544 MOVSD	(%R13,%RDI,8),%XMM7

  (1134) 0x46e54b MULSD	(%RBX,%RDX,8),%XMM7

  (1134) 0x46e550 MOV	(%R12,%R8,8),%R8

  (1134) 0x46e554 MOVSD	(%R13,%R8,8),%XMM2

  (1134) 0x46e55b ADDSD	%XMM7,%XMM2

  (1134) 0x46e55f MOVSD	%XMM2,(%R13,%R8,8)

  (1134) 0x46e566 ADDSD	%XMM7,%XMM1

  (1134) 0x46e56a ADDSD	%XMM7,%XMM0

  (1134) 0x46e56e INC	%RDI

  (1134) 0x46e571 CMP	%RDI,%RSI

  (1134) 0x46e574 JNE	46e540

0x46e576 JMP	46e250

0x46e57b MOV	-0x30(%RBP),%R10

0x46e57f MOV	-0x50(%RBP),%RAX

0x46e583 MOV	-0x38(%RBP),%R9

0x46e587 JMP	46e250

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1747 - 1837

--------------------------------------------------------------------------------

1747:              if (n_fine)

[...]

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
►96.74+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.75+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1737	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1811-1816,par_multi_interp.c:1824-1824,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.13
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.28
CQA cycles if fully vectorized	1.14
Front-end cycles	9.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	73.00
Nb loads	32.00
Nb stores	0.00
Nb stack references	13.00
FLOP/cycle	0.11
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.05
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.28
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source	par_multi_interp.c:1747-1747,par_multi_interp.c:1811-1816,par_multi_interp.c:1824-1824,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.13
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.28
CQA cycles if fully vectorized	1.14
Front-end cycles	9.13
P0 cycles	6.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.67
P4 cycles	6.67
P5 cycles	6.67
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	73.00
Nb loads	32.00
Nb stores	0.00
Nb stack references	13.00
FLOP/cycle	0.11
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.05
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1837
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1811-1837.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1747,1811-1816,1824,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 29 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.13 to 4.00 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 9.13 to 1.14 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	78
nb uops	73
loop length	356
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.67	6.67	6.67	8.00	8.00	8.00	8.00	0.00	0.00	0.50	0.50	0.00	0.00
cycles	6.00	6.00	6.00	6.67	6.67	6.67	8.00	8.00	8.00	8.00	0.00	0.00	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	8.00
Overall L1	9.13

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.13 cycles. At this rate:

10% of peak load performance is reached (28.05 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.13 to 8.00 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 46e25c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ADDSD (%RBX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 46e590 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x170(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RSI,%RDX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R9,(%RDI,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 46e2a0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x940>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xa8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x8(%R8,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 46e410 <hypre_BoomerAMGBuildMultipass.extracted.28+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e2ce <hypre_BoomerAMGBuildMultipass.extracted.28+0x96e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e3a3 <hypre_BoomerAMGBuildMultipass.extracted.28+0xa43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x158(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $-0x3,(%RDI,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,-0xe8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 46e23f <hypre_BoomerAMGBuildMultipass.extracted.28+0x8df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%R9,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP (%R8,%RSI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e23f <hypre_BoomerAMGBuildMultipass.extracted.28+0x8df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x18(,%RDI,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e405 <hypre_BoomerAMGBuildMultipass.extracted.28+0xaa5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 46e410 <hypre_BoomerAMGBuildMultipass.extracted.28+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 46e440 <hypre_BoomerAMGBuildMultipass.extracted.28+0xae0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
JAE 46e44d <hypre_BoomerAMGBuildMultipass.extracted.28+0xaed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e51c <hypre_BoomerAMGBuildMultipass.extracted.28+0xbbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
JMP 46e583 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc23>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x2,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e57b <hypre_BoomerAMGBuildMultipass.extracted.28+0xc1b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
JMP 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.28
Source file and lines	par_multi_interp.c:1747-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.13 to 4.00 cycles (2.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 9.13 to 1.14 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	78
nb uops	73
loop length	356
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.13 cycles
front end	9.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.67	6.67	6.67	8.00	8.00	8.00	8.00	0.00	0.00	0.50	0.50	0.00	0.00
cycles	6.00	6.00	6.00	6.67	6.67	6.67	8.00	8.00	8.00	8.00	0.00	0.00	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.13
Dispatch	8.00
Overall L1	9.13

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.13 cycles. At this rate:

10% of peak load performance is reached (28.05 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46e25c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	Latency	Recip. throughput	Vectorization
ADDSD (%RBX,%RDX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %RCX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 46e590 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc30>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x170(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RSI,%RDX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R9,(%RDI,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 46e2a0 <hypre_BoomerAMGBuildMultipass.extracted.28+0x940>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xa8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x8(%R8,%RSI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 46e410 <hypre_BoomerAMGBuildMultipass.extracted.28+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e2ce <hypre_BoomerAMGBuildMultipass.extracted.28+0x96e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e3a3 <hypre_BoomerAMGBuildMultipass.extracted.28+0xa43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x158(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $-0x3,(%RDI,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,-0xe8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 46e23f <hypre_BoomerAMGBuildMultipass.extracted.28+0x8df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%R8,%R9,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP (%R8,%RSI,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JNE 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e23f <hypre_BoomerAMGBuildMultipass.extracted.28+0x8df>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x18(,%RDI,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e405 <hypre_BoomerAMGBuildMultipass.extracted.28+0xaa5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R10,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 46e410 <hypre_BoomerAMGBuildMultipass.extracted.28+0xab0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0xa0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
JLE 46e440 <hypre_BoomerAMGBuildMultipass.extracted.28+0xae0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
JAE 46e44d <hypre_BoomerAMGBuildMultipass.extracted.28+0xaed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46e51c <hypre_BoomerAMGBuildMultipass.extracted.28+0xbbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
JMP 46e583 <hypre_BoomerAMGBuildMultipass.extracted.28+0xc23>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x2,%R9	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33	N/A
MOV %R10,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(,%RDI,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46e57b <hypre_BoomerAMGBuildMultipass.extracted.28+0xc1b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
JMP 46e250 <hypre_BoomerAMGBuildMultipass.extracted.28+0x8f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code