OV - exec - Loop 1118

	Loop Id: 1118	Module: exec	Source: par_multi_interp.c:1585-1660 [...]	Coverage: 0.10%

0x46d2a2 INC	%RDX

0x46d2a5 CMP	-0x58(%RBP),%RDX

0x46d2a9 JGE	46d931

0x46d2af MOV	-0xc8(%RBP),%RAX

0x46d2b6 MOV	%RDX,-0x40(%RBP)

0x46d2ba MOV	(%RAX,%RDX,8),%RDI

0x46d2be MOV	-0xd0(%RBP),%RAX

0x46d2c5 MOV	(%RAX,%RDI,8),%R8

0x46d2c9 MOV	-0x70(%RBP),%RAX

0x46d2cd MOV	(%RAX,%RDI,8),%RCX

0x46d2d1 MOV	0x8(%RAX,%RDI,8),%RAX

0x46d2d6 LEA	(%RAX,%R8,1),%R9

0x46d2da SUB	%RCX,%R9

0x46d2dd CMP	%R9,%R8

0x46d2e0 JGE	46d3b5

0x46d2e6 MOV	-0xb8(%RBP),%RDX

0x46d2ed MOV	0x8(%RDX),%R9

0x46d2f1 SUB	%RCX,%RAX

0x46d2f4 CMP	$0x8,%RAX

0x46d2f8 JB	46d380

0x46d2fe MOV	%RAX,%R10

0x46d301 SHR	$0x3,%R10

0x46d305 LEA	(%R9,%R8,8),%R11

0x46d309 ADD	$0x38,%R11

0x46d30d NOPL	(%RAX)

  (1126) 0x46d310 MOV	-0x38(%R11),%RCX

  (1126) 0x46d314 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d318 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d31d MOV	-0x30(%R11),%RCX

  (1126) 0x46d321 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d325 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d32a MOV	-0x28(%R11),%RCX

  (1126) 0x46d32e MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d332 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d337 MOV	-0x20(%R11),%RCX

  (1126) 0x46d33b MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d33f MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d344 MOV	-0x18(%R11),%RCX

  (1126) 0x46d348 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d34c MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d351 MOV	-0x10(%R11),%RCX

  (1126) 0x46d355 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d359 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d35e MOV	-0x8(%R11),%RCX

  (1126) 0x46d362 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d366 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d36b MOV	(%R11),%RCX

  (1126) 0x46d36e MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d372 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d377 ADD	$0x40,%R11

  (1126) 0x46d37b DEC	%R10

  (1126) 0x46d37e JNE	46d310

0x46d380 MOV	%RAX,%RCX

0x46d383 AND	$-0x8,%RCX

0x46d387 CMP	%RAX,%RCX

0x46d38a MOV	-0x48(%RBP),%R11

0x46d38e MOV	-0x50(%RBP),%R10

0x46d392 JAE	46d3b5

0x46d394 LEA	(%R9,%R8,8),%R8

0x46d398 NOPL	(%RAX,%RAX,1)

  (1125) 0x46d3a0 MOV	(%R8,%RCX,8),%RSI

  (1125) 0x46d3a4 MOV	(%R15,%RSI,8),%RSI

  (1125) 0x46d3a8 MOV	%RDI,(%R13,%RSI,8)

  (1125) 0x46d3ad INC	%RCX

  (1125) 0x46d3b0 CMP	%RCX,%RAX

  (1125) 0x46d3b3 JNE	46d3a0

0x46d3b5 MOV	-0x70(%RBP),%RAX

0x46d3b9 MOV	(%RAX,%RDI,8),%R8

0x46d3bd MOV	-0x80(%RBP),%RCX

0x46d3c1 MOV	(%RCX,%RDI,8),%RAX

0x46d3c5 MOV	0x8(%RCX,%RDI,8),%R9

0x46d3ca INC	%RAX

0x46d3cd XORPD	%XMM4,%XMM4

0x46d3d1 XORPD	%XMM3,%XMM3

0x46d3d5 JMP	46d3e3

  (1124) 0x46d3e0 INC	%RAX

  (1124) 0x46d3e3 CMP	%R9,%RAX

  (1124) 0x46d3e6 JGE	46d460

  (1124) 0x46d3e8 MOV	(%R10,%RAX,8),%RCX

  (1124) 0x46d3ec CMPQ	$-0x3,(%R11,%RCX,8)

  (1124) 0x46d3f1 JE	46d418

  (1124) 0x46d3f3 CMPQ	$0x1,-0xa8(%RBP)

  (1124) 0x46d3fb JE	46d412

  (1124) 0x46d3fd MOV	-0x98(%RBP),%RSI

  (1124) 0x46d404 MOV	(%RSI,%RDI,8),%R10

  (1124) 0x46d408 CMP	(%RSI,%RCX,8),%R10

  (1124) 0x46d40c MOV	-0x50(%RBP),%R10

  (1124) 0x46d410 JNE	46d418

  (1124) 0x46d412 ADDSD	(%R12,%RAX,8),%XMM3

  (1124) 0x46d418 CMP	$-0x1,%RCX

  (1124) 0x46d41c JE	46d3e0

  (1124) 0x46d41e CMP	%RDI,(%R13,%RCX,8)

  (1124) 0x46d423 JNE	46d3e0

  (1124) 0x46d425 MOVSD	(%R12,%RAX,8),%XMM5

  (1124) 0x46d42b MOV	-0x30(%RBP),%RDX

  (1124) 0x46d42f MOVSD	%XMM5,(%RDX,%R8,8)

  (1124) 0x46d435 MOV	-0x100(%RBP),%RSI

  (1124) 0x46d43c MOV	(%RSI,%RCX,8),%RCX

  (1124) 0x46d440 MOV	-0xe8(%RBP),%RDX

  (1124) 0x46d447 MOV	%RCX,(%RDX,%R8,8)

  (1124) 0x46d44b INC	%R8

  (1124) 0x46d44e ADDSD	(%R12,%RAX,8),%XMM4

  (1124) 0x46d454 MOV	-0x80(%RBP),%RCX

  (1124) 0x46d458 MOV	0x8(%RCX,%RDI,8),%R9

  (1124) 0x46d45d JMP	46d3e0

0x46d460 MOV	-0xd8(%RBP),%RAX

0x46d467 MOV	(%RAX,%RDI,8),%R9

0x46d46b MOV	-0x78(%RBP),%RAX

0x46d46f MOV	(%RAX,%RDI,8),%RCX

0x46d473 MOV	0x8(%RAX,%RDI,8),%RAX

0x46d478 LEA	(%RAX,%R9,1),%R10

0x46d47c SUB	%RCX,%R10

0x46d47f CMP	%R10,%R9

0x46d482 JGE	46d544

0x46d488 MOV	-0xc0(%RBP),%RDX

0x46d48f MOV	0x8(%RDX),%R10

0x46d493 SUB	%RCX,%RAX

0x46d496 CMP	$0x8,%RAX

0x46d49a JB	46d518

0x46d4a0 MOV	%RAX,%R11

0x46d4a3 SHR	$0x3,%R11

0x46d4a7 LEA	(%R10,%R9,8),%RCX

0x46d4ab ADD	$0x38,%RCX

0x46d4af NOP

  (1123) 0x46d4b0 MOV	-0x38(%RCX),%RSI

  (1123) 0x46d4b4 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4b8 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4bc MOV	-0x30(%RCX),%RSI

  (1123) 0x46d4c0 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4c4 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4c8 MOV	-0x28(%RCX),%RSI

  (1123) 0x46d4cc MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4d0 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4d4 MOV	-0x20(%RCX),%RSI

  (1123) 0x46d4d8 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4dc MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4e0 MOV	-0x18(%RCX),%RSI

  (1123) 0x46d4e4 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4e8 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4ec MOV	-0x10(%RCX),%RSI

  (1123) 0x46d4f0 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4f4 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4f8 MOV	-0x8(%RCX),%RSI

  (1123) 0x46d4fc MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d500 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d504 MOV	(%RCX),%RSI

  (1123) 0x46d507 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d50b MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d50f ADD	$0x40,%RCX

  (1123) 0x46d513 DEC	%R11

  (1123) 0x46d516 JNE	46d4b0

0x46d518 MOV	%RAX,%RCX

0x46d51b AND	$-0x8,%RCX

0x46d51f CMP	%RAX,%RCX

0x46d522 JAE	46d544

0x46d524 LEA	(%R10,%R9,8),%R9

0x46d528 NOPL	(%RAX,%RAX,1)

  (1122) 0x46d530 MOV	(%R9,%RCX,8),%RSI

  (1122) 0x46d534 MOV	(%RBX,%RSI,8),%RSI

  (1122) 0x46d538 MOV	%RDI,(%R14,%RSI,8)

  (1122) 0x46d53c INC	%RCX

  (1122) 0x46d53f CMP	%RCX,%RAX

  (1122) 0x46d542 JNE	46d530

0x46d544 MOV	-0x78(%RBP),%RAX

0x46d548 MOV	(%RAX,%RDI,8),%R9

0x46d54c MOV	-0x90(%RBP),%RAX

0x46d553 MOV	(%RAX,%RDI,8),%R10

0x46d557 MOV	0x8(%RAX,%RDI,8),%RAX

0x46d55c CMP	%RAX,%R10

0x46d55f JGE	46d640

0x46d565 MOV	-0xb0(%RBP),%RCX

0x46d56c LEA	(%RCX,%R10,8),%R11

0x46d570 MOV	-0x88(%RBP),%RSI

0x46d577 JMP	46d590

  (1121) 0x46d580 INC	%R10

  (1121) 0x46d583 ADD	$0x8,%R11

  (1121) 0x46d587 CMP	%RAX,%R10

  (1121) 0x46d58a JGE	46d640

  (1121) 0x46d590 MOV	%R11,%RCX

  (1121) 0x46d593 TEST	%RSI,%RSI

  (1121) 0x46d596 JE	46d5a6

  (1121) 0x46d598 MOV	(%R11),%RCX

  (1121) 0x46d59b MOV	-0x108(%RBP),%RDX

  (1121) 0x46d5a2 LEA	(%RDX,%RCX,8),%RCX

  (1121) 0x46d5a6 MOV	(%RCX),%RCX

  (1121) 0x46d5a9 MOV	-0x110(%RBP),%RDX

  (1121) 0x46d5b0 CMPQ	$-0x3,(%RDX,%RCX,8)

  (1121) 0x46d5b5 JE	46d5ed

  (1121) 0x46d5b7 CMPQ	$0x1,-0xa8(%RBP)

  (1121) 0x46d5bf JE	46d5e0

  (1121) 0x46d5c1 MOV	-0x98(%RBP),%RSI

  (1121) 0x46d5c8 MOV	(%RSI,%RDI,8),%RSI

  (1121) 0x46d5cc MOV	-0xe0(%RBP),%RDX

  (1121) 0x46d5d3 CMP	(%RDX,%RCX,8),%RSI

  (1121) 0x46d5d7 MOV	-0x88(%RBP),%RSI

  (1121) 0x46d5de JNE	46d5ed

  (1121) 0x46d5e0 MOV	-0xa0(%RBP),%RDX

  (1121) 0x46d5e7 ADDSD	(%RDX,%R10,8),%XMM3

  (1121) 0x46d5ed CMP	$-0x1,%RCX

  (1121) 0x46d5f1 JE	46d580

  (1121) 0x46d5f3 CMP	%RDI,(%R14,%RCX,8)

  (1121) 0x46d5f7 JNE	46d580

  (1121) 0x46d5f9 MOV	-0xa0(%RBP),%RDX

  (1121) 0x46d600 MOVSD	(%RDX,%R10,8),%XMM5

  (1121) 0x46d606 MOV	-0x38(%RBP),%RAX

  (1121) 0x46d60a MOVSD	%XMM5,(%RAX,%R9,8)

  (1121) 0x46d610 MOV	-0xf8(%RBP),%RAX

  (1121) 0x46d617 MOV	(%RAX,%RCX,8),%RAX

  (1121) 0x46d61b MOV	-0xf0(%RBP),%RCX

  (1121) 0x46d622 MOV	%RAX,(%RCX,%R9,8)

  (1121) 0x46d626 INC	%R9

  (1121) 0x46d629 ADDSD	(%RDX,%R10,8),%XMM4

  (1121) 0x46d62f MOV	-0x90(%RBP),%RAX

  (1121) 0x46d636 MOV	0x8(%RAX,%RDI,8),%RAX

  (1121) 0x46d63b JMP	46d580

0x46d640 MOV	-0x80(%RBP),%RAX

0x46d644 MOV	(%RAX,%RDI,8),%RAX

0x46d648 MULSD	(%R12,%RAX,8),%XMM4

0x46d64e UCOMISD	%XMM0,%XMM4

0x46d652 JE	46d660

0x46d654 XORPD	%XMM1,%XMM3

0x46d658 DIVSD	%XMM4,%XMM3

0x46d65c MOVAPD	%XMM3,%XMM2

0x46d660 MOV	-0x70(%RBP),%RAX

0x46d664 MOV	(%RAX,%RDI,8),%R10

0x46d668 SUB	%R10,%R8

0x46d66b MOV	-0x48(%RBP),%R11

0x46d66f MOV	-0x40(%RBP),%RDX

0x46d673 JLE	46d80c

0x46d679 CMP	$0x8,%R8

0x46d67d JB	46d72b

0x46d683 MOV	%R8,%RAX

0x46d686 SHR	$0x3,%RAX

0x46d68a MOV	-0x68(%RBP),%RCX

0x46d68e LEA	(%RCX,%R10,8),%R11

0x46d692 NOPW	%CS:(%RAX,%RAX,1)

  (1120) 0x46d6a0 MOVSD	-0x38(%R11),%XMM3

  (1120) 0x46d6a6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6aa MOVSD	%XMM3,-0x38(%R11)

  (1120) 0x46d6b0 MOVSD	-0x30(%R11),%XMM3

  (1120) 0x46d6b6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ba MOVSD	%XMM3,-0x30(%R11)

  (1120) 0x46d6c0 MOVSD	-0x28(%R11),%XMM3

  (1120) 0x46d6c6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ca MOVSD	%XMM3,-0x28(%R11)

  (1120) 0x46d6d0 MOVSD	-0x20(%R11),%XMM3

  (1120) 0x46d6d6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6da MOVSD	%XMM3,-0x20(%R11)

  (1120) 0x46d6e0 MOVSD	-0x18(%R11),%XMM3

  (1120) 0x46d6e6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ea MOVSD	%XMM3,-0x18(%R11)

  (1120) 0x46d6f0 MOVSD	-0x10(%R11),%XMM3

  (1120) 0x46d6f6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6fa MOVSD	%XMM3,-0x10(%R11)

  (1120) 0x46d700 MOVSD	-0x8(%R11),%XMM3

  (1120) 0x46d706 MULSD	%XMM2,%XMM3

  (1120) 0x46d70a MOVSD	%XMM3,-0x8(%R11)

  (1120) 0x46d710 MOVSD	(%R11),%XMM3

  (1120) 0x46d715 MULSD	%XMM2,%XMM3

  (1120) 0x46d719 MOVSD	%XMM3,(%R11)

  (1120) 0x46d71e ADD	$0x40,%R11

  (1120) 0x46d722 DEC	%RAX

  (1120) 0x46d725 JNE	46d6a0

0x46d72b MOV	%R8D,%EAX

0x46d72e AND	$0x7,%EAX

0x46d731 DEC	%RAX

0x46d734 CMP	$0x6,%RAX

0x46d738 MOV	-0x48(%RBP),%R11

0x46d73c JA	46d80c

0x46d80c MOV	-0x78(%RBP),%RAX

0x46d810 MOV	(%RAX,%RDI,8),%RDI

0x46d814 SUB	%RDI,%R9

0x46d817 MOV	-0x50(%RBP),%R10

0x46d81b JLE	46d2a2

0x46d821 CMP	$0x8,%R9

0x46d825 JB	46d8cb

0x46d82b MOV	%R9,%RAX

0x46d82e SHR	$0x3,%RAX

0x46d832 MOV	-0x60(%RBP),%RCX

0x46d836 LEA	(%RCX,%RDI,8),%R8

0x46d83a NOPW	(%RAX,%RAX,1)

  (1119) 0x46d840 MOVSD	-0x38(%R8),%XMM3

  (1119) 0x46d846 MULSD	%XMM2,%XMM3

  (1119) 0x46d84a MOVSD	%XMM3,-0x38(%R8)

  (1119) 0x46d850 MOVSD	-0x30(%R8),%XMM3

  (1119) 0x46d856 MULSD	%XMM2,%XMM3

  (1119) 0x46d85a MOVSD	%XMM3,-0x30(%R8)

  (1119) 0x46d860 MOVSD	-0x28(%R8),%XMM3

  (1119) 0x46d866 MULSD	%XMM2,%XMM3

  (1119) 0x46d86a MOVSD	%XMM3,-0x28(%R8)

  (1119) 0x46d870 MOVSD	-0x20(%R8),%XMM3

  (1119) 0x46d876 MULSD	%XMM2,%XMM3

  (1119) 0x46d87a MOVSD	%XMM3,-0x20(%R8)

  (1119) 0x46d880 MOVSD	-0x18(%R8),%XMM3

  (1119) 0x46d886 MULSD	%XMM2,%XMM3

  (1119) 0x46d88a MOVSD	%XMM3,-0x18(%R8)

  (1119) 0x46d890 MOVSD	-0x10(%R8),%XMM3

  (1119) 0x46d896 MULSD	%XMM2,%XMM3

  (1119) 0x46d89a MOVSD	%XMM3,-0x10(%R8)

  (1119) 0x46d8a0 MOVSD	-0x8(%R8),%XMM3

  (1119) 0x46d8a6 MULSD	%XMM2,%XMM3

  (1119) 0x46d8aa MOVSD	%XMM3,-0x8(%R8)

  (1119) 0x46d8b0 MOVSD	(%R8),%XMM3

  (1119) 0x46d8b5 MULSD	%XMM2,%XMM3

  (1119) 0x46d8b9 MOVSD	%XMM3,(%R8)

  (1119) 0x46d8be ADD	$0x40,%R8

  (1119) 0x46d8c2 DEC	%RAX

  (1119) 0x46d8c5 JNE	46d840

0x46d8cb MOV	%R9D,%EAX

0x46d8ce AND	$0x7,%EAX

0x46d8d1 DEC	%RAX

0x46d8d4 CMP	$0x6,%RAX

0x46d8d8 JA	46d2a2

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1585 - 1660

--------------------------------------------------------------------------------

1585:            if (n_fine)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►97.07+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.81+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1575	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.42
CQA speedup if FP arith vectorized	3.78
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source	par_multi_interp.c:1585-1585,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1614,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1635,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	3.84
CQA cycles if fully vectorized	1.81
Front-end cycles	14.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	11.25
P7 cycles	11.25
P8 cycles	11.25
P9 cycles	11.25
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	116.00
Nb loads	44.00
Nb stores	1.00
Nb stack references	17.00
FLOP/cycle	0.14
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.83
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	15.38
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	14.42
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.28

Metric	Value
CQA speedup if no scalar integer	2.42
CQA speedup if FP arith vectorized	3.78
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source	par_multi_interp.c:1585-1585,par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1614,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1635,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	3.84
CQA cycles if fully vectorized	1.81
Front-end cycles	14.50
P0 cycles	9.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	9.50
P6 cycles	11.25
P7 cycles	11.25
P8 cycles	11.25
P9 cycles	11.25
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	116.00
Nb loads	44.00
Nb stores	1.00
Nb stack references	17.00
FLOP/cycle	0.14
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.83
Bytes prefetched	0.00
Bytes loaded	352.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	15.38
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	14.42
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	15.28

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source file and lines	par_multi_interp.c:1585-1660
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1585,1605-1660.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1585,1605-1607,1610-1614,1617-1618,1631-1635,1638-1639,1655-1659.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 6.00 cycles (2.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.50 to 1.81 cycles (8.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1656

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 352 bytes (44 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	116
loop length	523
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	11.25	11.25	11.25	11.25	1.00	1.00	1.00	1.00	0.50	0.50
cycles	9.50	9.50	9.50	9.50	9.50	9.50	11.25	11.25	11.25	11.25	1.00	1.00	1.00	1.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	14.50
Dispatch	11.25
DIV/SQRT	4.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	57%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	80%

INT+FP

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	22%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

9% of peak load performance is reached (24.28 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 11.25 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 46d2a2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x58(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 46d931 <hypre_BoomerAMGBuildMultipass.extracted.27+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%R8,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d3b5 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d380 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JAE 46d3b5 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R9,%R8,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XORPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 46d3e3 <hypre_BoomerAMGBuildMultipass.extracted.27+0x423>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d544 <hypre_BoomerAMGBuildMultipass.extracted.27+0x584>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d518 <hypre_BoomerAMGBuildMultipass.extracted.27+0x558>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%R10,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46d544 <hypre_BoomerAMGBuildMultipass.extracted.27+0x584>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R10,%R9,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d640 <hypre_BoomerAMGBuildMultipass.extracted.27+0x680>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 46d590 <hypre_BoomerAMGBuildMultipass.extracted.27+0x5d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MULSD (%R12,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JE 46d660 <hypre_BoomerAMGBuildMultipass.extracted.27+0x6a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XORPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
DIVSD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 46d80c <hypre_BoomerAMGBuildMultipass.extracted.27+0x84c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d72b <hypre_BoomerAMGBuildMultipass.extracted.27+0x76b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JA 46d80c <hypre_BoomerAMGBuildMultipass.extracted.27+0x84c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 46d2a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d8cb <hypre_BoomerAMGBuildMultipass.extracted.27+0x90b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 46d2a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_BoomerAMGBuildMultipass.extracted.27
Source file and lines	par_multi_interp.c:1585-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.50 to 6.00 cycles (2.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

UCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1656

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 352 bytes (44 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	116
loop length	523
used x86 registers	11
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	9.50	9.50	9.50	9.50	9.50	9.50	11.25	11.25	11.25	11.25	1.00	1.00	1.00	1.00	0.50	0.50
cycles	9.50	9.50	9.50	9.50	9.50	9.50	11.25	11.25	11.25	11.25	1.00	1.00	1.00	1.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	14.50
Dispatch	11.25
DIV/SQRT	4.00
Overall L1	14.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	57%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	80%

INT+FP

all	15%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	22%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	22%

INT+FP

all	14%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

9% of peak load performance is reached (24.28 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.55 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 46d2a2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP -0x58(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JGE 46d931 <hypre_BoomerAMGBuildMultipass.extracted.27+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX,%RDX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%R8,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d3b5 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d380 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R10	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LEA (%R9,%R8,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JAE 46d3b5 <hypre_BoomerAMGBuildMultipass.extracted.27+0x3f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R9,%R8,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XORPD %XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XORPD %XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 46d3e3 <hypre_BoomerAMGBuildMultipass.extracted.27+0x423>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RAX,%R9,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d544 <hypre_BoomerAMGBuildMultipass.extracted.27+0x584>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d518 <hypre_BoomerAMGBuildMultipass.extracted.27+0x558>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x3,%R11	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LEA (%R10,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x38,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 46d544 <hypre_BoomerAMGBuildMultipass.extracted.27+0x584>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%R10,%R9,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d640 <hypre_BoomerAMGBuildMultipass.extracted.27+0x680>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JMP 46d590 <hypre_BoomerAMGBuildMultipass.extracted.27+0x5d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MULSD (%R12,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
UCOMISD %XMM0,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	7	1	scal (12.5%)
JE 46d660 <hypre_BoomerAMGBuildMultipass.extracted.27+0x6a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XORPD %XMM1,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
DIVSD %XMM4,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOVAPD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R10,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 46d80c <hypre_BoomerAMGBuildMultipass.extracted.27+0x84c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d72b <hypre_BoomerAMGBuildMultipass.extracted.27+0x76b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%R10,8),%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
JA 46d80c <hypre_BoomerAMGBuildMultipass.extracted.27+0x84c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RDI,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JLE 46d2a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 46d8cb <hypre_BoomerAMGBuildMultipass.extracted.27+0x90b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x60(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RCX,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x6,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JA 46d2a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code