OV - exec - Function hypre_ParCSRRelaxThreads.extracted.57

	Function: hypre_ParCSRRelaxThreads.extracted.57	Module: exec	Source: ams.c:3662-3682	Coverage (incl. loops): 47.26% \| (excl. loops): 4.46%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x52bcb0 PUSH	%RBP

0x52bcb1 MOV	%RSP,%RBP

0x52bcb4 PUSH	%R15

0x52bcb6 PUSH	%R14

0x52bcb8 PUSH	%R13

0x52bcba PUSH	%R12

0x52bcbc PUSH	%RBX

0x52bcbd SUB	$0x58,%RSP

0x52bcc1 MOV	%R9,-0x30(%RBP)

0x52bcc5 MOV	%R8,%R14

0x52bcc8 MOV	%RCX,-0x40(%RBP)

0x52bccc MOV	%RDX,-0x70(%RBP)

0x52bcd0 MOV	0x48(%RBP),%RAX

0x52bcd4 MOV	%RAX,-0x38(%RBP)

0x52bcd8 MOV	0x40(%RBP),%R15

0x52bcdc MOV	0x38(%RBP),%RAX

0x52bce0 MOV	%RAX,-0x68(%RBP)

0x52bce4 MOV	0x30(%RBP),%RAX

0x52bce8 MOV	%RAX,-0x60(%RBP)

0x52bcec MOV	0x28(%RBP),%R13

0x52bcf0 MOV	0x20(%RBP),%RBX

0x52bcf4 MOV	0x18(%RBP),%RAX

0x52bcf8 MOV	%RAX,-0x58(%RBP)

0x52bcfc MOV	0x10(%RBP),%R12

0x52bd00 MOVL	$0,-0x48(%RBP)

0x52bd07 MOV	(%RDI),%ESI

0x52bd09 MOVQ	$0,-0x50(%RBP)

0x52bd11 MOVQ	$0x1,-0x80(%RBP)

0x52bd19 SUB	$0x8,%RSP

0x52bd1d LEA	-0x80(%RBP),%RAX

0x52bd21 LEA	-0x48(%RBP),%RCX

0x52bd25 LEA	-0x50(%RBP),%R8

0x52bd29 LEA	0x60(%RBP),%R9

0x52bd2d MOV	$0x60a150,%EDI

0x52bd32 MOV	%ESI,-0x44(%RBP)

0x52bd35 MOV	$0x22,%EDX

0x52bd3a PUSH	$0x1

0x52bd3c PUSH	$0x1

0x52bd3e PUSH	%RAX

0x52bd3f CALL	41dc20 <__kmpc_for_static_init_8@plt>

0x52bd44 MOV	-0x30(%RBP),%R9

0x52bd48 ADD	$0x20,%RSP

0x52bd4c MOV	-0x50(%RBP),%RCX

0x52bd50 MOV	0x60(%RBP),%RAX

0x52bd54 SUB	%RCX,%RAX

0x52bd57 MOV	%RAX,-0x78(%RBP)

0x52bd5b JAE	52bd78

0x52bd5d MOV	$0x60a170,%EDI

0x52bd62 MOV	-0x44(%RBP),%ESI

0x52bd65 ADD	$0x58,%RSP

0x52bd69 POP	%RBX

0x52bd6a POP	%R12

0x52bd6c POP	%R13

0x52bd6e POP	%R14

0x52bd70 POP	%R15

0x52bd72 POP	%RBP

0x52bd73 JMP	41d3d0

0x52bd78 MOVSD	-0x40(%RBP),%XMM0

0x52bd7d XOR	%EDX,%EDX

0x52bd7f XORPD	%XMM1,%XMM1

0x52bd83 MOV	%RCX,-0x40(%RBP)

0x52bd87 JMP	52bdc8

(3956) 0x52bd89 MOV	-0x30(%RBP),%R9

(3956) 0x52bd8d MOV	-0x40(%RBP),%RCX

(3956) 0x52bd91 NOPW	%CS:(%RAX,%RAX,1)

(3956) 0x52bda0 MULSD	%XMM0,%XMM2

(3956) 0x52bda4 MOV	-0x70(%RBP),%RAX

(3956) 0x52bda8 DIVSD	(%RAX,%RSI,8),%XMM2

(3956) 0x52bdad MOV	-0x60(%RBP),%RAX

(3956) 0x52bdb1 ADDSD	(%RAX,%RSI,8),%XMM2

(3956) 0x52bdb6 MOVSD	%XMM2,(%RAX,%RSI,8)

  (3955) 0x52bdbb LEA	0x1(%RDX),%RAX

  (3955) 0x52bdbf CMP	-0x78(%RBP),%RDX

  (3955) 0x52bdc3 MOV	%RAX,%RDX

  (3955) 0x52bdc6 JE	52bd5d

  (3955) 0x52bdc8 LEA	(%RCX,%RDX,1),%RSI

  (3955) 0x52bdcc MOV	(%R9,%RSI,8),%RDI

  (3955) 0x52bdd0 UCOMISD	(%R14,%RDI,8),%XMM1

  (3955) 0x52bdd6 JE	52bdbb

(3956) 0x52bdd8 MOV	-0x68(%RBP),%RAX

(3956) 0x52bddc MOVSD	(%RAX,%RSI,8),%XMM2

(3956) 0x52bde1 MOV	0x8(%R9,%RSI,8),%R8

(3956) 0x52bde6 SUB	%RDI,%R8

(3956) 0x52bde9 JLE	52bfc7

(3956) 0x52bdef CMP	$0x8,%R8

(3956) 0x52bdf3 JB	52becb

(3956) 0x52bdf9 MOV	%R8,%R9

(3956) 0x52bdfc SHR	$0x3,%R9

(3956) 0x52be00 LEA	0x38(,%RDI,8),%R10

(3956) 0x52be08 NOPL	(%RAX,%RAX,1)

  (3958) 0x52be10 MOV	-0x38(%R12,%R10,1),%R11

  (3958) 0x52be15 MOV	-0x30(%R12,%R10,1),%RAX

  (3958) 0x52be1a MOVSD	(%R15,%R11,8),%XMM3

  (3958) 0x52be20 MULSD	-0x38(%R14,%R10,1),%XMM3

  (3958) 0x52be27 MOVSD	(%R15,%RAX,8),%XMM4

  (3958) 0x52be2d MULSD	-0x30(%R14,%R10,1),%XMM4

  (3958) 0x52be34 ADDSD	%XMM3,%XMM4

  (3958) 0x52be38 MOV	-0x28(%R12,%R10,1),%RAX

  (3958) 0x52be3d MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be43 MULSD	-0x28(%R14,%R10,1),%XMM3

  (3958) 0x52be4a MOV	-0x20(%R12,%R10,1),%RAX

  (3958) 0x52be4f MOVSD	(%R15,%RAX,8),%XMM5

  (3958) 0x52be55 MULSD	-0x20(%R14,%R10,1),%XMM5

  (3958) 0x52be5c ADDSD	%XMM3,%XMM5

  (3958) 0x52be60 MOV	-0x18(%R12,%R10,1),%RAX

  (3958) 0x52be65 MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be6b MULSD	-0x18(%R14,%R10,1),%XMM3

  (3958) 0x52be72 MOV	-0x10(%R12,%R10,1),%RAX

  (3958) 0x52be77 MOVSD	(%R15,%RAX,8),%XMM6

  (3958) 0x52be7d MULSD	-0x10(%R14,%R10,1),%XMM6

  (3958) 0x52be84 ADDSD	%XMM4,%XMM5

  (3958) 0x52be88 ADDSD	%XMM3,%XMM6

  (3958) 0x52be8c MOV	-0x8(%R12,%R10,1),%RAX

  (3958) 0x52be91 MOVSD	(%R15,%RAX,8),%XMM3

  (3958) 0x52be97 MULSD	-0x8(%R14,%R10,1),%XMM3

  (3958) 0x52be9e ADDSD	%XMM6,%XMM3

  (3958) 0x52bea2 ADDSD	%XMM5,%XMM3

  (3958) 0x52bea6 MOV	(%R12,%R10,1),%RAX

  (3958) 0x52beaa MOVSD	(%R15,%RAX,8),%XMM4

  (3958) 0x52beb0 MULSD	(%R14,%R10,1),%XMM4

  (3958) 0x52beb6 ADDSD	%XMM3,%XMM4

  (3958) 0x52beba SUBSD	%XMM4,%XMM2

  (3958) 0x52bebe ADD	$0x40,%R10

  (3958) 0x52bec2 DEC	%R9

  (3958) 0x52bec5 JNE	52be10

(3956) 0x52becb MOV	%R8D,%R9D

(3956) 0x52bece AND	$0x7,%R9D

(3956) 0x52bed2 DEC	%R9

(3956) 0x52bed5 CMP	$0x6,%R9

(3956) 0x52bed9 JA	52bf11

0x52bedb AND	$-0x8,%R8

0x52bedf JMP	0x5d9f38(,%R9,8)

0x52bee7 ADD	%R8,%RDI

0x52beea MOV	-0x30(%RBP),%R9

0x52beee JMP	52bfb3

0x52bef3 ADD	%R8,%RDI

0x52bef6 MOV	-0x30(%RBP),%R9

0x52befa JMP	52bf87

0x52beff ADD	%R8,%RDI

0x52bf02 MOV	-0x30(%RBP),%R9

0x52bf06 JMP	52bf71

0x52bf08 ADD	%R8,%RDI

0x52bf0b MOV	-0x30(%RBP),%R9

0x52bf0f JMP	52bf5b

(3956) 0x52bf11 MOV	-0x30(%RBP),%R9

(3956) 0x52bf15 JMP	52bfc7

0x52bf1a ADD	%R8,%RDI

0x52bf1d MOV	-0x30(%RBP),%R9

0x52bf21 JMP	52bf9d

0x52bf23 ADD	%R8,%RDI

0x52bf26 JMP	52bf41

0x52bf28 ADD	%R8,%RDI

0x52bf2b MOV	0x30(%R12,%RDI,8),%RAX

0x52bf30 MOVSD	(%R15,%RAX,8),%XMM3

0x52bf36 MULSD	0x30(%R14,%RDI,8),%XMM3

0x52bf3d SUBSD	%XMM3,%XMM2

0x52bf41 MOV	-0x30(%RBP),%R9

0x52bf45 MOV	0x28(%R12,%RDI,8),%RAX

0x52bf4a MOVSD	(%R15,%RAX,8),%XMM3

0x52bf50 MULSD	0x28(%R14,%RDI,8),%XMM3

0x52bf57 SUBSD	%XMM3,%XMM2

0x52bf5b MOV	0x20(%R12,%RDI,8),%RAX

0x52bf60 MOVSD	(%R15,%RAX,8),%XMM3

0x52bf66 MULSD	0x20(%R14,%RDI,8),%XMM3

0x52bf6d SUBSD	%XMM3,%XMM2

0x52bf71 MOV	0x18(%R12,%RDI,8),%RAX

0x52bf76 MOVSD	(%R15,%RAX,8),%XMM3

0x52bf7c MULSD	0x18(%R14,%RDI,8),%XMM3

0x52bf83 SUBSD	%XMM3,%XMM2

0x52bf87 MOV	0x10(%R12,%RDI,8),%RAX

0x52bf8c MOVSD	(%R15,%RAX,8),%XMM3

0x52bf92 MULSD	0x10(%R14,%RDI,8),%XMM3

0x52bf99 SUBSD	%XMM3,%XMM2

0x52bf9d MOV	0x8(%R12,%RDI,8),%RAX

0x52bfa2 MOVSD	(%R15,%RAX,8),%XMM3

0x52bfa8 MULSD	0x8(%R14,%RDI,8),%XMM3

0x52bfaf SUBSD	%XMM3,%XMM2

0x52bfb3 MOV	(%R12,%RDI,8),%RAX

0x52bfb7 MOVSD	(%R15,%RAX,8),%XMM3

0x52bfbd MULSD	(%R14,%RDI,8),%XMM3

0x52bfc3 SUBSD	%XMM3,%XMM2

(3956) 0x52bfc7 MOV	-0x58(%RBP),%RAX

(3956) 0x52bfcb MOV	(%RAX,%RSI,8),%RDI

(3956) 0x52bfcf MOV	0x8(%RAX,%RSI,8),%R8

(3956) 0x52bfd4 SUB	%RDI,%R8

(3956) 0x52bfd7 JLE	52bda0

(3956) 0x52bfdd CMP	$0x8,%R8

(3956) 0x52bfe1 JB	52c0b5

(3956) 0x52bfe7 MOV	%R8,%R9

(3956) 0x52bfea SHR	$0x3,%R9

(3956) 0x52bfee LEA	0x38(,%RDI,8),%R10

(3956) 0x52bff6 MOV	-0x38(%RBP),%RCX

(3956) 0x52bffa NOPW	(%RAX,%RAX,1)

  (3957) 0x52c000 MOV	-0x38(%R13,%R10,1),%RAX

  (3957) 0x52c005 MOV	-0x30(%R13,%R10,1),%R11

  (3957) 0x52c00a MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c00f MULSD	-0x38(%RBX,%R10,1),%XMM3

  (3957) 0x52c016 MOVSD	(%RCX,%R11,8),%XMM4

  (3957) 0x52c01c MULSD	-0x30(%RBX,%R10,1),%XMM4

  (3957) 0x52c023 ADDSD	%XMM3,%XMM4

  (3957) 0x52c027 MOV	-0x28(%R13,%R10,1),%RAX

  (3957) 0x52c02c MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c031 MULSD	-0x28(%RBX,%R10,1),%XMM3

  (3957) 0x52c038 MOV	-0x20(%R13,%R10,1),%RAX

  (3957) 0x52c03d MOVSD	(%RCX,%RAX,8),%XMM5

  (3957) 0x52c042 MULSD	-0x20(%RBX,%R10,1),%XMM5

  (3957) 0x52c049 ADDSD	%XMM3,%XMM5

  (3957) 0x52c04d MOV	-0x18(%R13,%R10,1),%RAX

  (3957) 0x52c052 MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c057 MULSD	-0x18(%RBX,%R10,1),%XMM3

  (3957) 0x52c05e MOV	-0x10(%R13,%R10,1),%RAX

  (3957) 0x52c063 MOVSD	(%RCX,%RAX,8),%XMM6

  (3957) 0x52c068 MULSD	-0x10(%RBX,%R10,1),%XMM6

  (3957) 0x52c06f ADDSD	%XMM4,%XMM5

  (3957) 0x52c073 ADDSD	%XMM3,%XMM6

  (3957) 0x52c077 MOV	-0x8(%R13,%R10,1),%RAX

  (3957) 0x52c07c MOVSD	(%RCX,%RAX,8),%XMM3

  (3957) 0x52c081 MULSD	-0x8(%RBX,%R10,1),%XMM3

  (3957) 0x52c088 ADDSD	%XMM6,%XMM3

  (3957) 0x52c08c ADDSD	%XMM5,%XMM3

  (3957) 0x52c090 MOV	(%R13,%R10,1),%RAX

  (3957) 0x52c095 MOVSD	(%RCX,%RAX,8),%XMM4

  (3957) 0x52c09a MULSD	(%RBX,%R10,1),%XMM4

  (3957) 0x52c0a0 ADDSD	%XMM3,%XMM4

  (3957) 0x52c0a4 SUBSD	%XMM4,%XMM2

  (3957) 0x52c0a8 ADD	$0x40,%R10

  (3957) 0x52c0ac DEC	%R9

  (3957) 0x52c0af JNE	52c000

(3956) 0x52c0b5 MOV	%R8D,%R9D

(3956) 0x52c0b8 AND	$0x7,%R9D

(3956) 0x52c0bc DEC	%R9

(3956) 0x52c0bf CMP	$0x6,%R9

(3956) 0x52c0c3 JA	52bd89

0x52c0c9 AND	$-0x8,%R8

0x52c0cd JMP	0x5d9f70(,%R9,8)

0x52c0d5 ADD	%R8,%RDI

0x52c0d8 MOV	-0x30(%RBP),%R9

0x52c0dc MOV	-0x38(%RBP),%R8

0x52c0e0 MOV	-0x40(%RBP),%RCX

0x52c0e4 JMP	52c1c1

0x52c0e9 ADD	%R8,%RDI

0x52c0ec MOV	-0x30(%RBP),%R9

0x52c0f0 MOV	-0x38(%RBP),%R8

0x52c0f4 JMP	52c193

0x52c0f9 ADD	%R8,%RDI

0x52c0fc MOV	-0x30(%RBP),%R9

0x52c100 MOV	-0x38(%RBP),%R8

0x52c104 JMP	52c17e

0x52c106 ADD	%R8,%RDI

0x52c109 MOV	-0x30(%RBP),%R9

0x52c10d MOV	-0x38(%RBP),%R8

0x52c111 JMP	52c169

0x52c113 ADD	%R8,%RDI

0x52c116 MOV	-0x30(%RBP),%R9

0x52c11a MOV	-0x38(%RBP),%R8

0x52c11e MOV	-0x40(%RBP),%RCX

0x52c122 JMP	52c1ac

0x52c127 ADD	%R8,%RDI

0x52c12a MOV	-0x30(%RBP),%R9

0x52c12e MOV	-0x38(%RBP),%R8

0x52c132 JMP	52c154

0x52c134 ADD	%R8,%RDI

0x52c137 MOV	0x30(%R13,%RDI,8),%RAX

0x52c13c MOV	-0x38(%RBP),%R8

0x52c140 MOVSD	(%R8,%RAX,8),%XMM3

0x52c146 MULSD	0x30(%RBX,%RDI,8),%XMM3

0x52c14c SUBSD	%XMM3,%XMM2

0x52c150 MOV	-0x30(%RBP),%R9

0x52c154 MOV	0x28(%R13,%RDI,8),%RAX

0x52c159 MOVSD	(%R8,%RAX,8),%XMM3

0x52c15f MULSD	0x28(%RBX,%RDI,8),%XMM3

0x52c165 SUBSD	%XMM3,%XMM2

0x52c169 MOV	0x20(%R13,%RDI,8),%RAX

0x52c16e MOVSD	(%R8,%RAX,8),%XMM3

0x52c174 MULSD	0x20(%RBX,%RDI,8),%XMM3

0x52c17a SUBSD	%XMM3,%XMM2

0x52c17e MOV	0x18(%R13,%RDI,8),%RAX

0x52c183 MOVSD	(%R8,%RAX,8),%XMM3

0x52c189 MULSD	0x18(%RBX,%RDI,8),%XMM3

0x52c18f SUBSD	%XMM3,%XMM2

0x52c193 MOV	-0x40(%RBP),%RCX

0x52c197 MOV	0x10(%R13,%RDI,8),%RAX

0x52c19c MOVSD	(%R8,%RAX,8),%XMM3

0x52c1a2 MULSD	0x10(%RBX,%RDI,8),%XMM3

0x52c1a8 SUBSD	%XMM3,%XMM2

0x52c1ac MOV	0x8(%R13,%RDI,8),%RAX

0x52c1b1 MOVSD	(%R8,%RAX,8),%XMM3

0x52c1b7 MULSD	0x8(%RBX,%RDI,8),%XMM3

0x52c1bd SUBSD	%XMM3,%XMM2

0x52c1c1 MOV	(%R13,%RDI,8),%RAX

0x52c1c6 MOVSD	(%R8,%RAX,8),%XMM3

0x52c1cc MULSD	(%RBX,%RDI,8),%XMM3

0x52c1d1 SUBSD	%XMM3,%XMM2

0x52c1d5 JMP	52bda0

0x52c1da NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.10+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.82+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_ParCSRRelaxThreads	ams.c:3866	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:272	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 4.46% of application time for run icx_5

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.75 to 9.00 cycles (2.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 23.75 to 2.14 cycles (11.09x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 23.75 to 21.88 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

14: addition or subtraction
14: multiply

The binary function is loading 640 bytes (80 double precision FP elements). The binary function is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	173
nb uops	175
loop length	723
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	21
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	23.75	23.75	23.75	23.75	7.00	7.00	7.00	7.00	0.00	0.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	23.75	23.75	23.75	23.75	7.00	7.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	23.75
Overall L1	23.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.75 cycles. At this rate:

10% of peak load performance is reached (26.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 52bcb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x58,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x80(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x60a150,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 52bd78 <hypre_ParCSRRelaxThreads.extracted.57+0xc8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x60a170,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x58,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOVSD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XORPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 52bdc8 <hypre_ParCSRRelaxThreads.extracted.57+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5d9f38(,%R9,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bfb3 <hypre_ParCSRRelaxThreads.extracted.57+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf87 <hypre_ParCSRRelaxThreads.extracted.57+0x2d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf71 <hypre_ParCSRRelaxThreads.extracted.57+0x2c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf5b <hypre_ParCSRRelaxThreads.extracted.57+0x2ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf9d <hypre_ParCSRRelaxThreads.extracted.57+0x2ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 52bf41 <hypre_ParCSRRelaxThreads.extracted.57+0x291>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x10(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5d9f70(,%R9,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 52c1c1 <hypre_ParCSRRelaxThreads.extracted.57+0x511>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c193 <hypre_ParCSRRelaxThreads.extracted.57+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c17e <hypre_ParCSRRelaxThreads.extracted.57+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c169 <hypre_ParCSRRelaxThreads.extracted.57+0x4b9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 52c1ac <hypre_ParCSRRelaxThreads.extracted.57+0x4fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c154 <hypre_ParCSRRelaxThreads.extracted.57+0x4a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
JMP 52bda0 <hypre_ParCSRRelaxThreads.extracted.57+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 4.46% of application time for run icx_5

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.75 to 9.00 cycles (2.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 23.75 to 21.88 cycles (1.09x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Type of elements and instruction set

28 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 28 FP arithmetical operations:

14: addition or subtraction
14: multiply

The binary function is loading 640 bytes (80 double precision FP elements). The binary function is storing 96 bytes (12 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	173
nb uops	175
loop length	723
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	21
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.83	7.83	7.83	7.83	7.83	7.83	23.75	23.75	23.75	23.75	7.00	7.00	7.00	7.00	0.00	0.00
cycles	7.83	7.83	7.83	7.83	7.83	7.83	23.75	23.75	23.75	23.75	7.00	7.00	7.00	7.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	23.75
Overall L1	23.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	2%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.75 cycles. At this rate:

10% of peak load performance is reached (26.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.04 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 52bcb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x58,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x80(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x60(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x60a150,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x44(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 52bd78 <hypre_ParCSRRelaxThreads.extracted.57+0xc8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x60a170,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x44(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x58,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOVSD -0x40(%RBP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XORPD %XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JMP 52bdc8 <hypre_ParCSRRelaxThreads.extracted.57+0x118>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5d9f38(,%R9,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bfb3 <hypre_ParCSRRelaxThreads.extracted.57+0x303>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf87 <hypre_ParCSRRelaxThreads.extracted.57+0x2d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf71 <hypre_ParCSRRelaxThreads.extracted.57+0x2c1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf5b <hypre_ParCSRRelaxThreads.extracted.57+0x2ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52bf9d <hypre_ParCSRRelaxThreads.extracted.57+0x2ed>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 52bf41 <hypre_ParCSRRelaxThreads.extracted.57+0x291>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x10(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R12,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R15,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5d9f70(,%R9,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 52c1c1 <hypre_ParCSRRelaxThreads.extracted.57+0x511>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c193 <hypre_ParCSRRelaxThreads.extracted.57+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c17e <hypre_ParCSRRelaxThreads.extracted.57+0x4ce>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c169 <hypre_ParCSRRelaxThreads.extracted.57+0x4b9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 52c1ac <hypre_ParCSRRelaxThreads.extracted.57+0x4fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 52c154 <hypre_ParCSRRelaxThreads.extracted.57+0x4a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x30(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R13,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%R8,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%RBX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
SUBSD %XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
JMP 52bda0 <hypre_ParCSRRelaxThreads.extracted.57+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads.extracted.57–	47.26	24.68
▼Loop 3956 - ams.c:3662-3682 - exec–	16.02	7.85
○Loop 3958 - ams.c:3672-3675 - exec	25.99	12.73
○Loop 3955 - ams.c:3662-3669 - exec	0.73	0.36
○Loop 3957 - ams.c:3677-3680 - exec	0.08	0.04

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