OV - exec - Function hypre_BoomerAMGCreate2ndS.extracted

	Function: hypre_BoomerAMGCreate2ndS.extracted	Module: exec	Source: par_strength.c:1253-1278 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

[...]

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x500130 PUSH	%RBP

0x500131 MOV	%RSP,%RBP

0x500134 PUSH	%R15

0x500136 PUSH	%R14

0x500138 PUSH	%R12

0x50013a PUSH	%RBX

0x50013b SUB	$0x20,%RSP

0x50013f MOV	%R9,%R15

0x500142 MOV	%R8,%RBX

0x500145 MOV	%RDX,%R14

0x500148 MOV	0x10(%RBP),%R12

0x50014c LEA	-0x30(%RBP),%RDI

0x500150 LEA	-0x38(%RBP),%RSI

0x500154 MOV	%RCX,%RDX

0x500157 CALL	41d3a0 <@plt>

0x50015c MOV	-0x30(%RBP),%RAX

0x500160 MOV	-0x38(%RBP),%RDX

0x500164 SUB	%RAX,%RDX

0x500167 JLE	500176

0x500169 CMP	$0x8,%RDX

0x50016d JAE	50017d

0x50016f XOR	%ECX,%ECX

0x500171 JMP	50020c

0x500176 XOR	%ECX,%ECX

0x500178 JMP	5002ab

0x50017d MOV	%RDX,%RSI

0x500180 SHR	$0x3,%RSI

0x500184 LEA	(%R14,%RAX,8),%RDI

0x500188 ADD	$0x38,%RDI

0x50018c XOR	%ECX,%ECX

0x50018e XCHG	%AX,%AX

(3259) 0x500190 XOR	%R8D,%R8D

(3259) 0x500193 CMPQ	$0,-0x38(%RDI)

(3259) 0x500198 SETG	%R8B

(3259) 0x50019c ADD	%RCX,%R8

(3259) 0x50019f XOR	%R9D,%R9D

(3259) 0x5001a2 CMPQ	$0,-0x30(%RDI)

(3259) 0x5001a7 SETG	%R9B

(3259) 0x5001ab XOR	%ECX,%ECX

(3259) 0x5001ad CMPQ	$0,-0x28(%RDI)

(3259) 0x5001b2 SETG	%CL

(3259) 0x5001b5 ADD	%R9,%RCX

(3259) 0x5001b8 ADD	%R8,%RCX

(3259) 0x5001bb XOR	%R8D,%R8D

(3259) 0x5001be CMPQ	$0,-0x20(%RDI)

(3259) 0x5001c3 SETG	%R8B

(3259) 0x5001c7 XOR	%R9D,%R9D

(3259) 0x5001ca CMPQ	$0,-0x18(%RDI)

(3259) 0x5001cf SETG	%R9B

(3259) 0x5001d3 ADD	%R8,%R9

(3259) 0x5001d6 XOR	%R8D,%R8D

(3259) 0x5001d9 CMPQ	$0,-0x10(%RDI)

(3259) 0x5001de SETG	%R8B

(3259) 0x5001e2 ADD	%R9,%R8

(3259) 0x5001e5 ADD	%RCX,%R8

(3259) 0x5001e8 XOR	%R9D,%R9D

(3259) 0x5001eb CMPQ	$0,-0x8(%RDI)

(3259) 0x5001f0 SETG	%R9B

(3259) 0x5001f4 XOR	%ECX,%ECX

(3259) 0x5001f6 CMPQ	$0,(%RDI)

(3259) 0x5001fa SETG	%CL

(3259) 0x5001fd ADD	%R9,%RCX

(3259) 0x500200 ADD	%R8,%RCX

(3259) 0x500203 ADD	$0x40,%RDI

(3259) 0x500207 DEC	%RSI

(3259) 0x50020a JNE	500190

0x50020c MOV	%EDX,%ESI

0x50020e AND	$0x7,%ESI

0x500211 DEC	%RSI

0x500214 CMP	$0x6,%RSI

0x500218 JA	5002ab

0x50021e AND	$-0x8,%RDX

0x500222 JMP	0x5d73f0(,%RSI,8)

0x500229 ADD	%RDX,%RAX

0x50022c JMP	50029e

0x50022e ADD	%RDX,%RAX

0x500231 JMP	500290

0x500233 ADD	%RDX,%RAX

0x500236 JMP	500282

0x500238 ADD	%RDX,%RAX

0x50023b JMP	500274

0x50023d ADD	%RDX,%RAX

0x500240 JMP	500266

0x500242 ADD	%RDX,%RAX

0x500245 JMP	500258

0x500247 ADD	%RDX,%RAX

0x50024a XOR	%EDX,%EDX

0x50024c CMPQ	$0,0x30(%R14,%RAX,8)

0x500252 SETG	%DL

0x500255 ADD	%RDX,%RCX

0x500258 XOR	%EDX,%EDX

0x50025a CMPQ	$0,0x28(%R14,%RAX,8)

0x500260 SETG	%DL

0x500263 ADD	%RDX,%RCX

0x500266 XOR	%EDX,%EDX

0x500268 CMPQ	$0,0x20(%R14,%RAX,8)

0x50026e SETG	%DL

0x500271 ADD	%RDX,%RCX

0x500274 XOR	%EDX,%EDX

0x500276 CMPQ	$0,0x18(%R14,%RAX,8)

0x50027c SETG	%DL

0x50027f ADD	%RDX,%RCX

0x500282 XOR	%EDX,%EDX

0x500284 CMPQ	$0,0x10(%R14,%RAX,8)

0x50028a SETG	%DL

0x50028d ADD	%RDX,%RCX

0x500290 XOR	%EDX,%EDX

0x500292 CMPQ	$0,0x8(%R14,%RAX,8)

0x500298 SETG	%DL

0x50029b ADD	%RDX,%RCX

0x50029e XOR	%EDX,%EDX

0x5002a0 CMPQ	$0,(%R14,%RAX,8)

0x5002a5 SETG	%DL

0x5002a8 ADD	%RDX,%RCX

0x5002ab MOV	%RCX,-0x28(%RBP)

0x5002af LEA	-0x28(%RBP),%RDI

0x5002b3 MOV	%R15,%RSI

0x5002b6 MOV	%R12,%RDX

0x5002b9 CALL	41dbc0 <@plt>

0x5002be MOV	-0x30(%RBP),%RAX

0x5002c2 MOV	-0x38(%RBP),%RCX

0x5002c6 MOV	%RCX,%RDI

0x5002c9 SUB	%RAX,%RDI

0x5002cc JLE	5003fa

0x5002d2 MOV	0x18(%RBP),%RDX

0x5002d6 MOV	-0x28(%RBP),%RSI

0x5002da CMP	$0x4,%RDI

0x5002de JB	5003be

0x5002e4 MOV	%RDI,%R8

0x5002e7 SHR	$0x2,%R8

0x5002eb LEA	0x3(%RAX),%R9

0x5002ef JMP	500315

0x5002f1 NOPW	%CS:(%RAX,%RAX,1)

(3258) 0x500300 MOVQ	$-0x1,(%RBX,%R9,8)

(3258) 0x500308 ADD	$0x4,%R9

(3258) 0x50030c DEC	%R8

(3258) 0x50030f JE	5003be

(3258) 0x500315 CMPQ	$0,-0x18(%R14,%R9,8)

(3258) 0x50031b JLE	500370

(3258) 0x50031d LEA	-0x3(%R9),%R10

(3258) 0x500321 MOV	%RSI,-0x18(%RBX,%R9,8)

(3258) 0x500326 MOV	%R10,(%RDX,%RSI,8)

(3258) 0x50032a INC	%RSI

(3258) 0x50032d CMPQ	$0,-0x10(%R14,%R9,8)

(3258) 0x500333 JLE	500381

(3258) 0x500335 LEA	-0x2(%R9),%R10

(3258) 0x500339 MOV	%RSI,-0x10(%RBX,%R9,8)

(3258) 0x50033e MOV	%R10,(%RDX,%RSI,8)

(3258) 0x500342 INC	%RSI

(3258) 0x500345 CMPQ	$0,-0x8(%R14,%R9,8)

(3258) 0x50034b JLE	500392

(3258) 0x50034d LEA	-0x1(%R9),%R10

(3258) 0x500351 MOV	%RSI,-0x8(%RBX,%R9,8)

(3258) 0x500356 MOV	%R10,(%RDX,%RSI,8)

(3258) 0x50035a INC	%RSI

(3258) 0x50035d CMPQ	$0,(%R14,%R9,8)

(3258) 0x500362 JG	5003a6

(3258) 0x500364 JMP	500300

0x500366 NOPW	%CS:(%RAX,%RAX,1)

(3258) 0x500370 MOVQ	$-0x1,-0x18(%RBX,%R9,8)

(3258) 0x500379 CMPQ	$0,-0x10(%R14,%R9,8)

(3258) 0x50037f JG	500335

(3258) 0x500381 MOVQ	$-0x1,-0x10(%RBX,%R9,8)

(3258) 0x50038a CMPQ	$0,-0x8(%R14,%R9,8)

(3258) 0x500390 JG	50034d

(3258) 0x500392 MOVQ	$-0x1,-0x8(%RBX,%R9,8)

(3258) 0x50039b CMPQ	$0,(%R14,%R9,8)

(3258) 0x5003a0 JLE	500300

(3258) 0x5003a6 MOV	%RSI,(%RBX,%R9,8)

(3258) 0x5003aa MOV	%R9,(%RDX,%RSI,8)

(3258) 0x5003ae INC	%RSI

(3258) 0x5003b1 ADD	$0x4,%R9

(3258) 0x5003b5 DEC	%R8

(3258) 0x5003b8 JNE	500315

0x5003be MOV	%RDI,%R8

0x5003c1 AND	$-0x4,%R8

0x5003c5 CMP	%RDI,%R8

0x5003c8 JAE	5003fa

0x5003ca ADD	%R8,%RAX

0x5003cd JMP	5003e0

0x5003cf NOP

(3257) 0x5003d0 MOVQ	$-0x1,(%RBX,%RAX,8)

(3257) 0x5003d8 INC	%RAX

(3257) 0x5003db CMP	%RAX,%RCX

(3257) 0x5003de JE	5003fa

(3257) 0x5003e0 CMPQ	$0,(%R14,%RAX,8)

(3257) 0x5003e5 JLE	5003d0

(3257) 0x5003e7 MOV	%RSI,(%RBX,%RAX,8)

(3257) 0x5003eb MOV	%RAX,(%RDX,%RSI,8)

(3257) 0x5003ef INC	%RSI

(3257) 0x5003f2 INC	%RAX

(3257) 0x5003f5 CMP	%RAX,%RCX

(3257) 0x5003f8 JNE	5003e0

0x5003fa ADD	$0x20,%RSP

0x5003fe POP	%RBX

0x5003ff POP	%R12

0x500401 POP	%R14

0x500403 POP	%R15

0x500405 POP	%RBP

0x500406 RET

0x500407 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►97.10+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.90+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGCreate2ndS	par_strength.c:1253	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:617	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1259-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 14.00 to 1.10 cycles (12.76x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1261

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	114
nb uops	112
loop length	390
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.50	11.50	11.50	11.50	11.50	11.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.50	11.50	11.50	11.50	11.50	11.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	11.50
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

3% of peak load performance is reached (8.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.00 to 11.50 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 500130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x30(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 41d3a0 <@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 500176 <hypre_BoomerAMGCreate2ndS.extracted+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 50017d <hypre_BoomerAMGCreate2ndS.extracted+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 50020c <hypre_BoomerAMGCreate2ndS.extracted+0xdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 5002ab <hypre_BoomerAMGCreate2ndS.extracted+0x17b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R14,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x38,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 5002ab <hypre_BoomerAMGCreate2ndS.extracted+0x17b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x5d73f0(,%RSI,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 50029e <hypre_BoomerAMGCreate2ndS.extracted+0x16e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500290 <hypre_BoomerAMGCreate2ndS.extracted+0x160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500282 <hypre_BoomerAMGCreate2ndS.extracted+0x152>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500274 <hypre_BoomerAMGCreate2ndS.extracted+0x144>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500266 <hypre_BoomerAMGCreate2ndS.extracted+0x136>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500258 <hypre_BoomerAMGCreate2ndS.extracted+0x128>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x30(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x28(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x20(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x18(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x10(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x8(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA -0x28(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 41dbc0 <@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 5003fa <hypre_BoomerAMGCreate2ndS.extracted+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 5003be <hypre_BoomerAMGCreate2ndS.extracted+0x28e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x3(%RAX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
JMP 500315 <hypre_BoomerAMGCreate2ndS.extracted+0x1e5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 5003fa <hypre_BoomerAMGCreate2ndS.extracted+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 5003e0 <hypre_BoomerAMGCreate2ndS.extracted+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253,1259-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1259
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1266

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1261

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	114
nb uops	112
loop length	390
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.50	11.50	11.50	11.50	11.50	11.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	11.50	11.50	11.50	11.50	11.50	11.50	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.00
Dispatch	11.50
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

3% of peak load performance is reached (8.57 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 500130

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
LEA -0x30(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 41d3a0 <@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 500176 <hypre_BoomerAMGCreate2ndS.extracted+0x46>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 50017d <hypre_BoomerAMGCreate2ndS.extracted+0x4d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 50020c <hypre_BoomerAMGCreate2ndS.extracted+0xdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 5002ab <hypre_BoomerAMGCreate2ndS.extracted+0x17b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%RSI	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
LEA (%R14,%RAX,8),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD $0x38,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $0x7,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x6,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 5002ab <hypre_BoomerAMGCreate2ndS.extracted+0x17b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
AND $-0x8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x5d73f0(,%RSI,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 50029e <hypre_BoomerAMGCreate2ndS.extracted+0x16e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500290 <hypre_BoomerAMGCreate2ndS.extracted+0x160>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500282 <hypre_BoomerAMGCreate2ndS.extracted+0x152>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500274 <hypre_BoomerAMGCreate2ndS.extracted+0x144>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500266 <hypre_BoomerAMGCreate2ndS.extracted+0x136>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 500258 <hypre_BoomerAMGCreate2ndS.extracted+0x128>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x30(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x28(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x20(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x18(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x10(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,0x8(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
CMPQ $0,(%R14,%RAX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
SETG %DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA -0x28(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CALL 41dbc0 <@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 5003fa <hypre_BoomerAMGCreate2ndS.extracted+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 5003be <hypre_BoomerAMGCreate2ndS.extracted+0x28e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
SHR $0x2,%R8	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
LEA 0x3(%RAX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
JMP 500315 <hypre_BoomerAMGCreate2ndS.extracted+0x1e5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMP %RDI,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 5003fa <hypre_BoomerAMGCreate2ndS.extracted+0x2ca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JMP 5003e0 <hypre_BoomerAMGCreate2ndS.extracted+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.extracted–	0.02	0.01
○Loop 3258 - par_strength.c:1268-1278 - exec	0.02	0.01
○Loop 3259 - par_strength.c:1261-1263 - exec	0.01	0.00
○Loop 3257 - par_strength.c:1268-1278 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code