OV - exec - Function hypre_BoomerAMGBuildMultipass.extracted.27

	Function: hypre_BoomerAMGBuildMultipass.extracted.27	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.41% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x46cfc0 PUSH	%RBP

0x46cfc1 MOV	%RSP,%RBP

0x46cfc4 PUSH	%R15

0x46cfc6 PUSH	%R14

0x46cfc8 PUSH	%R13

0x46cfca PUSH	%R12

0x46cfcc PUSH	%RBX

0x46cfcd SUB	$0xe8,%RSP

0x46cfd4 MOV	%R9,-0x88(%RBP)

0x46cfdb MOV	%R8,-0x98(%RBP)

0x46cfe2 MOV	%RCX,-0xa8(%RBP)

0x46cfe9 MOV	%RDX,-0x48(%RBP)

0x46cfed MOV	0xe8(%RBP),%RAX

0x46cff4 MOV	%RAX,-0x58(%RBP)

0x46cff8 MOV	0xe0(%RBP),%RAX

0x46cfff MOV	%RAX,-0x100(%RBP)

0x46d006 MOV	0xd8(%RBP),%RDI

0x46d00d MOV	0xd0(%RBP),%RAX

0x46d014 MOV	%RAX,-0x108(%RBP)

0x46d01b MOV	0xc8(%RBP),%RAX

0x46d022 MOV	%RAX,-0xf8(%RBP)

0x46d029 MOV	0xc0(%RBP),%RAX

0x46d030 MOV	%RAX,-0xc0(%RBP)

0x46d037 MOV	0xb8(%RBP),%RAX

0x46d03e MOV	%RAX,-0xb8(%RBP)

0x46d045 MOV	0xb0(%RBP),%RAX

0x46d04c MOV	%RAX,-0xd8(%RBP)

0x46d053 MOV	0xa8(%RBP),%RAX

0x46d05a MOV	%RAX,-0xd0(%RBP)

0x46d061 MOV	0xa0(%RBP),%RAX

0x46d068 MOV	%RAX,-0x68(%RBP)

0x46d06c MOV	0x98(%RBP),%RAX

0x46d073 MOV	%RAX,-0xc8(%RBP)

0x46d07a MOV	0x90(%RBP),%RBX

0x46d081 MOV	0x88(%RBP),%R15

0x46d088 MOV	0x80(%RBP),%RAX

0x46d08f MOV	%RAX,-0xe0(%RBP)

0x46d096 MOV	0x78(%RBP),%RAX

0x46d09a MOV	%RAX,-0x110(%RBP)

0x46d0a1 MOV	0x70(%RBP),%RAX

0x46d0a5 MOV	%RAX,-0xf0(%RBP)

0x46d0ac MOV	0x68(%RBP),%RAX

0x46d0b0 MOV	%RAX,-0x78(%RBP)

0x46d0b4 MOV	0x60(%RBP),%RAX

0x46d0b8 MOV	%RAX,-0x38(%RBP)

0x46d0bc MOV	0x58(%RBP),%RAX

0x46d0c0 MOV	%RAX,-0xe8(%RBP)

0x46d0c7 MOV	0x50(%RBP),%RAX

0x46d0cb MOV	%RAX,-0x70(%RBP)

0x46d0cf MOV	0x48(%RBP),%RAX

0x46d0d3 MOV	%RAX,-0x30(%RBP)

0x46d0d7 MOV	0x40(%RBP),%RCX

0x46d0db MOV	0x38(%RBP),%RAX

0x46d0df MOV	%RAX,-0xb0(%RBP)

0x46d0e6 MOV	0x30(%RBP),%RAX

0x46d0ea MOV	%RAX,-0x90(%RBP)

0x46d0f1 MOV	0x28(%RBP),%RAX

0x46d0f5 MOV	%RAX,-0xa0(%RBP)

0x46d0fc MOV	0x20(%RBP),%RAX

0x46d100 MOV	%RAX,-0x50(%RBP)

0x46d104 MOV	0x18(%RBP),%RAX

0x46d108 MOV	%RAX,-0x80(%RBP)

0x46d10c MOV	0x10(%RBP),%R12

0x46d110 TEST	%RDI,%RDI

0x46d113 MOV	%RCX,-0x40(%RBP)

0x46d117 MOV	%RDI,-0x60(%RBP)

0x46d11b JE	46d1ae

0x46d121 MOV	$0x8,%ESI

0x46d126 CALL	5a8860 <hypre_CAlloc>

0x46d12b MOV	-0x40(%RBP),%RCX

0x46d12f MOV	%RAX,%R13

0x46d132 TEST	%RCX,%RCX

0x46d135 JE	46d1b6

0x46d137 MOV	$0x8,%ESI

0x46d13c MOV	%RCX,%RDI

0x46d13f CALL	5a8860 <hypre_CAlloc>

0x46d144 MOV	%RAX,%R14

0x46d147 MOV	-0x60(%RBP),%RDX

0x46d14b TEST	%RDX,%RDX

0x46d14e JLE	46d161

0x46d150 SAL	$0x3,%RDX

0x46d154 MOV	%R13,%RDI

0x46d157 MOV	$0xff,%ESI

0x46d15c CALL	5b5350 <_intel_fast_memset>

0x46d161 MOV	-0x40(%RBP),%RDX

0x46d165 TEST	%RDX,%RDX

0x46d168 JLE	46d17b

0x46d16a SAL	$0x3,%RDX

0x46d16e MOV	%R14,%RDI

0x46d171 MOV	$0xff,%ESI

0x46d176 CALL	5b5350 <_intel_fast_memset>

0x46d17b CALL	5ac1c0 <hypre_GetThreadNum>

0x46d180 MOV	%RAX,-0x40(%RBP)

0x46d184 CALL	5ac1b0 <hypre_NumActiveThreads>

0x46d189 MOV	%RAX,%RCX

0x46d18c MOV	-0x68(%RBP),%RAX

0x46d190 MOV	0x8(%RAX),%RDI

0x46d194 MOV	-0x58(%RBP),%R8

0x46d198 MOV	%R8,%RAX

0x46d19b OR	%RCX,%RAX

0x46d19e SHR	$0x20,%RAX

0x46d1a2 JE	46d1c4

0x46d1a4 MOV	%R8,%RAX

0x46d1a7 CQTO

0x46d1a9 IDIV	%RCX

0x46d1ac JMP	46d1cb

0x46d1ae XOR	%R13D,%R13D

0x46d1b1 TEST	%RCX,%RCX

0x46d1b4 JNE	46d137

0x46d1b6 XOR	%R14D,%R14D

0x46d1b9 MOV	-0x60(%RBP),%RDX

0x46d1bd TEST	%RDX,%RDX

0x46d1c0 JG	46d150

0x46d1c2 JMP	46d161

0x46d1c4 MOV	%R8D,%EAX

0x46d1c7 XOR	%EDX,%EDX

0x46d1c9 DIV	%ECX

0x46d1cb MOV	-0x48(%RBP),%R11

0x46d1cf MOV	-0x50(%RBP),%R10

0x46d1d3 MOV	%RAX,%RDX

0x46d1d6 MOV	-0x40(%RBP),%R9

0x46d1da IMUL	%R9,%RDX

0x46d1de DEC	%RCX

0x46d1e1 LEA	0x1(%R9),%RSI

0x46d1e5 IMUL	%RAX,%RSI

0x46d1e9 CMP	%RCX,%R9

0x46d1ec CMOVE	%R8,%RSI

0x46d1f0 MOV	%RSI,-0x58(%RBP)

0x46d1f4 CMP	%RSI,%RDX

0x46d1f7 JGE	46d931

0x46d1fd ADD	%RDI,-0x58(%RBP)

0x46d201 ADD	%RDI,%RDX

0x46d204 MOV	-0x30(%RBP),%RAX

0x46d208 ADD	$0x38,%RAX

0x46d20c MOV	%RAX,-0x68(%RBP)

0x46d210 MOV	-0x38(%RBP),%RAX

0x46d214 ADD	$0x38,%RAX

0x46d218 MOV	%RAX,-0x60(%RBP)

0x46d21c XORPD	%XMM0,%XMM0

0x46d220 MOVAPD	0x157ed8(%RIP),%XMM1

0x46d228 JMP	46d2af

0x46d22d ADD	%R9,%RDI

0x46d230 MOV	-0x38(%RBP),%RAX

0x46d234 MOVSD	0x30(%RAX,%RDI,8),%XMM3

0x46d23a MULSD	%XMM2,%XMM3

0x46d23e MOVSD	%XMM3,0x30(%RAX,%RDI,8)

0x46d244 MOVSD	0x28(%RAX,%RDI,8),%XMM3

0x46d24a MULSD	%XMM2,%XMM3

0x46d24e MOVSD	%XMM3,0x28(%RAX,%RDI,8)

0x46d254 MOVSD	0x20(%RAX,%RDI,8),%XMM3

0x46d25a MULSD	%XMM2,%XMM3

0x46d25e MOVSD	%XMM3,0x20(%RAX,%RDI,8)

0x46d264 MOVSD	0x18(%RAX,%RDI,8),%XMM3

0x46d26a MULSD	%XMM2,%XMM3

0x46d26e MOVSD	%XMM3,0x18(%RAX,%RDI,8)

0x46d274 MOVSD	0x10(%RAX,%RDI,8),%XMM3

0x46d27a MULSD	%XMM2,%XMM3

0x46d27e MOVSD	%XMM3,0x10(%RAX,%RDI,8)

0x46d284 MOVSD	0x8(%RAX,%RDI,8),%XMM3

0x46d28a MULSD	%XMM2,%XMM3

0x46d28e MOVSD	%XMM3,0x8(%RAX,%RDI,8)

0x46d294 MOVSD	(%RAX,%RDI,8),%XMM3

0x46d299 MULSD	%XMM2,%XMM3

0x46d29d MOVSD	%XMM3,(%RAX,%RDI,8)

(1118) 0x46d2a2 INC	%RDX

(1118) 0x46d2a5 CMP	-0x58(%RBP),%RDX

(1118) 0x46d2a9 JGE	46d931

(1118) 0x46d2af MOV	-0xc8(%RBP),%RAX

(1118) 0x46d2b6 MOV	%RDX,-0x40(%RBP)

(1118) 0x46d2ba MOV	(%RAX,%RDX,8),%RDI

(1118) 0x46d2be MOV	-0xd0(%RBP),%RAX

(1118) 0x46d2c5 MOV	(%RAX,%RDI,8),%R8

(1118) 0x46d2c9 MOV	-0x70(%RBP),%RAX

(1118) 0x46d2cd MOV	(%RAX,%RDI,8),%RCX

(1118) 0x46d2d1 MOV	0x8(%RAX,%RDI,8),%RAX

(1118) 0x46d2d6 LEA	(%RAX,%R8,1),%R9

(1118) 0x46d2da SUB	%RCX,%R9

(1118) 0x46d2dd CMP	%R9,%R8

(1118) 0x46d2e0 JGE	46d3b5

(1118) 0x46d2e6 MOV	-0xb8(%RBP),%RDX

(1118) 0x46d2ed MOV	0x8(%RDX),%R9

(1118) 0x46d2f1 SUB	%RCX,%RAX

(1118) 0x46d2f4 CMP	$0x8,%RAX

(1118) 0x46d2f8 JB	46d380

(1118) 0x46d2fe MOV	%RAX,%R10

(1118) 0x46d301 SHR	$0x3,%R10

(1118) 0x46d305 LEA	(%R9,%R8,8),%R11

(1118) 0x46d309 ADD	$0x38,%R11

(1118) 0x46d30d NOPL	(%RAX)

  (1126) 0x46d310 MOV	-0x38(%R11),%RCX

  (1126) 0x46d314 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d318 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d31d MOV	-0x30(%R11),%RCX

  (1126) 0x46d321 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d325 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d32a MOV	-0x28(%R11),%RCX

  (1126) 0x46d32e MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d332 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d337 MOV	-0x20(%R11),%RCX

  (1126) 0x46d33b MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d33f MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d344 MOV	-0x18(%R11),%RCX

  (1126) 0x46d348 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d34c MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d351 MOV	-0x10(%R11),%RCX

  (1126) 0x46d355 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d359 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d35e MOV	-0x8(%R11),%RCX

  (1126) 0x46d362 MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d366 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d36b MOV	(%R11),%RCX

  (1126) 0x46d36e MOV	(%R15,%RCX,8),%RCX

  (1126) 0x46d372 MOV	%RDI,(%R13,%RCX,8)

  (1126) 0x46d377 ADD	$0x40,%R11

  (1126) 0x46d37b DEC	%R10

  (1126) 0x46d37e JNE	46d310

(1118) 0x46d380 MOV	%RAX,%RCX

(1118) 0x46d383 AND	$-0x8,%RCX

(1118) 0x46d387 CMP	%RAX,%RCX

(1118) 0x46d38a MOV	-0x48(%RBP),%R11

(1118) 0x46d38e MOV	-0x50(%RBP),%R10

(1118) 0x46d392 JAE	46d3b5

(1118) 0x46d394 LEA	(%R9,%R8,8),%R8

(1118) 0x46d398 NOPL	(%RAX,%RAX,1)

  (1125) 0x46d3a0 MOV	(%R8,%RCX,8),%RSI

  (1125) 0x46d3a4 MOV	(%R15,%RSI,8),%RSI

  (1125) 0x46d3a8 MOV	%RDI,(%R13,%RSI,8)

  (1125) 0x46d3ad INC	%RCX

  (1125) 0x46d3b0 CMP	%RCX,%RAX

  (1125) 0x46d3b3 JNE	46d3a0

(1118) 0x46d3b5 MOV	-0x70(%RBP),%RAX

(1118) 0x46d3b9 MOV	(%RAX,%RDI,8),%R8

(1118) 0x46d3bd MOV	-0x80(%RBP),%RCX

(1118) 0x46d3c1 MOV	(%RCX,%RDI,8),%RAX

(1118) 0x46d3c5 MOV	0x8(%RCX,%RDI,8),%R9

(1118) 0x46d3ca INC	%RAX

(1118) 0x46d3cd XORPD	%XMM4,%XMM4

(1118) 0x46d3d1 XORPD	%XMM3,%XMM3

(1118) 0x46d3d5 JMP	46d3e3

0x46d3d7 NOPW	(%RAX,%RAX,1)

  (1124) 0x46d3e0 INC	%RAX

  (1124) 0x46d3e3 CMP	%R9,%RAX

  (1124) 0x46d3e6 JGE	46d460

  (1124) 0x46d3e8 MOV	(%R10,%RAX,8),%RCX

  (1124) 0x46d3ec CMPQ	$-0x3,(%R11,%RCX,8)

  (1124) 0x46d3f1 JE	46d418

  (1124) 0x46d3f3 CMPQ	$0x1,-0xa8(%RBP)

  (1124) 0x46d3fb JE	46d412

  (1124) 0x46d3fd MOV	-0x98(%RBP),%RSI

  (1124) 0x46d404 MOV	(%RSI,%RDI,8),%R10

  (1124) 0x46d408 CMP	(%RSI,%RCX,8),%R10

  (1124) 0x46d40c MOV	-0x50(%RBP),%R10

  (1124) 0x46d410 JNE	46d418

  (1124) 0x46d412 ADDSD	(%R12,%RAX,8),%XMM3

  (1124) 0x46d418 CMP	$-0x1,%RCX

  (1124) 0x46d41c JE	46d3e0

  (1124) 0x46d41e CMP	%RDI,(%R13,%RCX,8)

  (1124) 0x46d423 JNE	46d3e0

  (1124) 0x46d425 MOVSD	(%R12,%RAX,8),%XMM5

  (1124) 0x46d42b MOV	-0x30(%RBP),%RDX

  (1124) 0x46d42f MOVSD	%XMM5,(%RDX,%R8,8)

  (1124) 0x46d435 MOV	-0x100(%RBP),%RSI

  (1124) 0x46d43c MOV	(%RSI,%RCX,8),%RCX

  (1124) 0x46d440 MOV	-0xe8(%RBP),%RDX

  (1124) 0x46d447 MOV	%RCX,(%RDX,%R8,8)

  (1124) 0x46d44b INC	%R8

  (1124) 0x46d44e ADDSD	(%R12,%RAX,8),%XMM4

  (1124) 0x46d454 MOV	-0x80(%RBP),%RCX

  (1124) 0x46d458 MOV	0x8(%RCX,%RDI,8),%R9

  (1124) 0x46d45d JMP	46d3e0

0x46d45f NOP

(1118) 0x46d460 MOV	-0xd8(%RBP),%RAX

(1118) 0x46d467 MOV	(%RAX,%RDI,8),%R9

(1118) 0x46d46b MOV	-0x78(%RBP),%RAX

(1118) 0x46d46f MOV	(%RAX,%RDI,8),%RCX

(1118) 0x46d473 MOV	0x8(%RAX,%RDI,8),%RAX

(1118) 0x46d478 LEA	(%RAX,%R9,1),%R10

(1118) 0x46d47c SUB	%RCX,%R10

(1118) 0x46d47f CMP	%R10,%R9

(1118) 0x46d482 JGE	46d544

(1118) 0x46d488 MOV	-0xc0(%RBP),%RDX

(1118) 0x46d48f MOV	0x8(%RDX),%R10

(1118) 0x46d493 SUB	%RCX,%RAX

(1118) 0x46d496 CMP	$0x8,%RAX

(1118) 0x46d49a JB	46d518

(1118) 0x46d4a0 MOV	%RAX,%R11

(1118) 0x46d4a3 SHR	$0x3,%R11

(1118) 0x46d4a7 LEA	(%R10,%R9,8),%RCX

(1118) 0x46d4ab ADD	$0x38,%RCX

(1118) 0x46d4af NOP

  (1123) 0x46d4b0 MOV	-0x38(%RCX),%RSI

  (1123) 0x46d4b4 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4b8 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4bc MOV	-0x30(%RCX),%RSI

  (1123) 0x46d4c0 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4c4 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4c8 MOV	-0x28(%RCX),%RSI

  (1123) 0x46d4cc MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4d0 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4d4 MOV	-0x20(%RCX),%RSI

  (1123) 0x46d4d8 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4dc MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4e0 MOV	-0x18(%RCX),%RSI

  (1123) 0x46d4e4 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4e8 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4ec MOV	-0x10(%RCX),%RSI

  (1123) 0x46d4f0 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d4f4 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d4f8 MOV	-0x8(%RCX),%RSI

  (1123) 0x46d4fc MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d500 MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d504 MOV	(%RCX),%RSI

  (1123) 0x46d507 MOV	(%RBX,%RSI,8),%RSI

  (1123) 0x46d50b MOV	%RDI,(%R14,%RSI,8)

  (1123) 0x46d50f ADD	$0x40,%RCX

  (1123) 0x46d513 DEC	%R11

  (1123) 0x46d516 JNE	46d4b0

(1118) 0x46d518 MOV	%RAX,%RCX

(1118) 0x46d51b AND	$-0x8,%RCX

(1118) 0x46d51f CMP	%RAX,%RCX

(1118) 0x46d522 JAE	46d544

(1118) 0x46d524 LEA	(%R10,%R9,8),%R9

(1118) 0x46d528 NOPL	(%RAX,%RAX,1)

  (1122) 0x46d530 MOV	(%R9,%RCX,8),%RSI

  (1122) 0x46d534 MOV	(%RBX,%RSI,8),%RSI

  (1122) 0x46d538 MOV	%RDI,(%R14,%RSI,8)

  (1122) 0x46d53c INC	%RCX

  (1122) 0x46d53f CMP	%RCX,%RAX

  (1122) 0x46d542 JNE	46d530

(1118) 0x46d544 MOV	-0x78(%RBP),%RAX

(1118) 0x46d548 MOV	(%RAX,%RDI,8),%R9

(1118) 0x46d54c MOV	-0x90(%RBP),%RAX

(1118) 0x46d553 MOV	(%RAX,%RDI,8),%R10

(1118) 0x46d557 MOV	0x8(%RAX,%RDI,8),%RAX

(1118) 0x46d55c CMP	%RAX,%R10

(1118) 0x46d55f JGE	46d640

(1118) 0x46d565 MOV	-0xb0(%RBP),%RCX

(1118) 0x46d56c LEA	(%RCX,%R10,8),%R11

(1118) 0x46d570 MOV	-0x88(%RBP),%RSI

(1118) 0x46d577 JMP	46d590

0x46d579 NOPL	(%RAX)

  (1121) 0x46d580 INC	%R10

  (1121) 0x46d583 ADD	$0x8,%R11

  (1121) 0x46d587 CMP	%RAX,%R10

  (1121) 0x46d58a JGE	46d640

  (1121) 0x46d590 MOV	%R11,%RCX

  (1121) 0x46d593 TEST	%RSI,%RSI

  (1121) 0x46d596 JE	46d5a6

  (1121) 0x46d598 MOV	(%R11),%RCX

  (1121) 0x46d59b MOV	-0x108(%RBP),%RDX

  (1121) 0x46d5a2 LEA	(%RDX,%RCX,8),%RCX

  (1121) 0x46d5a6 MOV	(%RCX),%RCX

  (1121) 0x46d5a9 MOV	-0x110(%RBP),%RDX

  (1121) 0x46d5b0 CMPQ	$-0x3,(%RDX,%RCX,8)

  (1121) 0x46d5b5 JE	46d5ed

  (1121) 0x46d5b7 CMPQ	$0x1,-0xa8(%RBP)

  (1121) 0x46d5bf JE	46d5e0

  (1121) 0x46d5c1 MOV	-0x98(%RBP),%RSI

  (1121) 0x46d5c8 MOV	(%RSI,%RDI,8),%RSI

  (1121) 0x46d5cc MOV	-0xe0(%RBP),%RDX

  (1121) 0x46d5d3 CMP	(%RDX,%RCX,8),%RSI

  (1121) 0x46d5d7 MOV	-0x88(%RBP),%RSI

  (1121) 0x46d5de JNE	46d5ed

  (1121) 0x46d5e0 MOV	-0xa0(%RBP),%RDX

  (1121) 0x46d5e7 ADDSD	(%RDX,%R10,8),%XMM3

  (1121) 0x46d5ed CMP	$-0x1,%RCX

  (1121) 0x46d5f1 JE	46d580

  (1121) 0x46d5f3 CMP	%RDI,(%R14,%RCX,8)

  (1121) 0x46d5f7 JNE	46d580

  (1121) 0x46d5f9 MOV	-0xa0(%RBP),%RDX

  (1121) 0x46d600 MOVSD	(%RDX,%R10,8),%XMM5

  (1121) 0x46d606 MOV	-0x38(%RBP),%RAX

  (1121) 0x46d60a MOVSD	%XMM5,(%RAX,%R9,8)

  (1121) 0x46d610 MOV	-0xf8(%RBP),%RAX

  (1121) 0x46d617 MOV	(%RAX,%RCX,8),%RAX

  (1121) 0x46d61b MOV	-0xf0(%RBP),%RCX

  (1121) 0x46d622 MOV	%RAX,(%RCX,%R9,8)

  (1121) 0x46d626 INC	%R9

  (1121) 0x46d629 ADDSD	(%RDX,%R10,8),%XMM4

  (1121) 0x46d62f MOV	-0x90(%RBP),%RAX

  (1121) 0x46d636 MOV	0x8(%RAX,%RDI,8),%RAX

  (1121) 0x46d63b JMP	46d580

(1118) 0x46d640 MOV	-0x80(%RBP),%RAX

(1118) 0x46d644 MOV	(%RAX,%RDI,8),%RAX

(1118) 0x46d648 MULSD	(%R12,%RAX,8),%XMM4

(1118) 0x46d64e UCOMISD	%XMM0,%XMM4

(1118) 0x46d652 JE	46d660

(1118) 0x46d654 XORPD	%XMM1,%XMM3

(1118) 0x46d658 DIVSD	%XMM4,%XMM3

(1118) 0x46d65c MOVAPD	%XMM3,%XMM2

(1118) 0x46d660 MOV	-0x70(%RBP),%RAX

(1118) 0x46d664 MOV	(%RAX,%RDI,8),%R10

(1118) 0x46d668 SUB	%R10,%R8

(1118) 0x46d66b MOV	-0x48(%RBP),%R11

(1118) 0x46d66f MOV	-0x40(%RBP),%RDX

(1118) 0x46d673 JLE	46d80c

(1118) 0x46d679 CMP	$0x8,%R8

(1118) 0x46d67d JB	46d72b

(1118) 0x46d683 MOV	%R8,%RAX

(1118) 0x46d686 SHR	$0x3,%RAX

(1118) 0x46d68a MOV	-0x68(%RBP),%RCX

(1118) 0x46d68e LEA	(%RCX,%R10,8),%R11

(1118) 0x46d692 NOPW	%CS:(%RAX,%RAX,1)

  (1120) 0x46d6a0 MOVSD	-0x38(%R11),%XMM3

  (1120) 0x46d6a6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6aa MOVSD	%XMM3,-0x38(%R11)

  (1120) 0x46d6b0 MOVSD	-0x30(%R11),%XMM3

  (1120) 0x46d6b6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ba MOVSD	%XMM3,-0x30(%R11)

  (1120) 0x46d6c0 MOVSD	-0x28(%R11),%XMM3

  (1120) 0x46d6c6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ca MOVSD	%XMM3,-0x28(%R11)

  (1120) 0x46d6d0 MOVSD	-0x20(%R11),%XMM3

  (1120) 0x46d6d6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6da MOVSD	%XMM3,-0x20(%R11)

  (1120) 0x46d6e0 MOVSD	-0x18(%R11),%XMM3

  (1120) 0x46d6e6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6ea MOVSD	%XMM3,-0x18(%R11)

  (1120) 0x46d6f0 MOVSD	-0x10(%R11),%XMM3

  (1120) 0x46d6f6 MULSD	%XMM2,%XMM3

  (1120) 0x46d6fa MOVSD	%XMM3,-0x10(%R11)

  (1120) 0x46d700 MOVSD	-0x8(%R11),%XMM3

  (1120) 0x46d706 MULSD	%XMM2,%XMM3

  (1120) 0x46d70a MOVSD	%XMM3,-0x8(%R11)

  (1120) 0x46d710 MOVSD	(%R11),%XMM3

  (1120) 0x46d715 MULSD	%XMM2,%XMM3

  (1120) 0x46d719 MOVSD	%XMM3,(%R11)

  (1120) 0x46d71e ADD	$0x40,%R11

  (1120) 0x46d722 DEC	%RAX

  (1120) 0x46d725 JNE	46d6a0

(1118) 0x46d72b MOV	%R8D,%EAX

(1118) 0x46d72e AND	$0x7,%EAX

(1118) 0x46d731 DEC	%RAX

(1118) 0x46d734 CMP	$0x6,%RAX

(1118) 0x46d738 MOV	-0x48(%RBP),%R11

(1118) 0x46d73c JA	46d80c

0x46d742 AND	$-0x8,%R8

0x46d746 JMP	0x5ca5b0(,%RAX,8)

0x46d74d ADD	%R8,%R10

0x46d750 MOV	-0x30(%RBP),%RAX

0x46d754 JMP	46d7fc

0x46d759 ADD	%R8,%R10

0x46d75c MOV	-0x30(%RBP),%RAX

0x46d760 JMP	46d7ea

0x46d765 ADD	%R8,%R10

0x46d768 MOV	-0x30(%RBP),%RAX

0x46d76c JMP	46d7d8

0x46d76e ADD	%R8,%R10

0x46d771 MOV	-0x30(%RBP),%RAX

0x46d775 JMP	46d7c6

0x46d777 ADD	%R8,%R10

0x46d77a MOV	-0x30(%RBP),%RAX

0x46d77e JMP	46d7b4

0x46d780 ADD	%R8,%R10

0x46d783 MOV	-0x30(%RBP),%RAX

0x46d787 JMP	46d7a2

0x46d789 ADD	%R8,%R10

0x46d78c MOV	-0x30(%RBP),%RAX

0x46d790 MOVSD	0x30(%RAX,%R10,8),%XMM3

0x46d797 MULSD	%XMM2,%XMM3

0x46d79b MOVSD	%XMM3,0x30(%RAX,%R10,8)

0x46d7a2 MOVSD	0x28(%RAX,%R10,8),%XMM3

0x46d7a9 MULSD	%XMM2,%XMM3

0x46d7ad MOVSD	%XMM3,0x28(%RAX,%R10,8)

0x46d7b4 MOVSD	0x20(%RAX,%R10,8),%XMM3

0x46d7bb MULSD	%XMM2,%XMM3

0x46d7bf MOVSD	%XMM3,0x20(%RAX,%R10,8)

0x46d7c6 MOVSD	0x18(%RAX,%R10,8),%XMM3

0x46d7cd MULSD	%XMM2,%XMM3

0x46d7d1 MOVSD	%XMM3,0x18(%RAX,%R10,8)

0x46d7d8 MOVSD	0x10(%RAX,%R10,8),%XMM3

0x46d7df MULSD	%XMM2,%XMM3

0x46d7e3 MOVSD	%XMM3,0x10(%RAX,%R10,8)

0x46d7ea MOVSD	0x8(%RAX,%R10,8),%XMM3

0x46d7f1 MULSD	%XMM2,%XMM3

0x46d7f5 MOVSD	%XMM3,0x8(%RAX,%R10,8)

0x46d7fc MOVSD	(%RAX,%R10,8),%XMM3

0x46d802 MULSD	%XMM2,%XMM3

0x46d806 MOVSD	%XMM3,(%RAX,%R10,8)

(1118) 0x46d80c MOV	-0x78(%RBP),%RAX

(1118) 0x46d810 MOV	(%RAX,%RDI,8),%RDI

(1118) 0x46d814 SUB	%RDI,%R9

(1118) 0x46d817 MOV	-0x50(%RBP),%R10

(1118) 0x46d81b JLE	46d2a2

(1118) 0x46d821 CMP	$0x8,%R9

(1118) 0x46d825 JB	46d8cb

(1118) 0x46d82b MOV	%R9,%RAX

(1118) 0x46d82e SHR	$0x3,%RAX

(1118) 0x46d832 MOV	-0x60(%RBP),%RCX

(1118) 0x46d836 LEA	(%RCX,%RDI,8),%R8

(1118) 0x46d83a NOPW	(%RAX,%RAX,1)

  (1119) 0x46d840 MOVSD	-0x38(%R8),%XMM3

  (1119) 0x46d846 MULSD	%XMM2,%XMM3

  (1119) 0x46d84a MOVSD	%XMM3,-0x38(%R8)

  (1119) 0x46d850 MOVSD	-0x30(%R8),%XMM3

  (1119) 0x46d856 MULSD	%XMM2,%XMM3

  (1119) 0x46d85a MOVSD	%XMM3,-0x30(%R8)

  (1119) 0x46d860 MOVSD	-0x28(%R8),%XMM3

  (1119) 0x46d866 MULSD	%XMM2,%XMM3

  (1119) 0x46d86a MOVSD	%XMM3,-0x28(%R8)

  (1119) 0x46d870 MOVSD	-0x20(%R8),%XMM3

  (1119) 0x46d876 MULSD	%XMM2,%XMM3

  (1119) 0x46d87a MOVSD	%XMM3,-0x20(%R8)

  (1119) 0x46d880 MOVSD	-0x18(%R8),%XMM3

  (1119) 0x46d886 MULSD	%XMM2,%XMM3

  (1119) 0x46d88a MOVSD	%XMM3,-0x18(%R8)

  (1119) 0x46d890 MOVSD	-0x10(%R8),%XMM3

  (1119) 0x46d896 MULSD	%XMM2,%XMM3

  (1119) 0x46d89a MOVSD	%XMM3,-0x10(%R8)

  (1119) 0x46d8a0 MOVSD	-0x8(%R8),%XMM3

  (1119) 0x46d8a6 MULSD	%XMM2,%XMM3

  (1119) 0x46d8aa MOVSD	%XMM3,-0x8(%R8)

  (1119) 0x46d8b0 MOVSD	(%R8),%XMM3

  (1119) 0x46d8b5 MULSD	%XMM2,%XMM3

  (1119) 0x46d8b9 MOVSD	%XMM3,(%R8)

  (1119) 0x46d8be ADD	$0x40,%R8

  (1119) 0x46d8c2 DEC	%RAX

  (1119) 0x46d8c5 JNE	46d840

(1118) 0x46d8cb MOV	%R9D,%EAX

(1118) 0x46d8ce AND	$0x7,%EAX

(1118) 0x46d8d1 DEC	%RAX

(1118) 0x46d8d4 CMP	$0x6,%RAX

(1118) 0x46d8d8 JA	46d2a2

0x46d8de AND	$-0x8,%R9

0x46d8e2 JMP	0x5ca5e8(,%RAX,8)

0x46d8e9 ADD	%R9,%RDI

0x46d8ec MOV	-0x38(%RBP),%RAX

0x46d8f0 JMP	46d294

0x46d8f5 ADD	%R9,%RDI

0x46d8f8 MOV	-0x38(%RBP),%RAX

0x46d8fc JMP	46d284

0x46d901 ADD	%R9,%RDI

0x46d904 MOV	-0x38(%RBP),%RAX

0x46d908 JMP	46d274

0x46d90d ADD	%R9,%RDI

0x46d910 MOV	-0x38(%RBP),%RAX

0x46d914 JMP	46d264

0x46d919 ADD	%R9,%RDI

0x46d91c MOV	-0x38(%RBP),%RAX

0x46d920 JMP	46d254

0x46d925 ADD	%R9,%RDI

0x46d928 MOV	-0x38(%RBP),%RAX

0x46d92c JMP	46d244

0x46d931 MOV	%R13,%RDI

0x46d934 CALL	5a8930 <hypre_Free>

0x46d939 MOV	%R14,%RDI

0x46d93c ADD	$0xe8,%RSP

0x46d943 POP	%RBX

0x46d944 POP	%R12

0x46d946 POP	%R13

0x46d948 POP	%R14

0x46d94a POP	%R15

0x46d94c POP	%RBP

0x46d94d JMP	5a8930

0x46d952 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►97.02+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.91+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1575	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_5

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.50 to 7.25 cycles (4.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 31.50 to 3.14 cycles (10.03x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_intel_fast_memset: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
JMP: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1657
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1659

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

14: multiply

The binary function is loading 584 bytes (73 double precision FP elements). The binary function is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	242
nb uops	248
loop length	1087
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.00 cycles
front end	31.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.33	13.33	13.33	13.33	13.33	13.33	31.50	31.50	31.50	31.50	7.00	7.00	0.00	0.00	7.00	7.00
cycles	13.33	13.33	13.33	13.33	13.33	13.33	31.50	31.50	31.50	31.50	7.00	7.00	0.00	0.00	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

13.00-18.00

Cycles summary

Front-end	31.00
Dispatch	31.50
DIV/SQRT	13.00-18.00
Overall L1	31.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	4%
load	6%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	1%
load	3%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	13%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.50 cycles. At this rate:

7% of peak load performance is reached (18.54 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46cfc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 46d1ae <hypre_BoomerAMGBuildMultipass.extracted.27+0x1ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5a8860 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 46d1b6 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a8860 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46d161 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5b5350 <_intel_fast_memset>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46d17b <hypre_BoomerAMGBuildMultipass.extracted.27+0x1bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5b5350 <_intel_fast_memset>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 5ac1c0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5ac1b0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JE 46d1c4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x204>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
JMP 46d1cb <hypre_BoomerAMGBuildMultipass.extracted.27+0x20b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 46d137 <hypre_BoomerAMGBuildMultipass.extracted.27+0x177>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 46d150 <hypre_BoomerAMGBuildMultipass.extracted.27+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46d161 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
DIV %ECX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R9,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RAX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
CMP %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVE %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d931 <hypre_BoomerAMGBuildMultipass.extracted.27+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RDI,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x157ed8(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 46d2af <hypre_BoomerAMGBuildMultipass.extracted.27+0x2ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x30(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x30(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x28(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x28(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x20(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x18(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x18(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x10(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x8(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x5ca5b0(,%RAX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7fc <hypre_BoomerAMGBuildMultipass.extracted.27+0x83c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7ea <hypre_BoomerAMGBuildMultipass.extracted.27+0x82a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7d8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x818>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7c6 <hypre_BoomerAMGBuildMultipass.extracted.27+0x806>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7b4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x30(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x30(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x28(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x28(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x20(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x18(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x18(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x10(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x8(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
AND $-0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5ca5e8(,%RAX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d294 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d284 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2c4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d274 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d264 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d254 <hypre_BoomerAMGBuildMultipass.extracted.27+0x294>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d244 <hypre_BoomerAMGBuildMultipass.extracted.27+0x284>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a8930 <hypre_Free>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a8930 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_5

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.50 to 7.25 cycles (4.34x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

_intel_fast_memset: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1591
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593
hypre_CAlloc: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1586
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1589
hypre_Free: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1662
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1596
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1597

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598
JMP: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1657
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1659

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1598

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

14: multiply

The binary function is loading 584 bytes (73 double precision FP elements). The binary function is storing 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	242
nb uops	248
loop length	1087
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	57

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	31.00 cycles
front end	31.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.33	13.33	13.33	13.33	13.33	13.33	31.50	31.50	31.50	31.50	7.00	7.00	0.00	0.00	7.00	7.00
cycles	13.33	13.33	13.33	13.33	13.33	13.33	31.50	31.50	31.50	31.50	7.00	7.00	0.00	0.00	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

13.00-18.00

Cycles summary

Front-end	31.00
Dispatch	31.50
DIV/SQRT	13.00-18.00
Overall L1	31.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	4%
load	6%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	1%
load	3%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	4%

Vector efficiency ratios

INT

all	11%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	13%
load	13%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	9%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.50 cycles. At this rate:

7% of peak load performance is reached (18.54 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.19 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 46cfc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R9,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x100(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xd8(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x108(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xf8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xb0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x98(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x90(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x88(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xe0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x110(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDI,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JE 46d1ae <hypre_BoomerAMGBuildMultipass.extracted.27+0x1ee>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5a8860 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 46d1b6 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1f6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x8,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a8860 <hypre_CAlloc>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46d161 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5b5350 <_intel_fast_memset>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV -0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JLE 46d17b <hypre_BoomerAMGBuildMultipass.extracted.27+0x1bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0xff,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 5b5350 <_intel_fast_memset>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
CALL 5ac1c0 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 5ac1b0 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RAX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
OR %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x20,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JE 46d1c4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x204>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
JMP 46d1cb <hypre_BoomerAMGBuildMultipass.extracted.27+0x20b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
TEST %RCX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 46d137 <hypre_BoomerAMGBuildMultipass.extracted.27+0x177>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV -0x60(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 46d150 <hypre_BoomerAMGBuildMultipass.extracted.27+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 46d161 <hypre_BoomerAMGBuildMultipass.extracted.27+0x1a1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
DIV %ECX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV -0x48(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x50(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x40(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R9,%RDX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA 0x1(%R9),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
IMUL %RAX,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
CMP %RCX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVE %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RSI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 46d931 <hypre_BoomerAMGBuildMultipass.extracted.27+0x971>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
ADD %RDI,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
ADD %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x38,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x157ed8(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
JMP 46d2af <hypre_BoomerAMGBuildMultipass.extracted.27+0x2ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x30(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x30(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x28(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x28(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x20(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x18(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x18(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x10(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x8(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RAX,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,(%RAX,%RDI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
AND $-0x8,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 0x5ca5b0(,%RAX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7fc <hypre_BoomerAMGBuildMultipass.extracted.27+0x83c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7ea <hypre_BoomerAMGBuildMultipass.extracted.27+0x82a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7d8 <hypre_BoomerAMGBuildMultipass.extracted.27+0x818>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7c6 <hypre_BoomerAMGBuildMultipass.extracted.27+0x806>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7b4 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d7a2 <hypre_BoomerAMGBuildMultipass.extracted.27+0x7e2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVSD 0x30(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x30(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x28(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x28(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x20(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x20(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x18(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x18(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x10(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x10(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD 0x8(%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,0x8(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOVSD (%RAX,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MULSD %XMM2,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOVSD %XMM3,(%RAX,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
AND $-0x8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5ca5e8(,%RAX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d294 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2d4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d284 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2c4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d274 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2b4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d264 <hypre_BoomerAMGBuildMultipass.extracted.27+0x2a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d254 <hypre_BoomerAMGBuildMultipass.extracted.27+0x294>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R9,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 46d244 <hypre_BoomerAMGBuildMultipass.extracted.27+0x284>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 5a8930 <hypre_Free>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0xe8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 5a8930 <hypre_Free>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.extracted.27–	0.41	0.21
▼Loop 1118 - par_multi_interp.c:1585-1660 - exec–	0.10	0.05
○Loop 1124 - par_multi_interp.c:1618-1628 - exec	0.29	0.14
○Loop 1125 - par_multi_interp.c:1612-1615 - exec	0.01	0.01
○Loop 1121 - par_multi_interp.c:1622-1652 - exec	0.00	0.01
○Loop 1126 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 1122 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 1119 - par_multi_interp.c:1585-1660 - exec	0.00	0.00
○Loop 1120 - par_multi_interp.c:1585-1658 - exec	0.00	0.00
○Loop 1123 - par_multi_interp.c:1633-1636 - exec	0.00	0.00

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