OV - exec - Function hypre

	Function: hypre_Rand	Module: exec	Source: random.c:76-115 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c: 76 - 115

--------------------------------------------------------------------------------

76:    high = Seed / q;

77:    low = Seed % q;

78:    test = a * low - r * high;

79:    if(test > 0)

[...]

99: {

[...]

115:    return ((HYPRE_Real)(hypre_RandI()) / m);

0x5ac120 PUSH	%RBP

0x5ac121 MOV	%RSP,%RBP

0x5ac124 MOV	0x5fb7d(%RIP),%RCX

0x5ac12b MOV	$0x41a705af1fe3fb79,%RDX

0x5ac135 MOV	%RCX,%RAX

0x5ac138 IMUL	%RDX

0x5ac13b MOV	%RDX,%RAX

0x5ac13e SHR	$0x3f,%RAX

0x5ac142 SAR	$0xf,%RDX

0x5ac146 ADD	%RAX,%RDX

0x5ac149 IMUL	$0x1f31d,%RDX,%RAX

0x5ac150 SUB	%RAX,%RCX

0x5ac153 IMUL	$0x41a7,%RCX,%RAX

0x5ac15a IMUL	$-0xb14,%RDX,%RCX

0x5ac161 LEA	(%RCX,%RAX,1),%RDX

0x5ac165 TEST	%RDX,%RDX

0x5ac168 LEA	0x7fffffff(%RCX,%RAX,1),%RAX

0x5ac170 CMOVG	%RDX,%RAX

0x5ac174 CVTSI2SD	%RAX,%XMM0

0x5ac179 MOV	%RAX,0x5fb28(%RIP)

0x5ac180 MULSD	0x37d98(%RIP),%XMM0

0x5ac188 POP	%RBP

0x5ac189 RET

0x5ac18a NOPW	%CS:(%RAX,%RAX,1)

0x5ac194 NOPW	%CS:(%RAX,%RAX,1)

0x5ac19e XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►13.76+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►13.55+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►12.53+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►11.70+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►11.50+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►11.09+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►9.24+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►9.04+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:612	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►2.46+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:626	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.23+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:626	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.03+	hypre_BoomerAMGIndepSetInit	par_indepset.c:67	exec
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2176	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:626	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_5

Source file and lines	random.c:76-115
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:76-79,99,115.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 1.25 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 3.38 to 0.42 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:79
CVTSI2SD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:115
IMUL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:77
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:79

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Conversion instructions

Detected expensive conversion instructions.

Details

CVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:115

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 16 bytes (2 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	27
loop length	106
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	2.67
Overall L1	3.38

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.38 to 2.67 cycles (1.27x speedup).

ASM code

In the binary file, the address of the function is: 5ac120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x5fb7d(%RIP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV $0x41a705af1fe3fb79,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDX	2	0.50	0.50	0.50	0.17	0.17	0.17	0	0	0	0	0	0	0	0	3	3	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3f,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
SAR $0xf,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL $0x1f31d,%RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL $0x41a7,%RCX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL $-0xb14,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x7fffffff(%RCX,%RAX,1),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
CMOVG %RDX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CVTSI2SD %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	scal (12.5%)
MOV %RAX,0x5fb28(%RIP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MULSD 0x37d98(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run icx_5

Source file and lines	random.c:76-115
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:76-79,99,115.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.38 to 1.25 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 8 data elements could be processed at once in vector registers.

By vectorizing your function, you can lower the cost of an iteration from 3.38 to 0.42 cycles (8.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVG: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:79
CVTSI2SD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:115
IMUL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:77
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:79

Workaround

Pass to your compiler a micro-architecture specialization option:

use march=native

Conversion instructions

Detected expensive conversion instructions.

Details

CVTSI2SD (INT32/64 to FP64, scalar): 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/utilities/random.c:115

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 16 bytes (2 double precision FP elements). The binary function is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	27
loop length	106
used x86 registers	5
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.38 cycles
front end	3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Dispatch	2.67
Overall L1	3.38

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.38 cycles. At this rate:

1% of peak load performance is reached (4.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5ac120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV 0x5fb7d(%RIP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV $0x41a705af1fe3fb79,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RDX	2	0.50	0.50	0.50	0.17	0.17	0.17	0	0	0	0	0	0	0	0	3	3	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3f,%RAX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
SAR $0xf,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL $0x1f31d,%RDX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL $0x41a7,%RCX,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL $-0xb14,%RDX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RAX,1),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
TEST %RDX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x7fffffff(%RCX,%RAX,1),%RAX	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	2	0.50	N/A
CMOVG %RDX,%RAX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
CVTSI2SD %RAX,%XMM0	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	3	1	scal (12.5%)
MOV %RAX,0x5fb28(%RIP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MULSD 0x37d98(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
○hypre_Rand	0.02	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code