OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace.extracted.19

	Function: hypre_CSRMatrixMatvecOutOfPlace.extracted.19	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.06% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

191:             if ( num_vectors==1 )

192:             {

193:                tempx = 0;

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x598960 PUSH	%RBP

0x598961 MOV	%RSP,%RBP

0x598964 PUSH	%R15

0x598966 PUSH	%R14

0x598968 PUSH	%R13

0x59896a PUSH	%R12

0x59896c PUSH	%RBX

0x59896d SUB	$0x78,%RSP

0x598971 MOV	%R9,-0x58(%RBP)

0x598975 MOV	%R8,%R14

0x598978 MOV	%RCX,-0x50(%RBP)

0x59897c MOV	%RDX,%R12

0x59897f MOV	0x40(%RBP),%RAX

0x598983 MOV	%RAX,-0x30(%RBP)

0x598987 MOV	0x38(%RBP),%R13

0x59898b MOV	0x30(%RBP),%RAX

0x59898f MOV	%RAX,-0x90(%RBP)

0x598996 MOV	0x28(%RBP),%RAX

0x59899a MOV	%RAX,-0x70(%RBP)

0x59899e MOV	0x20(%RBP),%R15

0x5989a2 MOV	0x18(%RBP),%RAX

0x5989a6 MOV	%RAX,-0x60(%RBP)

0x5989aa MOV	0x10(%RBP),%RBX

0x5989ae MOVL	$0,-0x38(%RBP)

0x5989b5 MOV	(%RDI),%ESI

0x5989b7 MOVQ	$0,-0x68(%RBP)

0x5989bf MOVQ	$0x1,-0x98(%RBP)

0x5989ca SUB	$0x8,%RSP

0x5989ce LEA	-0x98(%RBP),%RAX

0x5989d5 LEA	-0x38(%RBP),%RCX

0x5989d9 LEA	-0x68(%RBP),%R8

0x5989dd LEA	0x50(%RBP),%R9

0x5989e1 MOV	$0x60b3b0,%EDI

0x5989e6 MOV	%ESI,-0x34(%RBP)

0x5989e9 MOV	$0x22,%EDX

0x5989ee PUSH	$0x1

0x5989f0 PUSH	$0x1

0x5989f2 PUSH	%RAX

0x5989f3 CALL	41dc20 <__kmpc_for_static_init_8@plt>

0x5989f8 ADD	$0x20,%RSP

0x5989fc MOV	-0x68(%RBP),%RAX

0x598a00 MOV	0x50(%RBP),%RCX

0x598a04 MOV	%RAX,-0x48(%RBP)

0x598a08 SUB	%RAX,%RCX

0x598a0b MOV	%RCX,-0x40(%RBP)

0x598a0f JAE	598a2c

0x598a11 MOV	$0x60b3d0,%EDI

0x598a16 MOV	-0x34(%RBP),%ESI

0x598a19 ADD	$0x78,%RSP

0x598a1d POP	%RBX

0x598a1e POP	%R12

0x598a20 POP	%R13

0x598a22 POP	%R14

0x598a24 POP	%R15

0x598a26 POP	%RBP

0x598a27 JMP	41d3d0

0x598a2c CMP	$0x1,%R15

0x598a30 JNE	598c31

0x598a36 XOR	%EDX,%EDX

0x598a38 JMP	598af0

0x598a3d ADD	%RAX,%RDI

0x598a40 MOV	0x30(%R14,%RDI,8),%RAX

0x598a45 MOVSD	(%RBX,%RAX,8),%XMM1

0x598a4a MULSD	0x30(%R12,%RDI,8),%XMM1

0x598a51 ADDSD	%XMM1,%XMM0

0x598a55 MOV	0x28(%R14,%RDI,8),%RAX

0x598a5a MOVSD	(%RBX,%RAX,8),%XMM1

0x598a5f MULSD	0x28(%R12,%RDI,8),%XMM1

0x598a66 ADDSD	%XMM1,%XMM0

0x598a6a MOV	0x20(%R14,%RDI,8),%RAX

0x598a6f MOVSD	(%RBX,%RAX,8),%XMM1

0x598a74 MULSD	0x20(%R12,%RDI,8),%XMM1

0x598a7b ADDSD	%XMM1,%XMM0

0x598a7f MOV	0x18(%R14,%RDI,8),%RAX

0x598a84 MOVSD	(%RBX,%RAX,8),%XMM1

0x598a89 MULSD	0x18(%R12,%RDI,8),%XMM1

0x598a90 ADDSD	%XMM1,%XMM0

0x598a94 MOV	0x10(%R14,%RDI,8),%RAX

0x598a99 MOVSD	(%RBX,%RAX,8),%XMM1

0x598a9e MULSD	0x10(%R12,%RDI,8),%XMM1

0x598aa5 ADDSD	%XMM1,%XMM0

0x598aa9 MOV	0x8(%R14,%RDI,8),%RAX

0x598aae MOVSD	(%RBX,%RAX,8),%XMM1

0x598ab3 MULSD	0x8(%R12,%RDI,8),%XMM1

0x598aba ADDSD	%XMM1,%XMM0

0x598abe MOV	(%R14,%RDI,8),%RAX

0x598ac2 MOVSD	(%RBX,%RAX,8),%XMM1

0x598ac7 MULSD	(%R12,%RDI,8),%XMM1

0x598acd ADDSD	%XMM1,%XMM0

(5759) 0x598ad1 MOV	-0x60(%RBP),%RAX

(5759) 0x598ad5 ADDSD	(%RAX,%RSI,8),%XMM0

(5759) 0x598ada MOVSD	%XMM0,(%RAX,%RSI,8)

(5759) 0x598adf LEA	0x1(%RDX),%RAX

(5759) 0x598ae3 CMP	-0x40(%RBP),%RDX

(5759) 0x598ae7 MOV	%RAX,%RDX

(5759) 0x598aea JE	598a11

(5759) 0x598af0 MOV	-0x48(%RBP),%RAX

(5759) 0x598af4 ADD	%RDX,%RAX

(5759) 0x598af7 MOV	-0x58(%RBP),%RCX

(5759) 0x598afb MOV	(%RCX,%RAX,8),%RSI

(5759) 0x598aff MOV	-0x50(%RBP),%RAX

(5759) 0x598b03 MOV	(%RAX,%RSI,8),%RDI

(5759) 0x598b07 MOV	0x8(%RAX,%RSI,8),%RAX

(5759) 0x598b0c XORPD	%XMM0,%XMM0

(5759) 0x598b10 SUB	%RDI,%RAX

(5759) 0x598b13 JLE	598ad1

(5759) 0x598b15 CMP	$0x8,%RAX

(5759) 0x598b19 JB	598be4

(5759) 0x598b1f MOV	%RAX,%R8

(5759) 0x598b22 SHR	$0x3,%R8

(5759) 0x598b26 LEA	0x38(,%RDI,8),%R9

(5759) 0x598b2e XCHG	%AX,%AX

  (5760) 0x598b30 MOV	-0x38(%R14,%R9,1),%RCX

  (5760) 0x598b35 MOV	-0x30(%R14,%R9,1),%R10

  (5760) 0x598b3a MOVSD	(%RBX,%RCX,8),%XMM1

  (5760) 0x598b3f MULSD	-0x38(%R12,%R9,1),%XMM1

  (5760) 0x598b46 ADDSD	%XMM0,%XMM1

  (5760) 0x598b4a MOVSD	(%RBX,%R10,8),%XMM0

  (5760) 0x598b50 MULSD	-0x30(%R12,%R9,1),%XMM0

  (5760) 0x598b57 MOV	-0x28(%R14,%R9,1),%RCX

  (5760) 0x598b5c MOVSD	(%RBX,%RCX,8),%XMM2

  (5760) 0x598b61 MULSD	-0x28(%R12,%R9,1),%XMM2

  (5760) 0x598b68 ADDSD	%XMM0,%XMM2

  (5760) 0x598b6c MOV	-0x20(%R14,%R9,1),%RCX

  (5760) 0x598b71 MOVSD	(%RBX,%RCX,8),%XMM0

  (5760) 0x598b76 MULSD	-0x20(%R12,%R9,1),%XMM0

  (5760) 0x598b7d MOV	-0x18(%R14,%R9,1),%RCX

  (5760) 0x598b82 MOVSD	(%RBX,%RCX,8),%XMM3

  (5760) 0x598b87 MULSD	-0x18(%R12,%R9,1),%XMM3

  (5760) 0x598b8e ADDSD	%XMM1,%XMM2

  (5760) 0x598b92 ADDSD	%XMM0,%XMM3

  (5760) 0x598b96 MOV	-0x10(%R14,%R9,1),%RCX

  (5760) 0x598b9b MOVSD	(%RBX,%RCX,8),%XMM1

  (5760) 0x598ba0 MULSD	-0x10(%R12,%R9,1),%XMM1

  (5760) 0x598ba7 ADDSD	%XMM3,%XMM1

  (5760) 0x598bab ADDSD	%XMM2,%XMM1

  (5760) 0x598baf MOV	-0x8(%R14,%R9,1),%RCX

  (5760) 0x598bb4 MOVSD	(%RBX,%RCX,8),%XMM2

  (5760) 0x598bb9 MULSD	-0x8(%R12,%R9,1),%XMM2

  (5760) 0x598bc0 MOV	(%R14,%R9,1),%RCX

  (5760) 0x598bc4 MOVSD	(%RBX,%RCX,8),%XMM0

  (5760) 0x598bc9 MULSD	(%R12,%R9,1),%XMM0

  (5760) 0x598bcf ADDSD	%XMM2,%XMM0

  (5760) 0x598bd3 ADDSD	%XMM1,%XMM0

  (5760) 0x598bd7 ADD	$0x40,%R9

  (5760) 0x598bdb DEC	%R8

  (5760) 0x598bde JNE	598b30

(5759) 0x598be4 MOV	%EAX,%ECX

(5759) 0x598be6 AND	$0x7,%ECX

(5759) 0x598be9 DEC	%RCX

(5759) 0x598bec CMP	$0x6,%RCX

(5759) 0x598bf0 JA	598ad1

0x598bf6 AND	$-0x8,%RAX

0x598bfa JMP	0x5e1618(,%RCX,8)

0x598c01 ADD	%RAX,%RDI

0x598c04 JMP	598abe

0x598c09 ADD	%RAX,%RDI

0x598c0c JMP	598aa9

0x598c11 ADD	%RAX,%RDI

0x598c14 JMP	598a94

0x598c19 ADD	%RAX,%RDI

0x598c1c JMP	598a7f

0x598c21 ADD	%RAX,%RDI

0x598c24 JMP	598a6a

0x598c29 ADD	%RAX,%RDI

0x598c2c JMP	598a55

0x598c31 JL	598a11

0x598c37 DEC	%R15

0x598c3a XOR	%ECX,%ECX

0x598c3c JMP	598c55

0x598c3e XCHG	%AX,%AX

(5761) 0x598c40 MOV	-0x78(%RBP),%RCX

(5761) 0x598c44 LEA	0x1(%RCX),%RAX

(5761) 0x598c48 CMP	-0x40(%RBP),%RCX

(5761) 0x598c4c MOV	%RAX,%RCX

(5761) 0x598c4f JE	598a11

(5761) 0x598c55 MOV	-0x48(%RBP),%RAX

(5761) 0x598c59 MOV	%RCX,-0x78(%RBP)

(5761) 0x598c5d ADD	%RCX,%RAX

(5761) 0x598c60 MOV	-0x58(%RBP),%RCX

(5761) 0x598c64 MOV	(%RCX,%RAX,8),%RSI

(5761) 0x598c68 MOV	-0x50(%RBP),%RCX

(5761) 0x598c6c MOV	(%RCX,%RSI,8),%RAX

(5761) 0x598c70 MOV	0x8(%RCX,%RSI,8),%RDI

(5761) 0x598c75 SUB	%RAX,%RDI

(5761) 0x598c78 JLE	598c40

(5761) 0x598c7a MOV	%RDI,%RCX

(5761) 0x598c7d SHR	$0x2,%RCX

(5761) 0x598c81 MOV	%RCX,-0x88(%RBP)

(5761) 0x598c88 MOV	%RDI,%R9

(5761) 0x598c8b AND	$-0x4,%R9

(5761) 0x598c8f MOV	%EDI,%R10D

(5761) 0x598c92 AND	$0x3,%R10D

(5761) 0x598c96 ADD	%RAX,%R9

(5761) 0x598c99 IMUL	-0x70(%RBP),%RSI

(5761) 0x598c9e LEA	0x18(,%RAX,8),%RAX

(5761) 0x598ca6 MOV	%RAX,-0x80(%RBP)

(5761) 0x598caa XOR	%ECX,%ECX

(5761) 0x598cac JMP	598d46

0x598cb1 NOPW	%CS:(%RAX,%RAX,1)

  (5762) 0x598cc0 MOV	0x10(%R14,%R9,8),%RDX

  (5762) 0x598cc5 IMUL	%R13,%RDX

  (5762) 0x598cc9 MOV	%RCX,%RAX

  (5762) 0x598ccc IMUL	-0x30(%RBP),%RAX

  (5762) 0x598cd1 ADD	%RAX,%RDX

  (5762) 0x598cd4 MOVSD	(%RBX,%RDX,8),%XMM1

  (5762) 0x598cd9 MULSD	0x10(%R12,%R9,8),%XMM1

  (5762) 0x598ce0 ADDSD	%XMM1,%XMM0

  (5762) 0x598ce4 MOV	0x8(%R14,%R9,8),%RDX

  (5762) 0x598ce9 IMUL	%R13,%RDX

  (5762) 0x598ced ADD	%RAX,%RDX

  (5762) 0x598cf0 MOVSD	(%RBX,%RDX,8),%XMM1

  (5762) 0x598cf5 MULSD	0x8(%R12,%R9,8),%XMM1

  (5762) 0x598cfc ADDSD	%XMM1,%XMM0

  (5762) 0x598d00 MOV	(%R14,%R9,8),%RDX

  (5762) 0x598d04 IMUL	%R13,%RDX

  (5762) 0x598d08 ADD	%RAX,%RDX

  (5762) 0x598d0b MOVSD	(%RBX,%RDX,8),%XMM1

  (5762) 0x598d10 MULSD	(%R12,%R9,8),%XMM1

  (5762) 0x598d16 ADDSD	%XMM1,%XMM0

  (5762) 0x598d1a MOV	%RCX,%RAX

  (5762) 0x598d1d IMUL	-0x90(%RBP),%RAX

  (5762) 0x598d25 ADD	%RSI,%RAX

  (5762) 0x598d28 MOV	-0x60(%RBP),%RDX

  (5762) 0x598d2c ADDSD	(%RDX,%RAX,8),%XMM0

  (5762) 0x598d31 MOVSD	%XMM0,(%RDX,%RAX,8)

  (5762) 0x598d36 LEA	0x1(%RCX),%RAX

  (5762) 0x598d3a CMP	%R15,%RCX

  (5762) 0x598d3d MOV	%RAX,%RCX

  (5762) 0x598d40 JE	598c40

  (5762) 0x598d46 XORPD	%XMM0,%XMM0

  (5762) 0x598d4a CMP	$0x4,%RDI

  (5762) 0x598d4e JB	598de7

  (5762) 0x598d54 MOV	%RCX,%RAX

  (5762) 0x598d57 IMUL	-0x30(%RBP),%RAX

  (5762) 0x598d5c MOV	-0x88(%RBP),%R8

  (5762) 0x598d63 MOV	-0x80(%RBP),%R11

  (5762) 0x598d67 NOPW	(%RAX,%RAX,1)

    (5763) 0x598d70 MOV	-0x18(%R14,%R11,1),%RDX

    (5763) 0x598d75 IMUL	%R13,%RDX

    (5763) 0x598d79 ADD	%RAX,%RDX

    (5763) 0x598d7c MOVSD	(%RBX,%RDX,8),%XMM1

    (5763) 0x598d81 MULSD	-0x18(%R12,%R11,1),%XMM1

    (5763) 0x598d88 MOV	-0x10(%R14,%R11,1),%RDX

    (5763) 0x598d8d IMUL	%R13,%RDX

    (5763) 0x598d91 ADD	%RAX,%RDX

    (5763) 0x598d94 MOVSD	(%RBX,%RDX,8),%XMM2

    (5763) 0x598d99 MULSD	-0x10(%R12,%R11,1),%XMM2

    (5763) 0x598da0 MOV	-0x8(%R14,%R11,1),%RDX

    (5763) 0x598da5 IMUL	%R13,%RDX

    (5763) 0x598da9 ADD	%RAX,%RDX

    (5763) 0x598dac MOVSD	(%RBX,%RDX,8),%XMM3

    (5763) 0x598db1 MULSD	-0x8(%R12,%R11,1),%XMM3

    (5763) 0x598db8 ADDSD	%XMM0,%XMM1

    (5763) 0x598dbc ADDSD	%XMM2,%XMM3

    (5763) 0x598dc0 MOV	(%R14,%R11,1),%RDX

    (5763) 0x598dc4 IMUL	%R13,%RDX

    (5763) 0x598dc8 ADD	%RAX,%RDX

    (5763) 0x598dcb MOVSD	(%RBX,%RDX,8),%XMM0

    (5763) 0x598dd0 MULSD	(%R12,%R11,1),%XMM0

    (5763) 0x598dd6 ADDSD	%XMM1,%XMM3

    (5763) 0x598dda ADDSD	%XMM3,%XMM0

    (5763) 0x598dde ADD	$0x20,%R11

    (5763) 0x598de2 DEC	%R8

    (5763) 0x598de5 JNE	598d70

  (5762) 0x598de7 CMP	$0x1,%R10D

  (5762) 0x598deb JE	598e10

  (5762) 0x598ded CMP	$0x3,%R10D

  (5762) 0x598df1 JE	598cc0

  (5762) 0x598df7 CMP	$0x2,%R10D

  (5762) 0x598dfb JNE	598d1a

  (5762) 0x598e01 MOV	%RCX,%RAX

  (5762) 0x598e04 IMUL	-0x30(%RBP),%RAX

  (5762) 0x598e09 JMP	598ce4

0x598e0e XCHG	%AX,%AX

  (5762) 0x598e10 MOV	%RCX,%RAX

  (5762) 0x598e13 IMUL	-0x30(%RBP),%RAX

  (5762) 0x598e18 JMP	598d00

0x598e1d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.33+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.44+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:211	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:237	exec
○	hypre_BoomerAMGCycle	par_cycle.c:425	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:272	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec
►1.01+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_CSRMatrixMatvecOutOfPlac[...]	csr_matvec.c:211	exec
○	hypre_ParCSRMatrixMatvecOutOfP[...]	par_csr_matvec.c:237	exec
○	hypre_PCGSolve	pcg.c:496	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_5

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.63 to 3.75 cycles (3.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.63 to 1.12 cycles (12.16x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction
7: multiply

The binary function is loading 256 bytes (32 double precision FP elements). The binary function is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	109
loop length	463
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	20
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	11.50	11.50	11.50	11.50	3.50	3.50	3.50	3.50	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	11.50	11.50	11.50	11.50	3.50	3.50	3.50	3.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	11.50
Overall L1	13.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.63 cycles. At this rate:

7% of peak load performance is reached (18.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.63 to 11.50 cycles (1.18x speedup).

ASM code

In the binary file, the address of the function is: 598960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x50(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x60b3b0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 598a2c <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xcc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x60b3d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x1,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 598c31 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x2d1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 598af0 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x28(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x10(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5e1618(,%RCX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598abe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x15e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598aa9 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x149>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a94 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x134>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a7f <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x11f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a6a <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x10a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a55 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xf5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
JL 598a11 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 598c55 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x2f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run icx_5

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,191-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.63 to 3.75 cycles (3.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:194

Type of elements and instruction set

14 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 14 FP arithmetical operations:

7: addition or subtraction
7: multiply

The binary function is loading 256 bytes (32 double precision FP elements). The binary function is storing 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	111
nb uops	109
loop length	463
used x86 registers	14
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	20
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	11.50	11.50	11.50	11.50	3.50	3.50	3.50	3.50	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	11.50	11.50	11.50	11.50	3.50	3.50	3.50	3.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	11.50
Overall L1	13.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	11%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.63 cycles. At this rate:

7% of peak load performance is reached (18.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 598960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x98(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x68(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x50(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV $0x60b3b0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
JAE 598a2c <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xcc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV $0x60b3d0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
ADD $0x78,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x1,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 598c31 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x2d1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 598af0 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x30(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x28(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x28(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x20(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x20(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x18(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x18(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x10(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x10(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV 0x8(%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD 0x8(%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
MOV (%R14,%RDI,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVSD (%RBX,%RAX,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MULSD (%R12,%RDI,8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	3	0.50	scal (12.5%)
ADDSD %XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	2	0.50	scal (12.5%)
AND $-0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 0x5e1618(,%RCX,8)	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598abe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x15e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598aa9 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x149>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a94 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x134>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a7f <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x11f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a6a <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x10a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 598a55 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xf5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
JL 598a11 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xb1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 598c55 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x2f5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace.extracted.19–	0.06	0.03
▼Loop 5759 - csr_matvec.c:178-196 - exec–	0.01	0.01
○Loop 5760 - csr_matvec.c:194-195 - exec	0.04	0.02
▼Loop 5761 - csr_matvec.c:178-204 - exec–	0.00	0.00
▼Loop 5762 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 5763 - csr_matvec.c:202-203 - exec	0.00	0.00

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FMA

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CALL instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code