OV - exec - Function hypre_IJMatrixAssembleParCSR.extracted.25

	Function: hypre_IJMatrixAssembleParCSR.extracted.25	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage (incl. loops): 0.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x5804c0 PUSH	%RBP

0x5804c1 MOV	%RSP,%RBP

0x5804c4 PUSH	%R15

0x5804c6 PUSH	%R14

0x5804c8 PUSH	%R13

0x5804ca PUSH	%R12

0x5804cc PUSH	%RBX

0x5804cd SUB	$0x18,%RSP

0x5804d1 MOV	%R9,%RBX

0x5804d4 MOV	%R8,%R14

0x5804d7 MOV	%RCX,%R15

0x5804da MOV	%RDX,%R13

0x5804dd MOVL	$0,-0x2c(%RBP)

0x5804e4 MOV	(%RDI),%R12D

0x5804e7 MOVQ	$0,-0x38(%RBP)

0x5804ef MOVQ	$0x1,-0x40(%RBP)

0x5804f7 SUB	$0x8,%RSP

0x5804fb LEA	-0x40(%RBP),%RAX

0x5804ff LEA	-0x2c(%RBP),%RCX

0x580503 LEA	-0x38(%RBP),%R8

0x580507 LEA	0x18(%RBP),%R9

0x58050b MOV	$0x60adb0,%EDI

0x580510 MOV	%R12D,%ESI

0x580513 MOV	$0x22,%EDX

0x580518 PUSH	$0x1

0x58051a PUSH	$0x1

0x58051c PUSH	%RAX

0x58051d CALL	41dc20 <__kmpc_for_static_init_8@plt>

0x580522 ADD	$0x20,%RSP

0x580526 MOV	-0x38(%RBP),%RAX

0x58052a MOV	0x18(%RBP),%RCX

0x58052e CMP	%RCX,%RAX

0x580531 JBE	58054e

0x580533 MOV	$0x60add0,%EDI

0x580538 MOV	%R12D,%ESI

0x58053b ADD	$0x18,%RSP

0x58053f POP	%RBX

0x580540 POP	%R12

0x580542 POP	%R13

0x580544 POP	%R14

0x580546 POP	%R15

0x580548 POP	%RBP

0x580549 JMP	41d3d0

0x58054e MOV	(%R13,%RAX,8),%RDX

0x580553 JMP	58056b

0x580555 NOPW	%CS:(%RAX,%RAX,1)

(5325) 0x580560 MOV	%R8,%RDX

(5325) 0x580563 CMP	%RCX,%RAX

(5325) 0x580566 MOV	%RSI,%RAX

(5325) 0x580569 JE	580533

(5325) 0x58056b LEA	0x1(%RAX),%RSI

(5325) 0x58056f MOV	0x8(%R13,%RAX,8),%R8

(5325) 0x580574 CMP	%R8,%RDX

(5325) 0x580577 JGE	580560

(5325) 0x580579 MOV	%RDX,%RDI

(5325) 0x58057c JMP	58058d

0x58057e XCHG	%AX,%AX

  (5326) 0x580580 INC	%RDI

  (5326) 0x580583 MOV	(%R13,%RSI,8),%R8

  (5326) 0x580588 CMP	%R8,%RDI

  (5326) 0x58058b JGE	580560

  (5326) 0x58058d MOV	(%R15,%RDI,8),%R8

  (5326) 0x580591 SUB	%RBX,%R8

  (5326) 0x580594 MOV	%R8,(%R15,%RDI,8)

  (5326) 0x580598 CMP	%RAX,%R8

  (5326) 0x58059b JNE	580580

  (5326) 0x58059d MOVSD	(%R14,%RDX,8),%XMM0

  (5326) 0x5805a3 MOVSD	(%R14,%RDI,8),%XMM1

  (5326) 0x5805a9 MOVSD	%XMM1,(%R14,%RDX,8)

  (5326) 0x5805af MOVSD	%XMM0,(%R14,%RDI,8)

  (5326) 0x5805b5 MOV	(%R15,%RDX,8),%R8

  (5326) 0x5805b9 MOV	%R8,(%R15,%RDI,8)

  (5326) 0x5805bd MOV	%RAX,(%R15,%RDX,8)

  (5326) 0x5805c1 JMP	580580

0x5805c3 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.64+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.06+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	hypre_IJMatrixAssembleParCSR	IJMatrix_parcsr.c:2798	exec
○	BuildIJLaplacian27pt	amg.c:2267	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 5.75 to 0.38 cycles (15.06x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	48
nb uops	46
loop length	175
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	2.67
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.75 cycles. At this rate:

1% of peak load performance is reached (4.87 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.75 to 2.67 cycles (2.16x speedup).

ASM code

In the binary file, the address of the function is: 5804c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x18(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x60adb0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 58054e <hypre_IJMatrixAssembleParCSR.extracted.25+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x60add0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 58056b <hypre_IJMatrixAssembleParCSR.extracted.25+0xab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_5

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	48
nb uops	46
loop length	175
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	2.67	2.67	2.67	2.67	2.67	2.67	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.67	2.67	2.67	2.67	2.67	2.67	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	2.67
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.75 cycles. At this rate:

1% of peak load performance is reached (4.87 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 5804c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV (%RDI),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x18(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x60adb0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 41dc20 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 58054e <hypre_IJMatrixAssembleParCSR.extracted.25+0x8e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x60add0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
ADD $0x18,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 41d3d0 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV (%R13,%RAX,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 58056b <hypre_IJMatrixAssembleParCSR.extracted.25+0xab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR.extracted.25–	0.62	0.32
▼Loop 5325 - IJMatrix_parcsr.c:2798-2812 - exec–	0.01	0.01
○Loop 5326 - IJMatrix_parcsr.c:2803-2812 - exec	0.61	0.30

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