OV - exec - Loop 619

	Loop Id: 619	Module: exec	Source: par_coarsen.c:2437-2477 [...]	Coverage: 0.06%

0x259d70 CMPQ	$0,(%RSI,%R14,8)

0x259d75 JLE	259da0

0x259d77 MOVQ	$0x1,(%RSI,%R14,8)

0x259d7f LEA	0x1(%RAX),%R14

0x259d83 CMP	-0x30(%RBP),%RAX

0x259d87 MOV	%R14,%RAX

0x259d8a JGE	259d1a

0x259d8c MOV	(%RCX,%RAX,8),%R14

0x259d90 VUCOMISD	(%RDX,%R14,8),%XMM0

0x259d96 JBE	259d70

0x259d98 MOVQ	$-0x1,(%RSI,%R14,8)

0x259da0 MOV	(%RDI,%R14,8),%R15

0x259da4 MOV	0x8(%RDI,%R14,8),%R12

0x259da9 JMP	259db3

  (621) 0x259db0 INC	%R15

  (621) 0x259db3 CMP	%R12,%R15

  (621) 0x259db6 JGE	259de0

  (621) 0x259db8 MOV	(%R8,%R15,8),%R13

  (621) 0x259dbc CMPQ	$0,(%RSI,%R13,8)

  (621) 0x259dc1 JLE	259db0

  (621) 0x259dc3 MOVQ	$-0x1,(%RSI,%R14,8)

  (621) 0x259dcb MOV	0x8(%RDI,%R14,8),%R12

  (621) 0x259dd0 JMP	259db0

0x259de0 MOV	(%R9,%R14,8),%R15

0x259de4 MOV	0x8(%R9,%R14,8),%R12

0x259de9 JMP	259df3

  (620) 0x259df0 INC	%R15

  (620) 0x259df3 CMP	%R12,%R15

  (620) 0x259df6 JGE	259d7f

  (620) 0x259df8 MOV	(%R10,%R15,8),%R13

  (620) 0x259dfc CMPQ	$0,(%R11,%R13,8)

  (620) 0x259e01 JLE	259df0

  (620) 0x259e03 MOVQ	$-0x1,(%RSI,%R14,8)

  (620) 0x259e0b MOV	0x8(%R9,%R14,8),%R12

  (620) 0x259e10 JMP	259df0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2437 - 2477

--------------------------------------------------------------------------------

2437:      for (ig = 0; ig < graph_size; ig++) {

2438:        i = graph_array[ig];

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2474: 	 {

2475: 	   j = S_offd_j[jS];

2476: 	   if (CF_marker_offd[j] > 0) /* j is a C-point */

2477: 	     CF_marker[i] = F_PT;

Coverage (%)	Name	Source Location	Module
►95.70+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.54+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2435	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec
►1.11+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source	par_coarsen.c:2437-2438,par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.25
Front-end cycles	2.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	18.00
Nb loads	8.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source	par_coarsen.c:2437-2438,par_coarsen.c:2446-2446,par_coarsen.c:2453-2453,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.50
CQA cycles if fully vectorized	0.25
Front-end cycles	2.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	18.00
Nb loads	8.00
Nb stores	2.00
Nb stack references	1.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.94
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source file and lines	par_coarsen.c:2437-2477
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2437-2438,2446,2453,2465-2477.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2437-2438,2446,2453,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 11 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.50 to 0.25 cycles (10.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.25 cycles (1.11x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes (8 double precision FP elements). The binary loop is storing 16 bytes (2 double precision FP elements).

General properties

nb instructions	17
nb uops	18
loop length	70
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.67	1.67	1.67	2.50	2.50	2.50	2.50	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.00	1.00	1.00	1.67	1.67	1.67	2.50	2.50	2.50	2.50	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.25
Dispatch	2.50
Overall L1	2.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

10% of peak load performance is reached (25.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 259d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMPQ $0,(%RSI,%R14,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 259da0 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVQ $0x1,(%RSI,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 259d1a <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX,%RAX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VUCOMISD (%RDX,%R14,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 259d70 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0xe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVQ $-0x1,(%RSI,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI,%R14,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 259db3 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x123>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV (%R9,%R14,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%R9,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 259df3 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source file and lines	par_coarsen.c:2437-2477
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.50 to 1.00 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 2.50 to 2.25 cycles (1.11x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	17
nb uops	18
loop length	70
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.00	1.00	1.00	1.67	1.67	1.67	2.50	2.50	2.50	2.50	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.00	1.00	1.00	1.67	1.67	1.67	2.50	2.50	2.50	2.50	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.25
Dispatch	2.50
Overall L1	2.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.50 cycles. At this rate:

10% of peak load performance is reached (25.60 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 259d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
CMPQ $0,(%RSI,%R14,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 259da0 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x110>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVQ $0x1,(%RSI,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
LEA 0x1(%RAX),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP -0x30(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV %R14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JGE 259d1a <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x8a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%RCX,%RAX,8),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VUCOMISD (%RDX,%R14,8),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JBE 259d70 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0xe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOVQ $-0x1,(%RSI,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV (%RDI,%R14,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RDI,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 259db3 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x123>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV (%R9,%R14,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%R9,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
JMP 259df3 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code