OV - exec - Loop 429

	Loop Id: 429	Module: exec	Source: ams.c:3664-3682	Coverage: 18.83%

0x251070 INC	%RAX

0x251073 MOV	%RAX,%RCX

0x251076 CMP	%RBX,%RCX

0x251079 JG	251427

0x25107f MOV	(%R15,%RAX,8),%RSI

0x251083 VMOVSD	(%RDX,%RSI,8),%XMM0

0x251088 VUCOMISD	(%R13),%XMM0

0x25108e JE	251070

0x251090 MOV	-0x90(%RBP),%RCX

0x251097 MOV	0x8(%R15,%RAX,8),%RDI

0x25109c VMOVQ	(%RCX,%RAX,8),%XMM0

0x2510a1 MOV	%RDI,%R10

0x2510a4 SUB	%RSI,%R10

0x2510a7 JLE	2510c0

0x2510a9 CMP	$0x10,%R10

0x2510ad JAE	2510c9

0x2510af MOV	-0x38(%RBP),%R10

0x2510b3 MOV	%RSI,%R14

0x2510b6 JMP	251220

0x2510c0 MOV	-0x38(%RBP),%R10

0x2510c4 JMP	251238

0x2510c9 MOV	-0x70(%RBP),%R15

0x2510cd MOV	%R10,%RBX

0x2510d0 AND	$-0x10,%RBX

0x2510d4 LEA	(%R8,%RSI,8),%RCX

0x2510d8 VMOVQ	%XMM0,%XMM0

0x2510dc VXORPD	%XMM1,%XMM1,%XMM1

0x2510e0 VXORPD	%XMM2,%XMM2,%XMM2

0x2510e4 VXORPD	%XMM3,%XMM3,%XMM3

0x2510e8 XOR	%R13D,%R13D

0x2510eb LEA	(%RSI,%RBX,1),%R14

0x2510ef LEA	(%R15,%RSI,8),%RSI

0x2510f3 NOPW	%CS:(%RAX,%RAX,1)

  (432) 0x251100 MOV	0x10(%RCX,%R13,8),%R15

  (432) 0x251105 VMOVSD	(%R9,%R15,8),%XMM4

  (432) 0x25110b MOV	0x18(%RCX,%R13,8),%R15

  (432) 0x251110 VMOVHPD	(%R9,%R15,8),%XMM4,%XMM4

  (432) 0x251116 MOV	(%RCX,%R13,8),%R15

  (432) 0x25111a VMOVSD	(%R9,%R15,8),%XMM5

  (432) 0x251120 MOV	0x8(%RCX,%R13,8),%R15

  (432) 0x251125 VMOVHPD	(%R9,%R15,8),%XMM5,%XMM5

  (432) 0x25112b MOV	0x30(%RCX,%R13,8),%R15

  (432) 0x251130 VMOVSD	(%R9,%R15,8),%XMM6

  (432) 0x251136 MOV	0x38(%RCX,%R13,8),%R15

  (432) 0x25113b VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

  (432) 0x251141 VFNMADD231PD	-0x60(%RSI,%R13,8),%YMM4,%YMM0

  (432) 0x251148 VMOVHPD	(%R9,%R15,8),%XMM6,%XMM6

  (432) 0x25114e MOV	0x20(%RCX,%R13,8),%R15

  (432) 0x251153 VMOVSD	(%R9,%R15,8),%XMM7

  (432) 0x251159 MOV	0x28(%RCX,%R13,8),%R15

  (432) 0x25115e VMOVHPD	(%R9,%R15,8),%XMM7,%XMM7

  (432) 0x251164 MOV	0x50(%RCX,%R13,8),%R15

  (432) 0x251169 VMOVSD	(%R9,%R15,8),%XMM8

  (432) 0x25116f MOV	0x58(%RCX,%R13,8),%R15

  (432) 0x251174 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM5

  (432) 0x25117a VFNMADD231PD	-0x40(%RSI,%R13,8),%YMM5,%YMM1

  (432) 0x251181 VMOVHPD	(%R9,%R15,8),%XMM8,%XMM8

  (432) 0x251187 MOV	0x40(%RCX,%R13,8),%R15

  (432) 0x25118c VMOVSD	(%R9,%R15,8),%XMM9

  (432) 0x251192 MOV	0x48(%RCX,%R13,8),%R15

  (432) 0x251197 VMOVHPD	(%R9,%R15,8),%XMM9,%XMM9

  (432) 0x25119d MOV	0x70(%RCX,%R13,8),%R15

  (432) 0x2511a2 VMOVSD	(%R9,%R15,8),%XMM10

  (432) 0x2511a8 MOV	0x78(%RCX,%R13,8),%R15

  (432) 0x2511ad VINSERTF128	$0x1,%XMM8,%YMM9,%YMM6

  (432) 0x2511b3 VFNMADD231PD	-0x20(%RSI,%R13,8),%YMM6,%YMM2

  (432) 0x2511ba VMOVHPD	(%R9,%R15,8),%XMM10,%XMM10

  (432) 0x2511c0 MOV	0x60(%RCX,%R13,8),%R15

  (432) 0x2511c5 VMOVSD	(%R9,%R15,8),%XMM11

  (432) 0x2511cb MOV	0x68(%RCX,%R13,8),%R15

  (432) 0x2511d0 VMOVHPD	(%R9,%R15,8),%XMM11,%XMM11

  (432) 0x2511d6 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM7

  (432) 0x2511dc VFNMADD231PD	(%RSI,%R13,8),%YMM7,%YMM3

  (432) 0x2511e2 ADD	$0x10,%R13

  (432) 0x2511e6 CMP	%R13,%RBX

  (432) 0x2511e9 JNE	251100

0x2511ef VADDPD	%YMM0,%YMM1,%YMM0

0x2511f3 VADDPD	%YMM2,%YMM3,%YMM1

0x2511f7 MOV	-0x58(%RBP),%R13

0x2511fb MOV	-0x50(%RBP),%R15

0x2511ff VADDPD	%YMM0,%YMM1,%YMM0

0x251203 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x251209 VADDPD	%XMM1,%XMM0,%XMM0

0x25120d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x251212 VADDSD	%XMM1,%XMM0,%XMM0

0x251216 CMP	%RBX,%R10

0x251219 MOV	-0x38(%RBP),%R10

0x25121d JE	251238

0x25121f NOP

  (433) 0x251220 MOV	(%R8,%R14,8),%RCX

  (433) 0x251224 VMOVSD	(%R9,%RCX,8),%XMM1

  (433) 0x25122a VFNMADD231SD	(%RDX,%R14,8),%XMM1,%XMM0

  (433) 0x251230 INC	%R14

  (433) 0x251233 CMP	%R14,%RDI

  (433) 0x251236 JNE	251220

0x251238 MOV	-0x88(%RBP),%RCX

0x25123f MOV	0x8(%RCX,%RAX,8),%RDI

0x251244 MOV	(%RCX,%RAX,8),%RSI

0x251248 MOV	%RDI,%RBX

0x25124b SUB	%RSI,%RBX

0x25124e JLE	251270

0x251250 CMP	$0x10,%RBX

0x251254 JAE	251279

0x251256 MOV	-0x30(%RBP),%RBX

0x25125a MOV	%RSI,%R14

0x25125d JMP	2513e0

0x251270 MOV	-0x30(%RBP),%RBX

0x251274 JMP	2513f8

0x251279 MOV	-0x68(%RBP),%R15

0x25127d MOV	%RBX,%R10

0x251280 AND	$-0x10,%R10

0x251284 LEA	(%R11,%RSI,8),%RCX

0x251288 VMOVQ	%XMM0,%XMM0

0x25128c VXORPD	%XMM1,%XMM1,%XMM1

0x251290 VXORPD	%XMM2,%XMM2,%XMM2

0x251294 VXORPD	%XMM3,%XMM3,%XMM3

0x251298 XOR	%R13D,%R13D

0x25129b LEA	(%RSI,%R10,1),%R14

0x25129f LEA	(%R15,%RSI,8),%RSI

0x2512a3 NOPW	%CS:(%RAX,%RAX,1)

  (430) 0x2512b0 MOV	0x10(%RCX,%R13,8),%R15

  (430) 0x2512b5 VMOVSD	(%R12,%R15,8),%XMM4

  (430) 0x2512bb MOV	0x18(%RCX,%R13,8),%R15

  (430) 0x2512c0 VMOVHPD	(%R12,%R15,8),%XMM4,%XMM4

  (430) 0x2512c6 MOV	(%RCX,%R13,8),%R15

  (430) 0x2512ca VMOVSD	(%R12,%R15,8),%XMM5

  (430) 0x2512d0 MOV	0x8(%RCX,%R13,8),%R15

  (430) 0x2512d5 VMOVHPD	(%R12,%R15,8),%XMM5,%XMM5

  (430) 0x2512db MOV	0x30(%RCX,%R13,8),%R15

  (430) 0x2512e0 VMOVSD	(%R12,%R15,8),%XMM6

  (430) 0x2512e6 MOV	0x38(%RCX,%R13,8),%R15

  (430) 0x2512eb VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

  (430) 0x2512f1 VFNMADD231PD	-0x60(%RSI,%R13,8),%YMM4,%YMM0

  (430) 0x2512f8 VMOVHPD	(%R12,%R15,8),%XMM6,%XMM6

  (430) 0x2512fe MOV	0x20(%RCX,%R13,8),%R15

  (430) 0x251303 VMOVSD	(%R12,%R15,8),%XMM7

  (430) 0x251309 MOV	0x28(%RCX,%R13,8),%R15

  (430) 0x25130e VMOVHPD	(%R12,%R15,8),%XMM7,%XMM7

  (430) 0x251314 MOV	0x50(%RCX,%R13,8),%R15

  (430) 0x251319 VMOVSD	(%R12,%R15,8),%XMM8

  (430) 0x25131f MOV	0x58(%RCX,%R13,8),%R15

  (430) 0x251324 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM5

  (430) 0x25132a VFNMADD231PD	-0x40(%RSI,%R13,8),%YMM5,%YMM1

  (430) 0x251331 VMOVHPD	(%R12,%R15,8),%XMM8,%XMM8

  (430) 0x251337 MOV	0x40(%RCX,%R13,8),%R15

  (430) 0x25133c VMOVSD	(%R12,%R15,8),%XMM9

  (430) 0x251342 MOV	0x48(%RCX,%R13,8),%R15

  (430) 0x251347 VMOVHPD	(%R12,%R15,8),%XMM9,%XMM9

  (430) 0x25134d MOV	0x70(%RCX,%R13,8),%R15

  (430) 0x251352 VMOVSD	(%R12,%R15,8),%XMM10

  (430) 0x251358 MOV	0x78(%RCX,%R13,8),%R15

  (430) 0x25135d VINSERTF128	$0x1,%XMM8,%YMM9,%YMM6

  (430) 0x251363 VFNMADD231PD	-0x20(%RSI,%R13,8),%YMM6,%YMM2

  (430) 0x25136a VMOVHPD	(%R12,%R15,8),%XMM10,%XMM10

  (430) 0x251370 MOV	0x60(%RCX,%R13,8),%R15

  (430) 0x251375 VMOVSD	(%R12,%R15,8),%XMM11

  (430) 0x25137b MOV	0x68(%RCX,%R13,8),%R15

  (430) 0x251380 VMOVHPD	(%R12,%R15,8),%XMM11,%XMM11

  (430) 0x251386 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM7

  (430) 0x25138c VFNMADD231PD	(%RSI,%R13,8),%YMM7,%YMM3

  (430) 0x251392 ADD	$0x10,%R13

  (430) 0x251396 CMP	%R13,%R10

  (430) 0x251399 JNE	2512b0

0x25139f VADDPD	%YMM0,%YMM1,%YMM0

0x2513a3 VADDPD	%YMM2,%YMM3,%YMM1

0x2513a7 MOV	-0x58(%RBP),%R13

0x2513ab MOV	-0x50(%RBP),%R15

0x2513af VADDPD	%YMM0,%YMM1,%YMM0

0x2513b3 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x2513b9 VADDPD	%XMM1,%XMM0,%XMM0

0x2513bd VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x2513c2 VADDSD	%XMM1,%XMM0,%XMM0

0x2513c6 CMP	%R10,%RBX

0x2513c9 MOV	-0x30(%RBP),%RBX

0x2513cd MOV	-0x38(%RBP),%R10

0x2513d1 JE	2513f8

0x2513d3 NOPW	%CS:(%RAX,%RAX,1)

  (431) 0x2513e0 MOV	(%R11,%R14,8),%RCX

  (431) 0x2513e4 VMOVSD	(%R12,%RCX,8),%XMM1

  (431) 0x2513ea VFNMADD231SD	(%R10,%R14,8),%XMM1,%XMM0

  (431) 0x2513f0 INC	%R14

  (431) 0x2513f3 CMP	%R14,%RDI

  (431) 0x2513f6 JNE	2513e0

0x2513f8 MOV	0x50(%RBP),%RSI

0x2513fc MOV	-0x80(%RBP),%RDI

0x251400 LEA	0x1(%RAX),%RCX

0x251404 VMULSD	(%RSI),%XMM0,%XMM0

0x251408 MOV	-0x78(%RBP),%RSI

0x25140c VDIVSD	(%RDI,%RAX,8),%XMM0,%XMM0

0x251411 VADDSD	(%RSI,%RAX,8),%XMM0,%XMM0

0x251416 VMOVSD	%XMM0,(%RSI,%RAX,8)

0x25141b MOV	%RCX,%RAX

0x25141e CMP	%RBX,%RCX

0x251421 JLE	25107f

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3664 - 3682

--------------------------------------------------------------------------------

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
►96.34+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.94+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:243	exec
○	hypre_PCGSolve	pcg.c:545	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.77
CQA speedup if FP arith vectorized	3.53
CQA speedup if fully vectorized	5.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source	ams.c:3664-3664,ams.c:3669-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	3.26
CQA cycles if fully vectorized	2.00
Front-end cycles	11.50
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	92.00
Nb loads	28.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	2.87
Nb FLOP add-sub	31.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.17
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	72.73
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	35.23
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.77
CQA speedup if FP arith vectorized	3.53
CQA speedup if fully vectorized	5.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source	ams.c:3664-3664,ams.c:3669-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	3.26
CQA cycles if fully vectorized	2.00
Front-end cycles	11.50
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	5.00
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	1.00
P15 cycles	1.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	96.00
Nb uops	92.00
Nb loads	28.00
Nb stores	1.00
Nb stack references	11.00
FLOP/cycle	2.87
Nb FLOP add-sub	31.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.17
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	72.73
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	35.23
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source file and lines	ams.c:3664-3682
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3664-3682.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3664,3669-3672,3677,3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=17
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 17 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 6.50 cycles (1.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
72% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3669

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 6 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 33 FP arithmetical operations:

31: addition or subtraction
1: multiply
1: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	92
loop length	406
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	11.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	7.25	7.25	7.25	7.25	4.00	4.00	6.00	6.00	1.00	1.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	7.25	7.25	7.25	7.25	4.00	4.00	6.00	6.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	11.50
Dispatch	7.25
DIV/SQRT	4.00
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	69%
load	0%
store	0%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	90%

INT+FP

all	50%
load	0%
store	0%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	26%
load	12%
store	12%
mul	12%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	22%
load	12%
store	12%
mul	12%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

7% of peak load performance is reached (19.48 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.50 to 7.25 cycles (1.59x speedup).

ASM code

In the binary file, the address of the loop is: 25107f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 251427 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R15,%RAX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDX,%RSI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD (%R13),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 251070 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x120>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R15,%RAX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 2510c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2510c9 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x179>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 251220 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 251238 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x70(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RSI,%RBX,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RSI,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 251238 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 251270 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 251279 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x329>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2513e0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 2513f8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x68(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RSI,%R10,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RSI,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 2513f8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVSD (%RDI,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD (%RSI,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 25107f <hypre_ParCSRRelaxThreads.omp_outlined.28+0x12f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source file and lines	ams.c:3664-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=17
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.50 to 6.50 cycles (1.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
72% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3669

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3672
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3677

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 33 FP arithmetical operations:

31: addition or subtraction
1: multiply
1: divide

The binary loop is loading 224 bytes (28 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	96
nb uops	92
loop length	406
used x86 registers	13
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	11
ADD-SUB / MUL ratio	11.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.00	5.00	5.00	5.00	5.00	5.00	7.25	7.25	7.25	7.25	4.00	4.00	6.00	6.00	1.00	1.00
cycles	5.00	5.00	5.00	5.00	5.00	5.00	7.25	7.25	7.25	7.25	4.00	4.00	6.00	6.00	1.00	1.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	11.50
Dispatch	7.25
DIV/SQRT	4.00
Overall L1	11.50

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	69%
load	0%
store	0%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	90%

INT+FP

all	50%
load	0%
store	0%
mul	0%
add-sub	72%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	26%
load	12%
store	12%
mul	12%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	22%
load	12%
store	12%
mul	12%
add-sub	35%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.50 cycles. At this rate:

7% of peak load performance is reached (19.48 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 25107f

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 251427 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4d7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R15,%RAX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDX,%RSI,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VUCOMISD (%R13),%XMM0	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JE 251070 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x120>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R15,%RAX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ (%RCX,%RAX,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 2510c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2510c9 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x179>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 251220 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 251238 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x70(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RSI,%RBX,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RSI,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 251238 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2e8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RAX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 251270 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x320>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 251279 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x329>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2513e0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x490>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 2513f8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x68(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x10,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R11,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMOVQ %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R13D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RSI,%R10,1),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R15,%RSI,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x58(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %YMM0,%YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x30(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 2513f8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x4a8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x50(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VMULSD (%RSI),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VDIVSD (%RDI,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
VADDSD (%RSI,%RAX,8),%XMM0,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM0,(%RSI,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RBX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 25107f <hypre_ParCSRRelaxThreads.omp_outlined.28+0x12f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code