OV - exec - Loop 3622

	Loop Id: 3622	Module: exec	Source: csr_matvec.c:310-312	Coverage: 5.78%

0x2f89c0 MOV	-0x50(%R10,%RDX,8),%RAX    [2]

0x2f89c5 VMOVSD	(%R8,%RAX,8),%XMM4    [1]

0x2f89cb MOV	-0x48(%R10,%RDX,8),%RAX    [2]

0x2f89d0 VMOVHPD	(%R8,%RAX,8),%XMM4,%XMM4    [1]

0x2f89d6 MOV	-0x60(%R10,%RDX,8),%RAX    [2]

0x2f89db VMOVSD	(%R8,%RAX,8),%XMM5    [1]

0x2f89e1 MOV	-0x58(%R10,%RDX,8),%RAX    [2]

0x2f89e6 VMOVHPD	(%R8,%RAX,8),%XMM5,%XMM5    [1]

0x2f89ec MOV	-0x30(%R10,%RDX,8),%RAX    [2]

0x2f89f1 VMOVSD	(%R8,%RAX,8),%XMM6    [1]

0x2f89f7 MOV	-0x28(%R10,%RDX,8),%RAX    [2]

0x2f89fc VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

0x2f8a02 VFNMADD231PD	-0x60(%R9,%RDX,8),%YMM4,%YMM0    [3]

0x2f8a09 VMOVHPD	(%R8,%RAX,8),%XMM6,%XMM6    [1]

0x2f8a0f MOV	-0x40(%R10,%RDX,8),%RAX    [2]

0x2f8a14 VMOVSD	(%R8,%RAX,8),%XMM7    [1]

0x2f8a1a MOV	-0x38(%R10,%RDX,8),%RAX    [2]

0x2f8a1f VMOVHPD	(%R8,%RAX,8),%XMM7,%XMM7    [1]

0x2f8a25 MOV	-0x10(%R10,%RDX,8),%RAX    [2]

0x2f8a2a VMOVSD	(%R8,%RAX,8),%XMM8    [1]

0x2f8a30 MOV	-0x8(%R10,%RDX,8),%RAX    [2]

0x2f8a35 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM5

0x2f8a3b VFNMADD231PD	-0x40(%R9,%RDX,8),%YMM5,%YMM1    [3]

0x2f8a42 VMOVHPD	(%R8,%RAX,8),%XMM8,%XMM8    [1]

0x2f8a48 MOV	-0x20(%R10,%RDX,8),%RAX    [2]

0x2f8a4d VMOVSD	(%R8,%RAX,8),%XMM9    [1]

0x2f8a53 MOV	-0x18(%R10,%RDX,8),%RAX    [2]

0x2f8a58 VMOVHPD	(%R8,%RAX,8),%XMM9,%XMM9    [1]

0x2f8a5e MOV	0x10(%R10,%RDX,8),%RAX    [2]

0x2f8a63 VMOVSD	(%R8,%RAX,8),%XMM10    [1]

0x2f8a69 MOV	0x18(%R10,%RDX,8),%RAX    [2]

0x2f8a6e VINSERTF128	$0x1,%XMM8,%YMM9,%YMM6

0x2f8a74 VFNMADD231PD	-0x20(%R9,%RDX,8),%YMM6,%YMM2    [3]

0x2f8a7b VMOVHPD	(%R8,%RAX,8),%XMM10,%XMM10    [1]

0x2f8a81 MOV	(%R10,%RDX,8),%RAX    [2]

0x2f8a85 VMOVSD	(%R8,%RAX,8),%XMM11    [1]

0x2f8a8b MOV	0x8(%R10,%RDX,8),%RAX    [2]

0x2f8a90 VMOVHPD	(%R8,%RAX,8),%XMM11,%XMM11    [1]

0x2f8a96 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM7

0x2f8a9c VFNMADD231PD	(%R9,%RDX,8),%YMM7,%YMM3    [3]

0x2f8aa2 ADD	$0x10,%RDX

0x2f8aa6 CMP	%RDX,%R13

0x2f8aa9 JNE	2f89c0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 310 - 312

--------------------------------------------------------------------------------

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.80
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P6, P7, P8, P9,
Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source	csr_matvec.c:310-312
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	9.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.50
Front-end cycles	5.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	42.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.56
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	33.33
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.80
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P6, P7, P8, P9,
Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source	csr_matvec.c:310-312
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	9.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.50
Front-end cycles	5.25
P0 cycles	0.33
P1 cycles	0.33
P2 cycles	0.33
P3 cycles	0.33
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	9.00
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	42.00
Nb loads	36.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.56
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	16.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	33.33
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	20.83
Vector-efficiency ratio load	20.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source file and lines	csr_matvec.c:310-312
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310-312.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.00 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.00 to 5.25 cycles (1.71x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 16 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	42
loop length	239
used x86 registers	6
used mmx registers	0
used xmm registers	8
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.25
Dispatch	9.00
Data deps.	4.00
Overall L1	9.00

Vectorization ratios

all	33%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	20%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

16% of peak load performance is reached (42.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2f89c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV -0x50(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x48(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x60(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x58(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x30(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x28(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x60(%R9,%RDX,8),%YMM4,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x40(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x38(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x10(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x8(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x40(%R9,%RDX,8),%YMM5,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x20(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x18(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV 0x10(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM8,%YMM9,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x20(%R9,%RDX,8),%YMM6,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV (%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM10,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD (%R9,%RDX,8),%YMM7,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 2f89c0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18+0x9c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source file and lines	csr_matvec.c:310-312
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.00 to 5.00 cycles (1.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

20% of SSE/AVX loads are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 16 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:312
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

4 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction (all inside FMA instructions)
16: multiply (all inside FMA instructions)

The binary loop is loading 384 bytes (48 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	42
loop length	239
used x86 registers	6
used mmx registers	0
used xmm registers	8
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	4.00	4.00	4.00	4.00	0.00	0.00
cycles	0.33	0.33	0.33	0.33	0.33	0.33	9.00	9.00	9.00	9.00	4.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.25
Dispatch	9.00
Data deps.	4.00
Overall L1	9.00

Vectorization ratios

all	33%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	20%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

16% of peak load performance is reached (42.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2f89c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
MOV -0x50(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x48(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x60(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x58(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x30(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x28(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x60(%R9,%RDX,8),%YMM4,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x40(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x38(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x10(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x8(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x40(%R9,%RDX,8),%YMM5,%YMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV -0x20(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV -0x18(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV 0x10(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM8,%YMM9,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD -0x20(%R9,%RDX,8),%YMM6,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R8,%RAX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
MOV (%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD (%R8,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x8(%R10,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM10,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	0.50	vect (25.0%)
VFNMADD231PD (%R9,%RDX,8),%YMM7,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	4	0.50	vect (50.0%)
ADD $0x10,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RDX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 2f89c0 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18+0x9c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code