OV - exec - Loop 2914

	Loop Id: 2914	Module: exec	Source: par_csr_matop.c:937-989 [...]	Coverage: 0.30%

0x2d79d0 MOV	-0x50(%RBP),%R9

0x2d79d4 MOV	-0x58(%RBP),%RAX

0x2d79d8 INC	%R8

0x2d79db CMP	%R8,(%RAX,%R9,8)

0x2d79df JLE	2d7730

0x2d79e5 MOV	-0x90(%RBP),%RAX

0x2d79ec MOV	-0x140(%RBP),%RDX

0x2d79f3 MOV	-0x78(%RBP),%RCX

0x2d79f7 MOV	(%RAX,%R8,8),%R9

0x2d79fb VMOVSD	(%RDX,%R8,8),%XMM0

0x2d7a01 MOV	(%RCX,%R9,8),%RSI

0x2d7a05 MOV	0x8(%RCX,%R9,8),%RCX

0x2d7a0a CMP	%RCX,%RSI

0x2d7a0d JGE	2d7a85

0x2d7a0f MOV	-0x80(%RBP),%R10

0x2d7a13 MOV	-0x128(%RBP),%RAX

0x2d7a1a MOV	-0x88(%RBP),%R11

0x2d7a21 MOV	(%RAX),%RDX

0x2d7a24 MOV	(%R10),%R10

0x2d7a27 MOV	(%R11),%RAX

0x2d7a2a MOV	%RAX,-0x38(%RBP)

0x2d7a2e JMP	2d7a49

  (2916) 0x2d7a30 VMOVSD	(%RDX,%RSI,8),%XMM1

  (2916) 0x2d7a35 VFMADD213SD	(%R10,%R11,8),%XMM0,%XMM1

  (2916) 0x2d7a3b VMOVSD	%XMM1,(%R10,%R11,8)

  (2916) 0x2d7a41 INC	%RSI

  (2916) 0x2d7a44 CMP	%RCX,%RSI

  (2916) 0x2d7a47 JGE	2d7a85

  (2916) 0x2d7a49 MOV	-0x40(%RBP),%RAX

  (2916) 0x2d7a4d MOV	(%RAX,%RSI,8),%RAX

  (2916) 0x2d7a51 MOV	(%RDI,%RAX,8),%R11

  (2916) 0x2d7a55 CMP	%R12,%R11

  (2916) 0x2d7a58 JGE	2d7a30

  (2916) 0x2d7a5a MOV	%R13,(%RDI,%RAX,8)

  (2916) 0x2d7a5e MOV	-0x38(%RBP),%RCX

  (2916) 0x2d7a62 VMULSD	(%RDX,%RSI,8),%XMM0,%XMM1

  (2916) 0x2d7a67 VMOVSD	%XMM1,(%R10,%R13,8)

  (2916) 0x2d7a6d MOV	%RAX,(%RCX,%R13,8)

  (2916) 0x2d7a71 MOV	-0x78(%RBP),%RCX

  (2916) 0x2d7a75 INC	%R13

  (2916) 0x2d7a78 MOV	0x8(%RCX,%R9,8),%RCX

  (2916) 0x2d7a7d INC	%RSI

  (2916) 0x2d7a80 CMP	%RCX,%RSI

  (2916) 0x2d7a83 JL	2d7a49

0x2d7a85 MOV	-0x148(%RBP),%RAX

0x2d7a8c CMPQ	$0,(%RAX)

0x2d7a90 JE	2d79d0

0x2d7a96 MOV	-0x70(%RBP),%RAX

0x2d7a9a MOV	(%RAX,%R9,8),%R10

0x2d7a9e MOV	0x8(%RAX,%R9,8),%R11

0x2d7aa3 CMP	%R11,%R10

0x2d7aa6 JGE	2d79d0

0x2d7aac MOV	-0xa0(%RBP),%RDX

0x2d7ab3 MOV	-0x120(%RBP),%RAX

0x2d7aba MOV	-0xa8(%RBP),%RCX

0x2d7ac1 MOV	(%RAX),%RSI

0x2d7ac4 MOV	(%RDX),%RDX

0x2d7ac7 MOV	(%RCX),%RAX

0x2d7aca MOV	%RAX,-0x38(%RBP)

0x2d7ace JMP	2d7aed

  (2915) 0x2d7ad0 VMOVSD	(%RSI,%R10,8),%XMM1

  (2915) 0x2d7ad6 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM1

  (2915) 0x2d7adc VMOVSD	%XMM1,(%RDX,%RAX,8)

  (2915) 0x2d7ae1 INC	%R10

  (2915) 0x2d7ae4 CMP	%R11,%R10

  (2915) 0x2d7ae7 JGE	2d79d0

  (2915) 0x2d7aed MOV	-0x30(%RBP),%RAX

  (2915) 0x2d7af1 MOV	-0x48(%RBP),%RCX

  (2915) 0x2d7af5 MOV	(%RAX,%R10,8),%RAX

  (2915) 0x2d7af9 MOV	(%RCX,%RAX,8),%RCX

  (2915) 0x2d7afd ADD	(%RBX),%RCX

  (2915) 0x2d7b00 MOV	(%RDI,%RCX,8),%RAX

  (2915) 0x2d7b04 CMP	%R15,%RAX

  (2915) 0x2d7b07 JGE	2d7ad0

  (2915) 0x2d7b09 MOV	%R14,(%RDI,%RCX,8)

  (2915) 0x2d7b0d MOV	-0x38(%RBP),%RAX

  (2915) 0x2d7b11 VMULSD	(%RSI,%R10,8),%XMM0,%XMM1

  (2915) 0x2d7b17 VMOVSD	%XMM1,(%RDX,%R14,8)

  (2915) 0x2d7b1d SUB	(%RBX),%RCX

  (2915) 0x2d7b20 MOV	%RCX,(%RAX,%R14,8)

  (2915) 0x2d7b24 MOV	-0x70(%RBP),%RCX

  (2915) 0x2d7b28 INC	%R14

  (2915) 0x2d7b2b MOV	0x8(%RCX,%R9,8),%R11

  (2915) 0x2d7b30 INC	%R10

  (2915) 0x2d7b33 CMP	%R11,%R10

  (2915) 0x2d7b36 JL	2d7aed

0x2d7b38 JMP	2d79d0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 937 - 989

--------------------------------------------------------------------------------

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	4.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	0.91
Front-end cycles	4.88
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	27.00
Nb stores	2.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	216.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	4.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.49
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	0.91
Front-end cycles	4.88
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	2.33
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	7.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	27.00
Nb stores	2.00
Nb stack references	14.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	216.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:937-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 1.50 cycles (4.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 0.91 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 4.88 cycles (1.49x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 216 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	39
nb uops	39
loop length	176
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.33	2.33	2.33	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	2.33	2.33	2.33	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	7.25
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

11% of peak load performance is reached (29.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.21 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2d79e5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 2d7730 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD (%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV (%RCX,%R9,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JGE 2d7a85 <hypre_ParMatmul.omp_outlined.7+0x625>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x128(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d7a49 <hypre_ParMatmul.omp_outlined.7+0x5e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x148(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R9,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RAX,%R9,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x120(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d7aed <hypre_ParMatmul.omp_outlined.7+0x68d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:937-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 1.50 cycles (4.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 0.91 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.25 to 4.88 cycles (1.49x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 216 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	39
nb uops	39
loop length	176
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	2.33	2.33	2.33	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	2.33	2.33	2.33	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	7.25
Overall L1	7.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

11% of peak load performance is reached (29.79 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.21 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2d79e5

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 2d7730 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x90(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD (%RDX,%R8,8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV (%RCX,%R9,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x8(%RCX,%R9,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JGE 2d7a85 <hypre_ParMatmul.omp_outlined.7+0x625>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x128(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x88(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d7a49 <hypre_ParMatmul.omp_outlined.7+0x5e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x148(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%R9,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RAX,%R9,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xa0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x120(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d7aed <hypre_ParMatmul.omp_outlined.7+0x68d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
JMP 2d79d0 <hypre_ParMatmul.omp_outlined.7+0x570>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code