OV - exec - Loop 1248

	Loop Id: 1248	Module: exec	Source: par_lr_interp.c:1609-1675 [...]	Coverage: 0.04%

0x27cbc0 MOV	0x48(%RSP),%RDX

0x27cbc5 VMOVSD	(%R14,%RCX,8),%XMM13

0x27cbcb VADDSD	(%RDX,%R11,8),%XMM13,%XMM13

0x27cbd1 VMOVSD	%XMM13,(%R14,%RCX,8)

0x27cbd7 INC	%R11

0x27cbda CMP	%RBX,%R11

0x27cbdd JE	27dd33

0x27cbe3 MOV	0xa0(%RSP),%RCX

0x27cbeb MOV	(%RCX,%R11,8),%RDX

0x27cbef MOV	(%R15,%RDX,8),%RCX

0x27cbf3 CMP	%R9,%RCX

0x27cbf6 JGE	27cbc0

0x27cbf8 MOV	%RDX,0x98(%RSP)

0x27cc00 CMP	%RCX,0x70(%RSP)

0x27cc05 JNE	27cc80

0x27cc07 MOV	%R11,0x90(%RSP)

0x27cc0f VMOVAPD	%XMM6,%XMM13

0x27cc13 MOV	0x1a0(%RSP),%RSI

0x27cc1b MOV	0x98(%RSP),%RDX

0x27cc23 MOV	0xa8(%RSP),%RCX

0x27cc2b MOV	(%RSI,%RDX,8),%R8

0x27cc2f MOV	0x8(%RSI,%RDX,8),%R11

0x27cc34 MOV	0x48(%RSP),%RDX

0x27cc39 VMOVQ	(%RCX),%XMM14

0x27cc3d VCMPSD	$0xe,(%RDX,%R8,8),%XMM5,%K1

0x27cc45 LEA	0x1(%R8),%R14

0x27cc49 MOV	%R11,0x30(%RSP)

0x27cc4e VMOVSD	-0x6d9b0(%RIP),%XMM13{%K1}

0x27cc58 CMP	%R11,%R14

0x27cc5b JGE	27d3b0

0x27cc61 MOV	%R8,%RCX

0x27cc64 NOT	%RCX

0x27cc67 ADD	%R11,%RCX

0x27cc6a CMP	$0x4,%RCX

0x27cc6e JAE	27cccf

0x27cc70 MOV	%R14,%RCX

0x27cc73 JMP	27dcac

0x27cc80 MOV	0x78(%RSP),%RCX

0x27cc85 MOV	0x98(%RSP),%RDX

0x27cc8d CMPQ	$-0x3,(%RCX,%RDX,8)

0x27cc92 JE	27cbd7

0x27cc98 CMPQ	$0x1,0x1d0(%RSP)

0x27cca1 JE	27ccbf

0x27cca3 MOV	0x1f0(%RSP),%R8

0x27ccab MOV	%RDX,%RCX

0x27ccae MOV	%RCX,%RSI

0x27ccb1 MOV	(%R8,%R13,8),%RCX

0x27ccb5 CMP	%RCX,(%R8,%RSI,8)

0x27ccb9 JNE	27cbd7

0x27ccbf MOV	0x48(%RSP),%RCX

0x27ccc4 VADDSD	(%RCX,%R11,8),%XMM8,%XMM8

0x27ccca JMP	27cbd7

0x27cccf CMP	$0x20,%RCX

0x27ccd3 JAE	27ccdc

0x27ccd5 XOR	%ESI,%ESI

0x27ccd7 JMP	27d280

0x27ccdc VBROADCASTSD	%XMM13,%ZMM0

0x27cce2 VMOVSD	%XMM8,0x110(%RSP)

0x27cceb MOV	%RCX,%RSI

0x27ccee MOV	%RCX,%RBX

0x27ccf1 AND	$-0x20,%RSI

0x27ccf5 VMOVQ	%XMM14,%XMM6

0x27ccf9 VXORPD	%XMM16,%XMM16,%XMM16

0x27ccff VXORPD	%XMM18,%XMM18,%XMM18

0x27cd05 VXORPD	%XMM17,%XMM17,%XMM17

0x27cd0b VMOVAPD	%ZMM0,0x340(%RSP)

0x27cd13 MOV	0x310(%RSP),%RCX

0x27cd1b MOV	0x308(%RSP),%RDX

0x27cd23 MOV	%R8,0x148(%RSP)

0x27cd2b LEA	(%RCX,%R8,8),%RCX

0x27cd2f LEA	(%RDX,%R8,8),%R10

0x27cd33 XOR	%R8D,%R8D

0x27cd36 JMP	27cd93

  (1256) 0x27cd40 KORB	%K5,%K4,%K4

  (1256) 0x27cd44 KORB	%K0,%K2,%K2

  (1256) 0x27cd48 KORB	%K3,%K1,%K1

  (1256) 0x27cd4c ADD	$0x20,%R8

  (1256) 0x27cd50 VMOVAPD	%ZMM6,%ZMM23{%K4}

  (1256) 0x27cd56 KMOVW	0x50(%RSP),%K4

  (1256) 0x27cd5c VMOVAPD	%ZMM18,%ZMM25{%K2}

  (1256) 0x27cd62 VMOVAPD	%ZMM17,%ZMM26{%K1}

  (1256) 0x27cd68 VMOVAPD	%ZMM23,%ZMM6

  (1256) 0x27cd6e VMOVAPD	%ZMM25,%ZMM18

  (1256) 0x27cd74 VMOVAPD	%ZMM26,%ZMM17

  (1256) 0x27cd7a KORB	%K4,%K6,%K4

  (1256) 0x27cd7e VMOVAPD	%ZMM16,%ZMM24{%K4}

  (1256) 0x27cd84 VMOVAPD	%ZMM24,%ZMM16

  (1256) 0x27cd8a CMP	%R8,%RSI

  (1256) 0x27cd8d JE	27d1a0

  (1256) 0x27cd93 MOV	-0x88(%RCX,%R8,8),%RDX

  (1256) 0x27cd9b VMOVQ	(%R15,%RDX,8),%XMM25

  (1256) 0x27cda2 MOV	-0x90(%RCX,%R8,8),%RDX

  (1256) 0x27cdaa VMOVQ	(%R15,%RDX,8),%XMM30

  (1256) 0x27cdb1 MOV	-0x98(%RCX,%R8,8),%RDX

  (1256) 0x27cdb9 VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27cdbf MOV	-0xa0(%RCX,%R8,8),%RDX

  (1256) 0x27cdc7 VPUNPCKLQDQ	%XMM25,%XMM30,%XMM30

  (1256) 0x27cdcd VMOVAPS	%XMM0,0x60(%RSP)

  (1256) 0x27cdd3 VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27cdd9 MOV	-0xa8(%RCX,%R8,8),%RDX

  (1256) 0x27cde1 VMOVAPS	%XMM0,0x50(%RSP)

  (1256) 0x27cde7 VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27cded MOV	-0xb0(%RCX,%R8,8),%RDX

  (1256) 0x27cdf5 VMOVAPS	%XMM0,0xc0(%RSP)

  (1256) 0x27cdfe VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27ce04 MOV	-0xb8(%RCX,%R8,8),%RDX

  (1256) 0x27ce0c VMOVAPS	%XMM0,0x100(%RSP)

  (1256) 0x27ce15 VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27ce1b MOV	-0xc0(%RCX,%R8,8),%RDX

  (1256) 0x27ce23 VMOVQ	(%R15,%RDX,8),%XMM26

  (1256) 0x27ce2a MOV	-0x48(%RCX,%R8,8),%RDX

  (1256) 0x27ce2f VMOVAPS	%XMM0,0x130(%RSP)

  (1256) 0x27ce38 VMOVSD	(%R15,%RDX,8),%XMM0

  (1256) 0x27ce3e MOV	-0x50(%RCX,%R8,8),%RDX

  (1256) 0x27ce43 VMOVQ	(%R15,%RDX,8),%XMM23

  (1256) 0x27ce4a MOV	-0x58(%RCX,%R8,8),%RDX

  (1256) 0x27ce4f VMOVAPS	%XMM0,0x240(%RSP)

  (1256) 0x27ce58 VMOVDQA64	0x50(%RSP),%XMM25

  (1256) 0x27ce60 VPUNPCKLQDQ	0x130(%RSP),%XMM26,%XMM26

  (1256) 0x27ce68 VPUNPCKLQDQ	0x240(%RSP),%XMM23,%XMM23

  (1256) 0x27ce70 VMOVQ	(%R15,%RDX,8),%XMM24

  (1256) 0x27ce77 MOV	-0x60(%RCX,%R8,8),%RDX

  (1256) 0x27ce7c VPUNPCKLQDQ	0x60(%RSP),%XMM25,%XMM25

  (1256) 0x27ce84 VMOVQ	(%R15,%RDX,8),%XMM21

  (1256) 0x27ce8b MOV	-0x68(%RCX,%R8,8),%RDX

  (1256) 0x27ce90 VINSERTI32X4	$0x1,%XMM30,%YMM25,%YMM25

  (1256) 0x27ce97 VMOVDQA64	0x100(%RSP),%XMM30

  (1256) 0x27ce9f VPUNPCKLQDQ	0xc0(%RSP),%XMM30,%XMM30

  (1256) 0x27cea7 VMOVQ	(%R15,%RDX,8),%XMM22

  (1256) 0x27ceae MOV	-0x70(%RCX,%R8,8),%RDX

  (1256) 0x27ceb3 VPUNPCKLQDQ	%XMM24,%XMM21,%XMM21

  (1256) 0x27ceb9 VINSERTI32X4	$0x1,%XMM23,%YMM21,%YMM21

  (1256) 0x27cec0 VMOVQ	(%R15,%RDX,8),%XMM19

  (1256) 0x27cec7 MOV	-0x78(%RCX,%R8,8),%RDX

  (1256) 0x27cecc VINSERTI32X4	$0x1,%XMM30,%YMM26,%YMM26

  (1256) 0x27ced3 VINSERTI64X4	$0x1,%YMM25,%ZMM26,%ZMM25

  (1256) 0x27ceda VPCMPNLTQ	%ZMM9,%ZMM25,%K4

  (1256) 0x27cee1 VMOVQ	(%R15,%RDX,8),%XMM20

  (1256) 0x27cee8 MOV	-0x80(%RCX,%R8,8),%RDX

  (1256) 0x27ceed VPUNPCKLQDQ	%XMM22,%XMM19,%XMM19

  (1256) 0x27cef3 VMOVQ	(%R15,%RDX,8),%XMM2

  (1256) 0x27cef9 MOV	-0x8(%RCX,%R8,8),%RDX

  (1256) 0x27cefe VMOVQ	(%R15,%RDX,8),%XMM4

  (1256) 0x27cf04 MOV	-0x10(%RCX,%R8,8),%RDX

  (1256) 0x27cf09 VPUNPCKLQDQ	%XMM20,%XMM2,%XMM2

  (1256) 0x27cf0f VINSERTI32X4	$0x1,%XMM19,%YMM2,%YMM2

  (1256) 0x27cf16 VMOVQ	(%R15,%RDX,8),%XMM11

  (1256) 0x27cf1c MOV	-0x18(%RCX,%R8,8),%RDX

  (1256) 0x27cf21 VINSERTI64X4	$0x1,%YMM21,%ZMM2,%ZMM2

  (1256) 0x27cf28 VPCMPNLTQ	%ZMM9,%ZMM2,%K1

  (1256) 0x27cf2f VMOVQ	(%R15,%RDX,8),%XMM7

  (1256) 0x27cf35 MOV	-0x20(%RCX,%R8,8),%RDX

  (1256) 0x27cf3a VPUNPCKLQDQ	%XMM4,%XMM11,%XMM4

  (1256) 0x27cf3e VMOVQ	(%R15,%RDX,8),%XMM1

  (1256) 0x27cf44 MOV	-0x28(%RCX,%R8,8),%RDX

  (1256) 0x27cf49 VMOVQ	(%R15,%RDX,8),%XMM3

  (1256) 0x27cf4f MOV	-0x30(%RCX,%R8,8),%RDX

  (1256) 0x27cf54 VPUNPCKLQDQ	%XMM7,%XMM1,%XMM1

  (1256) 0x27cf58 VINSERTI128	$0x1,%XMM4,%YMM1,%YMM1

  (1256) 0x27cf5e VMOVQ	(%R15,%RDX,8),%XMM10

  (1256) 0x27cf64 MOV	-0x38(%RCX,%R8,8),%RDX

  (1256) 0x27cf69 VMOVQ	(%R15,%RDX,8),%XMM5

  (1256) 0x27cf6f MOV	-0x40(%RCX,%R8,8),%RDX

  (1256) 0x27cf74 VPUNPCKLQDQ	%XMM3,%XMM10,%XMM3

  (1256) 0x27cf78 VMOVQ	(%R15,%RDX,8),%XMM31

  (1256) 0x27cf7f MOV	0x38(%RCX,%R8,8),%RDX

  (1256) 0x27cf84 VMOVQ	(%R15,%RDX,8),%XMM8

  (1256) 0x27cf8a MOV	0x30(%RCX,%R8,8),%RDX

  (1256) 0x27cf8f VPUNPCKLQDQ	%XMM5,%XMM31,%XMM4

  (1256) 0x27cf95 VINSERTI128	$0x1,%XMM3,%YMM4,%YMM3

  (1256) 0x27cf9b VMOVQ	(%R15,%RDX,8),%XMM14

  (1256) 0x27cfa1 MOV	0x28(%RCX,%R8,8),%RDX

  (1256) 0x27cfa6 VINSERTI64X4	$0x1,%YMM1,%ZMM3,%ZMM1

  (1256) 0x27cfad VPCMPNLTQ	%ZMM9,%ZMM1,%K2

  (1256) 0x27cfb4 VMOVDQA64	0x380(%RSP),%ZMM1

  (1256) 0x27cfbc VPCMPEQQ	-0xc0(%RCX,%R8,8),%ZMM1,%K3

  (1256) 0x27cfc4 VPCMPEQQ	-0x80(%RCX,%R8,8),%ZMM1,%K6

  (1256) 0x27cfcc VPCMPEQQ	-0x40(%RCX,%R8,8),%ZMM1,%K7

  (1256) 0x27cfd4 VPCMPEQQ	(%RCX,%R8,8),%ZMM1,%K0

  (1256) 0x27cfdb VMOVQ	(%R15,%RDX,8),%XMM12

  (1256) 0x27cfe1 MOV	0x20(%RCX,%R8,8),%RDX

  (1256) 0x27cfe6 VPUNPCKLQDQ	%XMM8,%XMM14,%XMM3

  (1256) 0x27cfeb VMOVQ	(%R15,%RDX,8),%XMM0

  (1256) 0x27cff1 MOV	0x18(%RCX,%R8,8),%RDX

  (1256) 0x27cff6 KORB	%K4,%K3,%K4

  (1256) 0x27cffa KORB	%K1,%K6,%K3

  (1256) 0x27cffe KORB	%K2,%K7,%K2

  (1256) 0x27d002 VMOVQ	(%R15,%RDX,8),%XMM15

  (1256) 0x27d008 MOV	0x10(%RCX,%R8,8),%RDX

  (1256) 0x27d00d VPUNPCKLQDQ	%XMM12,%XMM0,%XMM0

  (1256) 0x27d012 VINSERTI128	$0x1,%XMM3,%YMM0,%YMM0

  (1256) 0x27d018 VMOVQ	(%R15,%RDX,8),%XMM27

  (1256) 0x27d01f MOV	0x8(%RCX,%R8,8),%RDX

  (1256) 0x27d024 VMOVQ	(%R15,%RDX,8),%XMM28

  (1256) 0x27d02b MOV	(%RCX,%R8,8),%RDX

  (1256) 0x27d02f VPUNPCKLQDQ	%XMM15,%XMM27,%XMM3

  (1256) 0x27d035 VMOVQ	(%R15,%RDX,8),%XMM29

  (1256) 0x27d03c VPUNPCKLQDQ	%XMM28,%XMM29,%XMM4

  (1256) 0x27d042 VINSERTI128	$0x1,%XMM3,%YMM4,%YMM3

  (1256) 0x27d048 VINSERTI64X4	$0x1,%YMM0,%ZMM3,%ZMM0

  (1256) 0x27d04f VPCMPNLTQ	%ZMM9,%ZMM0,%K5

  (1256) 0x27d056 KORB	%K5,%K0,%K1

  (1256) 0x27d05a KUNPCKBW	%K4,%K3,%K0

  (1256) 0x27d05e KUNPCKWD	%K0,%K2,%K0

  (1256) 0x27d062 VPMOVM2W	%K1,%ZMM1

  (1256) 0x27d068 VPMOVM2W	%K0,%ZMM0

  (1256) 0x27d06e VINSERTI32X4	$0x3,%XMM1,%ZMM0,%ZMM0

  (1256) 0x27d075 VPMOVW2M	%ZMM0,%K0

  (1256) 0x27d07b KORTESTD	%K0,%K0

  (1256) 0x27d080 KMOVD	%K0,0x50(%RSP)

  (1256) 0x27d087 JE	27d0f8

  (1256) 0x27d089 VMOVUPD	-0x40(%R10,%R8,8),%ZMM21{%K2}{z}

  (1256) 0x27d091 VMOVAPD	0x340(%RSP),%ZMM3

  (1256) 0x27d099 VMOVUPD	-0xc0(%R10,%R8,8),%ZMM19{%K4}{z}

  (1256) 0x27d0a1 VMOVUPD	-0x80(%R10,%R8,8),%ZMM20{%K3}{z}

  (1256) 0x27d0a9 VMOVUPD	(%R10,%R8,8),%ZMM22{%K1}{z}

  (1256) 0x27d0b0 VPXOR	%XMM4,%XMM4,%XMM4

  (1256) 0x27d0b4 VMULPD	%ZMM3,%ZMM21,%ZMM2

  (1256) 0x27d0ba VMULPD	%ZMM3,%ZMM19,%ZMM0

  (1256) 0x27d0c0 VMULPD	%ZMM3,%ZMM20,%ZMM1

  (1256) 0x27d0c6 VMULPD	%ZMM3,%ZMM22,%ZMM3

  (1256) 0x27d0cc VCMPPD	$0x1,%ZMM4,%ZMM2,%K0

  (1256) 0x27d0d3 VCMPPD	$0x1,%ZMM4,%ZMM0,%K5

  (1256) 0x27d0da VCMPPD	$0x1,%ZMM4,%ZMM1,%K6

  (1256) 0x27d0e1 KMOVW	%K0,0x60(%RSP)

  (1256) 0x27d0e7 VCMPPD	$0x1,%ZMM4,%ZMM3,%K0

  (1256) 0x27d0ee KMOVQ	%K0,0x100(%RSP)

  (1256) 0x27d0f8 KMOVW	%K6,0xc0(%RSP)

  (1256) 0x27d101 KMOVQ	%K5,%K0

  (1256) 0x27d106 KUNPCKBW	%K5,%K6,%K5

  (1256) 0x27d10a KMOVW	0x60(%RSP),%K7

  (1256) 0x27d110 KMOVD	0x50(%RSP),%K6

  (1256) 0x27d117 KUNPCKWD	%K5,%K7,%K5

  (1256) 0x27d11b KMOVQ	%K1,%K7

  (1256) 0x27d120 KMOVQ	0x100(%RSP),%K1

  (1256) 0x27d12a VPMOVM2W	%K5,%ZMM0

  (1256) 0x27d130 VPMOVM2W	%K1,%ZMM1

  (1256) 0x27d136 VINSERTI32X4	$0x3,%XMM1,%ZMM0,%ZMM0

  (1256) 0x27d13d VPMOVW2M	%ZMM0,%K5

  (1256) 0x27d143 KTESTD	%K6,%K5

  (1256) 0x27d148 KANDNB	%K4,%K0,%K5

  (1256) 0x27d14c KMOVW	0xc0(%RSP),%K0

  (1256) 0x27d155 KNOTB	%K4,%K4

  (1256) 0x27d159 KNOTB	%K3,%K6

  (1256) 0x27d15d KANDNB	%K3,%K0,%K0

  (1256) 0x27d161 KANDNB	%K7,%K1,%K3

  (1256) 0x27d165 KNOTB	%K7,%K1

  (1256) 0x27d169 KMOVW	%K0,0x50(%RSP)

  (1256) 0x27d16f KMOVW	0x60(%RSP),%K0

  (1256) 0x27d175 KANDNB	%K2,%K0,%K0

  (1256) 0x27d179 KNOTB	%K2,%K2

  (1256) 0x27d17d JE	27cd40

  (1256) 0x27d183 VADDPD	%ZMM6,%ZMM19,%ZMM23

  (1256) 0x27d189 VADDPD	%ZMM16,%ZMM20,%ZMM24

  (1256) 0x27d18f VADDPD	%ZMM18,%ZMM21,%ZMM25

  (1256) 0x27d195 VADDPD	%ZMM17,%ZMM22,%ZMM26

  (1256) 0x27d19b JMP	27cd40

0x27d1a0 VADDPD	%ZMM23,%ZMM24,%ZMM0

0x27d1a6 VADDPD	%ZMM25,%ZMM26,%ZMM1

0x27d1ac VADDPD	%ZMM0,%ZMM1,%ZMM0

0x27d1b2 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x27d1b9 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x27d1bf VEXTRACTF128	$0x1,%YMM0,%XMM1

0x27d1c5 VADDPD	%XMM1,%XMM0,%XMM0

0x27d1c9 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x27d1ce VADDSD	%XMM1,%XMM0,%XMM14

0x27d1d2 CMP	%RSI,%RBX

0x27d1d5 JNE	27d228

0x27d1d7 VMOVDQA64	0x400(%RSP),%ZMM3

0x27d1df VMOVDQA	-0x6dd47(%RIP),%XMM4

0x27d1e7 VMOVSD	-0x6dec7(%RIP),%XMM6

0x27d1ef VMOVAPD	0x2a0(%RSP),%YMM7

0x27d1f8 VMOVSD	0x110(%RSP),%XMM8

0x27d201 VMOVDQA	0x2c0(%RSP),%YMM11

0x27d20a VMOVDQA64	0x3c0(%RSP),%ZMM12

0x27d212 MOV	0xd8(%RSP),%R10

0x27d21a VPXOR	%XMM5,%XMM5,%XMM5

0x27d21e VPXOR	%XMM10,%XMM10,%XMM10

0x27d223 JMP	27d3b0

0x27d228 MOV	%RBX,%RCX

0x27d22b TEST	$0x1c,%CL

0x27d22e JE	27dc47

0x27d234 VMOVDQA64	0x400(%RSP),%ZMM3

0x27d23c VMOVDQA	-0x6dda4(%RIP),%XMM4

0x27d244 VMOVSD	-0x6df24(%RIP),%XMM6

0x27d24c VMOVDQA	0x2a0(%RSP),%YMM7

0x27d255 VMOVSD	0x110(%RSP),%XMM8

0x27d25e VMOVDQA	0x2c0(%RSP),%YMM11

0x27d267 VMOVDQA64	0x3c0(%RSP),%ZMM12

0x27d26f MOV	0x148(%RSP),%R8

0x27d277 VPXOR	%XMM5,%XMM5,%XMM5

0x27d27b VPXOR	%XMM10,%XMM10,%XMM10

0x27d280 MOV	%RCX,0xc0(%RSP)

0x27d288 AND	$-0x4,%RCX

0x27d28c VBROADCASTSD	%XMM13,%YMM15

0x27d291 VMOVQ	%XMM14,%XMM14

0x27d296 MOV	%RCX,0x60(%RSP)

0x27d29b ADD	%R14,%RCX

0x27d29e MOV	0x328(%RSP),%RDX

0x27d2a6 MOV	0x320(%RSP),%R11

0x27d2ae LEA	(%RDX,%R8,8),%R10

0x27d2b2 LEA	(%R11,%R8,8),%RDX

0x27d2b6 MOV	%RDX,0x50(%RSP)

0x27d2bb JMP	27d306

  (1255) 0x27d2c0 MOV	0x50(%RSP),%RDX

  (1255) 0x27d2c5 VPCMPEQQ	%YMM7,%YMM16,%K1

  (1255) 0x27d2cb VMOVUPD	(%RDX,%RSI,8),%YMM17{%K1}{z}

  (1255) 0x27d2d2 VMULPD	%YMM15,%YMM17,%YMM0

  (1255) 0x27d2d8 VCMPPD	$0x1,%YMM10,%YMM0,%YMM0

  (1255) 0x27d2de VANDPD	%YMM7,%YMM0,%YMM18

  (1255) 0x27d2e4 VPCMPEQQ	%YMM7,%YMM18,%K1

  (1255) 0x27d2ea MOV	0x30(%RSP),%R11

  (1255) 0x27d2ef ADD	$0x4,%RSI

  (1255) 0x27d2f3 VPCMPEQQ	%YMM7,%YMM16,%K1{%K1}

  (1255) 0x27d2f9 VADDPD	%YMM14,%YMM17,%YMM14{%K1}

  (1255) 0x27d2ff CMP	%RSI,0x60(%RSP)

  (1255) 0x27d304 JE	27d376

  (1255) 0x27d306 MOV	0x10(%R10,%RSI,8),%R8

  (1255) 0x27d30b MOV	0x18(%R10,%RSI,8),%RBX

  (1255) 0x27d310 MOV	(%R10,%RSI,8),%RDX

  (1255) 0x27d314 MOV	0x8(%R10,%RSI,8),%R11

  (1255) 0x27d319 VPCMPEQQ	(%R10,%RSI,8),%YMM11,%K1

  (1255) 0x27d320 VMOVQ	(%R15,%RBX,8),%XMM0

  (1255) 0x27d326 VMOVQ	(%R15,%R8,8),%XMM1

  (1255) 0x27d32c VMOVQ	(%R15,%RDX,8),%XMM2

  (1255) 0x27d332 VPUNPCKLQDQ	%XMM0,%XMM1,%XMM0

  (1255) 0x27d336 VMOVQ	(%R15,%R11,8),%XMM1

  (1255) 0x27d33c VPUNPCKLQDQ	%XMM1,%XMM2,%XMM1

  (1255) 0x27d340 VINSERTI128	$0x1,%XMM0,%YMM1,%YMM0

  (1255) 0x27d346 VPCMPNLTQ	%YMM9,%YMM0,%K0

  (1255) 0x27d34d KORW	%K0,%K1,%K0

  (1255) 0x27d351 VPMOVM2Q	%K0,%YMM0

  (1255) 0x27d357 KMOVD	%K0,%EDX

  (1255) 0x27d35b VPSRLQ	$0x3f,%YMM0,%YMM16

  (1255) 0x27d362 TEST	$0xf,%DL

  (1255) 0x27d365 JNE	27d2c0

  (1255) 0x27d36b VXORPD	%XMM18,%XMM18,%XMM18

  (1255) 0x27d371 JMP	27d2e4

0x27d376 VEXTRACTF128	$0x1,%YMM14,%XMM0

0x27d37c MOV	0x60(%RSP),%RDX

0x27d381 MOV	0xd8(%RSP),%R10

0x27d389 VADDPD	%XMM0,%XMM14,%XMM0

0x27d38d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x27d392 VADDSD	%XMM1,%XMM0,%XMM14

0x27d396 CMP	%RDX,0xc0(%RSP)

0x27d39e JNE	27dcac

0x27d3a4 NOPW	%CS:(%RAX,%RAX,1)

0x27d3b0 CMP	$0x2,%R10

0x27d3b4 JL	27dae0

0x27d3ba MOV	0x198(%RSP),%RCX

0x27d3c2 MOV	0x98(%RSP),%RDX

0x27d3ca MOV	(%RCX,%RDX,8),%RBX

0x27d3ce MOV	0x8(%RCX,%RDX,8),%RSI

0x27d3d3 MOV	%RSI,%RDX

0x27d3d6 SUB	%RBX,%RDX

0x27d3d9 JLE	27dae0

0x27d3df MOV	0x1f8(%RSP),%RCX

0x27d3e7 MOV	(%RCX),%R8

0x27d3ea CMP	$0x4,%RDX

0x27d3ee JAE	27d3f8

0x27d3f0 MOV	%RBX,%RCX

0x27d3f3 JMP	27dd0c

0x27d3f8 MOV	%RSI,0x148(%RSP)

0x27d400 MOV	%R8,0x340(%RSP)

0x27d408 CMP	$0x20,%RDX

0x27d40c JAE	27d416

0x27d40e XOR	%R10D,%R10D

0x27d411 JMP	27d9a7

0x27d416 VBROADCASTSD	%XMM13,%ZMM0

0x27d41c VMOVDQA64	%ZMM9,0x440(%RSP)

0x27d424 VMOVSD	%XMM8,0x110(%RSP)

0x27d42d MOV	%RBX,%RSI

0x27d430 LEA	0xc0(%R8,%RSI,8),%R8

0x27d438 MOV	%RDX,%R10

0x27d43b AND	$-0x20,%R10

0x27d43f VMOVQ	%XMM14,%XMM15

0x27d444 VPXORD	%XMM16,%XMM16,%XMM16

0x27d44a VXORPD	%XMM17,%XMM17,%XMM17

0x27d450 VXORPD	%XMM18,%XMM18,%XMM18

0x27d456 MOV	%RDX,%RBX

0x27d459 VMOVAPD	%ZMM0,0x240(%RSP)

0x27d461 MOV	0x38(%RSP),%RCX

0x27d466 MOV	%RSI,0x2e8(%RSP)

0x27d46e LEA	(%RCX,%RSI,8),%RCX

0x27d472 XOR	%ESI,%ESI

0x27d474 JMP	27d4e4

  (1253) 0x27d480 VBLENDMPD	%ZMM23,%ZMM15,%ZMM19{%K5}

  (1253) 0x27d486 KMOVW	0x100(%RSP),%K5

  (1253) 0x27d48f VBLENDMPD	%ZMM24,%ZMM16,%ZMM20{%K6}

  (1253) 0x27d495 ADD	$0x20,%RSI

  (1253) 0x27d499 VMOVAPD	%ZMM15,%ZMM19{%K4}

  (1253) 0x27d49f VMOVAPD	%ZMM16,%ZMM20{%K3}

  (1253) 0x27d4a5 VMOVAPD	%ZMM19,%ZMM15

  (1253) 0x27d4ab VMOVAPD	%ZMM20,%ZMM16

  (1253) 0x27d4b1 VBLENDMPD	%ZMM25,%ZMM17,%ZMM21{%K5}

  (1253) 0x27d4b7 KMOVW	0x50(%RSP),%K5

  (1253) 0x27d4bd VMOVAPD	%ZMM17,%ZMM21{%K2}

  (1253) 0x27d4c3 VMOVAPD	%ZMM21,%ZMM17

  (1253) 0x27d4c9 VBLENDMPD	%ZMM26,%ZMM18,%ZMM22{%K5}

  (1253) 0x27d4cf VMOVAPD	%ZMM18,%ZMM22{%K1}

  (1253) 0x27d4d5 VMOVAPD	%ZMM22,%ZMM18

  (1253) 0x27d4db CMP	%RSI,%R10

  (1253) 0x27d4de JE	27d8bf

  (1253) 0x27d4e4 MOV	0x38(%RCX,%RSI,8),%RDX

  (1253) 0x27d4e9 VMOVQ	(%R12,%RDX,8),%XMM0

  (1253) 0x27d4ef MOV	0x30(%RCX,%RSI,8),%RDX

  (1253) 0x27d4f4 VMOVQ	(%R12,%RDX,8),%XMM24

  (1253) 0x27d4fb MOV	0x28(%RCX,%RSI,8),%RDX

  (1253) 0x27d500 VMOVSD	(%R12,%RDX,8),%XMM1

  (1253) 0x27d506 MOV	0x20(%RCX,%RSI,8),%RDX

  (1253) 0x27d50b VPUNPCKLQDQ	%XMM0,%XMM24,%XMM0

  (1253) 0x27d511 VMOVAPS	%XMM1,0x60(%RSP)

  (1253) 0x27d517 VMOVSD	(%R12,%RDX,8),%XMM1

  (1253) 0x27d51d MOV	0x18(%RCX,%RSI,8),%RDX

  (1253) 0x27d522 VMOVAPS	%XMM1,0x50(%RSP)

  (1253) 0x27d528 VMOVSD	(%R12,%RDX,8),%XMM1

  (1253) 0x27d52e MOV	0x10(%RCX,%RSI,8),%RDX

  (1253) 0x27d533 VMOVAPS	%XMM1,0xc0(%RSP)

  (1253) 0x27d53c VMOVSD	(%R12,%RDX,8),%XMM1

  (1253) 0x27d542 MOV	0x8(%RCX,%RSI,8),%RDX

  (1253) 0x27d547 VMOVAPS	%XMM1,0x100(%RSP)

  (1253) 0x27d550 VMOVSD	(%R12,%RDX,8),%XMM1

  (1253) 0x27d556 MOV	(%RCX,%RSI,8),%RDX

  (1253) 0x27d55a VMOVQ	(%R12,%RDX,8),%XMM23

  (1253) 0x27d561 MOV	0x78(%RCX,%RSI,8),%RDX

  (1253) 0x27d566 VMOVAPS	%XMM1,0x130(%RSP)

  (1253) 0x27d56f VMOVDQA64	0x50(%RSP),%XMM24

  (1253) 0x27d577 VPUNPCKLQDQ	0x130(%RSP),%XMM23,%XMM23

  (1253) 0x27d57f VMOVQ	(%R12,%RDX,8),%XMM6

  (1253) 0x27d585 MOV	0x70(%RCX,%RSI,8),%RDX

  (1253) 0x27d58a VPUNPCKLQDQ	0x60(%RSP),%XMM24,%XMM24

  (1253) 0x27d592 VMOVQ	(%R12,%RDX,8),%XMM7

  (1253) 0x27d598 MOV	0x68(%RCX,%RSI,8),%RDX

  (1253) 0x27d59d VINSERTI32X4	$0x1,%XMM0,%YMM24,%YMM0

  (1253) 0x27d5a4 VMOVDQA64	0x100(%RSP),%XMM24

  (1253) 0x27d5ac VPUNPCKLQDQ	0xc0(%RSP),%XMM24,%XMM24

  (1253) 0x27d5b4 VMOVQ	(%R12,%RDX,8),%XMM8

  (1253) 0x27d5ba MOV	0x60(%RCX,%RSI,8),%RDX

  (1253) 0x27d5bf VMOVQ	(%R12,%RDX,8),%XMM9

  (1253) 0x27d5c5 MOV	0x58(%RCX,%RSI,8),%RDX

  (1253) 0x27d5ca VINSERTI32X4	$0x1,%XMM24,%YMM23,%YMM23

  (1253) 0x27d5d1 VINSERTI64X4	$0x1,%YMM0,%ZMM23,%ZMM23

  (1253) 0x27d5d8 VPUNPCKLQDQ	%XMM6,%XMM7,%XMM0

  (1253) 0x27d5dc VMOVQ	(%R12,%RDX,8),%XMM10

  (1253) 0x27d5e2 MOV	0x50(%RCX,%RSI,8),%RDX

  (1253) 0x27d5e7 VPUNPCKLQDQ	%XMM8,%XMM9,%XMM6

  (1253) 0x27d5ec VINSERTI128	$0x1,%XMM0,%YMM6,%YMM0

  (1253) 0x27d5f2 VMOVQ	(%R12,%RDX,8),%XMM11

  (1253) 0x27d5f8 MOV	0x48(%RCX,%RSI,8),%RDX

  (1253) 0x27d5fd VMOVQ	(%R12,%RDX,8),%XMM12

  (1253) 0x27d603 MOV	0x40(%RCX,%RSI,8),%RDX

  (1253) 0x27d608 VPUNPCKLQDQ	%XMM10,%XMM11,%XMM6

  (1253) 0x27d60d VMOVQ	(%R12,%RDX,8),%XMM21

  (1253) 0x27d614 MOV	0xb8(%RCX,%RSI,8),%RDX

  (1253) 0x27d61c VMOVQ	(%R12,%RDX,8),%XMM22

  (1253) 0x27d623 MOV	0xb0(%RCX,%RSI,8),%RDX

  (1253) 0x27d62b VPUNPCKLQDQ	%XMM12,%XMM21,%XMM7

  (1253) 0x27d631 VMOVDQA64	0x3c0(%RSP),%ZMM12

  (1253) 0x27d639 VINSERTI128	$0x1,%XMM6,%YMM7,%YMM6

  (1253) 0x27d63f VMOVQ	(%R12,%RDX,8),%XMM25

  (1253) 0x27d646 MOV	0xa8(%RCX,%RSI,8),%RDX

  (1253) 0x27d64e VINSERTI64X4	$0x1,%YMM0,%ZMM6,%ZMM24

  (1253) 0x27d655 VMOVQ	(%R12,%RDX,8),%XMM26

  (1253) 0x27d65c MOV	0xa0(%RCX,%RSI,8),%RDX

  (1253) 0x27d664 VPCMPGTQ	%ZMM23,%ZMM12,%K4

  (1253) 0x27d66a VPCMPGTQ	%ZMM24,%ZMM12,%K3

  (1253) 0x27d670 KUNPCKBW	%K4,%K3,%K0

  (1253) 0x27d674 VPUNPCKLQDQ	%XMM22,%XMM25,%XMM0

  (1253) 0x27d67a VMOVQ	(%R12,%RDX,8),%XMM27

  (1253) 0x27d681 MOV	0x98(%RCX,%RSI,8),%RDX

  (1253) 0x27d689 VMOVQ	(%R12,%RDX,8),%XMM28

  (1253) 0x27d690 MOV	0x90(%RCX,%RSI,8),%RDX

  (1253) 0x27d698 VPUNPCKLQDQ	%XMM26,%XMM27,%XMM6

  (1253) 0x27d69e VINSERTI128	$0x1,%XMM0,%YMM6,%YMM0

  (1253) 0x27d6a4 VMOVQ	(%R12,%RDX,8),%XMM29

  (1253) 0x27d6ab MOV	0x88(%RCX,%RSI,8),%RDX

  (1253) 0x27d6b3 VMOVQ	(%R12,%RDX,8),%XMM30

  (1253) 0x27d6ba MOV	0x80(%RCX,%RSI,8),%RDX

  (1253) 0x27d6c2 VPUNPCKLQDQ	%XMM28,%XMM29,%XMM6

  (1253) 0x27d6c8 VMOVQ	(%R12,%RDX,8),%XMM31

  (1253) 0x27d6cf MOV	0xf8(%RCX,%RSI,8),%RDX

  (1253) 0x27d6d7 VMOVQ	(%R12,%RDX,8),%XMM19

  (1253) 0x27d6de MOV	0xf0(%RCX,%RSI,8),%RDX

  (1253) 0x27d6e6 VPUNPCKLQDQ	%XMM30,%XMM31,%XMM7

  (1253) 0x27d6ec VINSERTI128	$0x1,%XMM6,%YMM7,%YMM6

  (1253) 0x27d6f2 VMOVQ	(%R12,%RDX,8),%XMM20

  (1253) 0x27d6f9 MOV	0xe8(%RCX,%RSI,8),%RDX

  (1253) 0x27d701 VINSERTI64X4	$0x1,%YMM0,%ZMM6,%ZMM25

  (1253) 0x27d708 VPCMPGTQ	%ZMM25,%ZMM12,%K2

  (1253) 0x27d70e KUNPCKWD	%K0,%K2,%K0

  (1253) 0x27d712 KMOVW	%K2,0xc0(%RSP)

  (1253) 0x27d71b VMOVQ	(%R12,%RDX,8),%XMM5

  (1253) 0x27d721 MOV	0xe0(%RCX,%RSI,8),%RDX

  (1253) 0x27d729 VPUNPCKLQDQ	%XMM19,%XMM20,%XMM0

  (1253) 0x27d72f VMOVQ	(%R12,%RDX,8),%XMM14

  (1253) 0x27d735 MOV	0xd8(%RCX,%RSI,8),%RDX

  (1253) 0x27d73d VMOVQ	(%R12,%RDX,8),%XMM1

  (1253) 0x27d743 MOV	0xd0(%RCX,%RSI,8),%RDX

  (1253) 0x27d74b VPUNPCKLQDQ	%XMM5,%XMM14,%XMM5

  (1253) 0x27d74f VINSERTI128	$0x1,%XMM0,%YMM5,%YMM0

  (1253) 0x27d755 VMOVQ	(%R12,%RDX,8),%XMM2

  (1253) 0x27d75b MOV	0xc8(%RCX,%RSI,8),%RDX

  (1253) 0x27d763 VMOVQ	(%R12,%RDX,8),%XMM3

  (1253) 0x27d769 MOV	0xc0(%RCX,%RSI,8),%RDX

  (1253) 0x27d771 VPUNPCKLQDQ	%XMM1,%XMM2,%XMM1

  (1253) 0x27d775 VMOVQ	(%R12,%RDX,8),%XMM4

  (1253) 0x27d77b VPUNPCKLQDQ	%XMM3,%XMM4,%XMM2

  (1253) 0x27d77f VINSERTI128	$0x1,%XMM1,%YMM2,%YMM1

  (1253) 0x27d785 VINSERTI64X4	$0x1,%YMM0,%ZMM1,%ZMM26

  (1253) 0x27d78c VPMOVM2W	%K0,%ZMM0

  (1253) 0x27d792 VPCMPGTQ	%ZMM26,%ZMM12,%K1

  (1253) 0x27d798 VPMOVM2W	%K1,%ZMM1

  (1253) 0x27d79e VINSERTI32X4	$0x3,%XMM1,%ZMM0,%ZMM0

  (1253) 0x27d7a5 KMOVQ	%K1,0x60(%RSP)

  (1253) 0x27d7ac VPMOVW2M	%ZMM0,%K0

  (1253) 0x27d7b2 KNOTD	%K0,%K0

  (1253) 0x27d7b7 KORTESTD	%K0,%K0

  (1253) 0x27d7bc KMOVD	%K0,0x50(%RSP)

  (1253) 0x27d7c3 JE	27d840

  (1253) 0x27d7c5 VPCMPNLTQ	%ZMM12,%ZMM26,%K1

  (1253) 0x27d7cc VPCMPNLTQ	%ZMM12,%ZMM25,%K6

  (1253) 0x27d7d3 VPCMPNLTQ	%ZMM12,%ZMM24,%K7

  (1253) 0x27d7da VPCMPNLTQ	%ZMM12,%ZMM23,%K5

  (1253) 0x27d7e1 VMOVAPD	0x240(%RSP),%ZMM3

  (1253) 0x27d7e9 VPXOR	%XMM4,%XMM4,%XMM4

  (1253) 0x27d7ed VMOVUPD	-0xc0(%R8,%RSI,8),%ZMM19{%K5}{z}

  (1253) 0x27d7f5 VMOVUPD	-0x80(%R8,%RSI,8),%ZMM20{%K7}{z}

  (1253) 0x27d7fd VMOVUPD	-0x40(%R8,%RSI,8),%ZMM21{%K6}{z}

  (1253) 0x27d805 VMOVUPD	(%R8,%RSI,8),%ZMM22{%K1}{z}

  (1253) 0x27d80c VMULPD	%ZMM3,%ZMM19,%ZMM0

  (1253) 0x27d812 VMULPD	%ZMM3,%ZMM20,%ZMM1

  (1253) 0x27d818 VMULPD	%ZMM3,%ZMM21,%ZMM2

  (1253) 0x27d81e VMULPD	%ZMM3,%ZMM22,%ZMM3

  (1253) 0x27d824 VCMPPD	$0x1,%ZMM4,%ZMM0,%K5

  (1253) 0x27d82b VCMPPD	$0x1,%ZMM4,%ZMM1,%K6

  (1253) 0x27d832 VCMPPD	$0x1,%ZMM4,%ZMM2,%K7

  (1253) 0x27d839 VCMPPD	$0x1,%ZMM4,%ZMM3,%K0

  (1253) 0x27d840 KMOVD	0x50(%RSP),%K2

  (1253) 0x27d847 KUNPCKBW	%K5,%K6,%K1

  (1253) 0x27d84b VPMOVM2W	%K0,%ZMM1

  (1253) 0x27d851 KORB	%K5,%K4,%K5

  (1253) 0x27d855 KORB	%K6,%K3,%K6

  (1253) 0x27d859 KUNPCKWD	%K1,%K7,%K1

  (1253) 0x27d85d VPMOVM2W	%K1,%ZMM0

  (1253) 0x27d863 VINSERTI32X4	$0x3,%XMM1,%ZMM0,%ZMM0

  (1253) 0x27d86a VPMOVW2M	%ZMM0,%K1

  (1253) 0x27d870 KTESTD	%K2,%K1

  (1253) 0x27d875 KMOVW	0xc0(%RSP),%K2

  (1253) 0x27d87e KORB	%K7,%K2,%K1

  (1253) 0x27d882 KMOVW	%K1,0x100(%RSP)

  (1253) 0x27d88b KMOVQ	0x60(%RSP),%K1

  (1253) 0x27d892 KORB	%K0,%K1,%K7

  (1253) 0x27d896 KMOVW	%K7,0x50(%RSP)

  (1253) 0x27d89c JE	27d480

  (1253) 0x27d8a2 VADDPD	%ZMM15,%ZMM19,%ZMM23

  (1253) 0x27d8a8 VADDPD	%ZMM16,%ZMM20,%ZMM24

  (1253) 0x27d8ae VADDPD	%ZMM17,%ZMM21,%ZMM25

  (1253) 0x27d8b4 VADDPD	%ZMM18,%ZMM22,%ZMM26

  (1253) 0x27d8ba JMP	27d480

0x27d8bf VADDPD	%ZMM19,%ZMM20,%ZMM0

0x27d8c5 VADDPD	%ZMM21,%ZMM22,%ZMM1

0x27d8cb MOV	0x148(%RSP),%RSI

0x27d8d3 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x27d8d9 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x27d8e0 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x27d8e6 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x27d8ec VADDPD	%XMM1,%XMM0,%XMM0

0x27d8f0 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x27d8f5 VADDSD	%XMM1,%XMM0,%XMM14

0x27d8f9 CMP	%R10,%RBX

0x27d8fc JNE	27d94f

0x27d8fe VMOVDQA64	0x400(%RSP),%ZMM3

0x27d906 VMOVDQA	-0x6e46e(%RIP),%XMM4

0x27d90e VMOVSD	-0x6e5ee(%RIP),%XMM6

0x27d916 VMOVAPD	0x2a0(%RSP),%YMM7

0x27d91f VMOVSD	0x110(%RSP),%XMM8

0x27d928 VMOVDQA64	0x440(%RSP),%ZMM9

0x27d930 VMOVDQA	0x2c0(%RSP),%YMM11

0x27d939 MOV	0xd8(%RSP),%R10

0x27d941 VPXOR	%XMM5,%XMM5,%XMM5

0x27d945 VPXOR	%XMM10,%XMM10,%XMM10

0x27d94a JMP	27dae0

0x27d94f VMOVDQA64	0x400(%RSP),%ZMM3

0x27d957 VMOVDQA	-0x6e4bf(%RIP),%XMM4

0x27d95f VMOVSD	-0x6e63f(%RIP),%XMM6

0x27d967 VMOVAPD	0x2a0(%RSP),%YMM7

0x27d970 VMOVSD	0x110(%RSP),%XMM8

0x27d979 VMOVDQA64	0x440(%RSP),%ZMM9

0x27d981 VMOVDQA	0x2c0(%RSP),%YMM11

0x27d98a MOV	%RBX,%RDX

0x27d98d MOV	0x2e8(%RSP),%RBX

0x27d995 VPXOR	%XMM5,%XMM5,%XMM5

0x27d999 VPXOR	%XMM10,%XMM10,%XMM10

0x27d99e TEST	$0x1c,%DL

0x27d9a1 JE	27dcdf

0x27d9a7 MOV	%RDX,0xc0(%RSP)

0x27d9af AND	$-0x4,%RDX

0x27d9b3 VBROADCASTSD	%XMM13,%YMM15

0x27d9b8 VMOVQ	%XMM14,%XMM14

0x27d9bd MOV	%RDX,0x60(%RSP)

0x27d9c2 LEA	(%RBX,%RDX,1),%RCX

0x27d9c6 MOV	0x330(%RSP),%RDX

0x27d9ce MOV	0x340(%RSP),%RSI

0x27d9d6 LEA	(%RDX,%RBX,8),%R8

0x27d9da LEA	(%RSI,%RBX,8),%RDX

0x27d9de MOV	%RDX,0x50(%RSP)

0x27d9e3 JMP	27da37

  (1252) 0x27d9f0 MOV	0x50(%RSP),%RDX

  (1252) 0x27d9f5 VMOVUPD	(%RDX,%R10,8),%YMM16{%K1}{z}

  (1252) 0x27d9fc VMULPD	%YMM15,%YMM16,%YMM0

  (1252) 0x27da02 VCMPPD	$0x1,%YMM10,%YMM0,%YMM0

  (1252) 0x27da08 VANDPD	%YMM7,%YMM0,%YMM17

  (1252) 0x27da0e MOV	0x30(%RSP),%R11

  (1252) 0x27da13 VADDPD	%YMM14,%YMM16,%YMM0

  (1252) 0x27da19 VPCMPNEQQ	%YMM7,%YMM17,%K2{%K1}

  (1252) 0x27da20 ADD	$0x4,%R10

  (1252) 0x27da24 VMOVAPD	%YMM14,%YMM0{%K2}

  (1252) 0x27da2a VMOVAPD	%YMM0,%YMM14{%K1}

  (1252) 0x27da30 CMP	%R10,0x60(%RSP)

  (1252) 0x27da35 JE	27da9b

  (1252) 0x27da37 MOV	-0x8(%R8,%R10,8),%RBX

  (1252) 0x27da3c MOV	(%R8,%R10,8),%RSI

  (1252) 0x27da40 MOV	-0x18(%R8,%R10,8),%RDX

  (1252) 0x27da45 MOV	-0x10(%R8,%R10,8),%R11

  (1252) 0x27da4a VMOVQ	(%R12,%RSI,8),%XMM0

  (1252) 0x27da50 VMOVQ	(%R12,%RBX,8),%XMM1

  (1252) 0x27da56 VMOVQ	(%R12,%RDX,8),%XMM2

  (1252) 0x27da5c VPUNPCKLQDQ	%XMM0,%XMM1,%XMM0

  (1252) 0x27da60 VMOVQ	(%R12,%R11,8),%XMM1

  (1252) 0x27da66 VPUNPCKLQDQ	%XMM1,%XMM2,%XMM1

  (1252) 0x27da6a VINSERTI128	$0x1,%XMM0,%YMM1,%YMM0

  (1252) 0x27da70 VPCMPNLTQ	%YMM12,%YMM0,%K0

  (1252) 0x27da77 VPCMPGTQ	%YMM0,%YMM12,%YMM0

  (1252) 0x27da7c VPANDN	%YMM7,%YMM0,%YMM0

  (1252) 0x27da80 KORTESTB	%K0,%K0

  (1252) 0x27da84 VPCMPEQQ	%YMM7,%YMM0,%K1

  (1252) 0x27da8a JNE	27d9f0

  (1252) 0x27da90 VXORPD	%XMM17,%XMM17,%XMM17

  (1252) 0x27da96 JMP	27da0e

0x27da9b VEXTRACTF128	$0x1,%YMM14,%XMM0

0x27daa1 MOV	0x60(%RSP),%RDX

0x27daa6 MOV	0xd8(%RSP),%R10

0x27daae MOV	0x148(%RSP),%RSI

0x27dab6 MOV	0x340(%RSP),%R8

0x27dabe VADDPD	%XMM0,%XMM14,%XMM0

0x27dac2 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x27dac7 VADDSD	%XMM1,%XMM0,%XMM14

0x27dacb CMP	%RDX,0xc0(%RSP)

0x27dad3 JNE	27dd0c

0x27dad9 NOPL	(%RAX)

0x27dae0 MOV	0x48(%RSP),%RCX

0x27dae5 MOV	0x90(%RSP),%RDX

0x27daed VUCOMISD	%XMM5,%XMM14

0x27daf1 VMOVSD	(%RCX,%RDX,8),%XMM15

0x27daf6 JE	27dc18

0x27dafc VDIVSD	%XMM14,%XMM15,%XMM14

0x27db01 CMP	%R11,%R14

0x27db04 JGE	27db81

0x27db06 MOV	0xe8(%RSP),%RCX

0x27db0e MOV	(%RCX),%RCX

0x27db11 JMP	27db28

  (1250) 0x27db20 INC	%R14

  (1250) 0x27db23 CMP	%R14,%R11

  (1250) 0x27db26 JE	27db81

  (1250) 0x27db28 MOV	0xa0(%RSP),%RDX

  (1250) 0x27db30 MOV	(%RDX,%R14,8),%RSI

  (1250) 0x27db34 MOV	(%R15,%RSI,8),%R8

  (1250) 0x27db38 CMP	%R9,%R8

  (1250) 0x27db3b JL	27db5f

  (1250) 0x27db3d MOV	0x48(%RSP),%RDX

  (1250) 0x27db42 VMOVSD	(%RDX,%R14,8),%XMM15

  (1250) 0x27db48 VMULSD	%XMM13,%XMM15,%XMM0

  (1250) 0x27db4d VUCOMISD	%XMM5,%XMM0

  (1250) 0x27db51 JAE	27db5f

  (1250) 0x27db53 VFMADD213SD	(%RCX,%R8,8),%XMM14,%XMM15

  (1250) 0x27db59 VMOVSD	%XMM15,(%RCX,%R8,8)

  (1250) 0x27db5f CMP	%R13,%RSI

  (1250) 0x27db62 JNE	27db20

  (1250) 0x27db64 MOV	0x48(%RSP),%RDX

  (1250) 0x27db69 VMOVSD	(%RDX,%R14,8),%XMM15

  (1250) 0x27db6f VMULSD	%XMM13,%XMM15,%XMM0

  (1250) 0x27db74 VUCOMISD	%XMM5,%XMM0

  (1250) 0x27db78 JAE	27db20

  (1250) 0x27db7a VFMADD231SD	%XMM15,%XMM14,%XMM8

  (1250) 0x27db7f JMP	27db20

0x27db81 CMP	$0x2,%R10

0x27db85 JL	27dc1d

0x27db8b MOV	0x198(%RSP),%RDX

0x27db93 MOV	0x98(%RSP),%RSI

0x27db9b MOV	(%RDX,%RSI,8),%RCX

0x27db9f MOV	0x8(%RDX,%RSI,8),%RDX

0x27dba4 CMP	%RDX,%RCX

0x27dba7 JGE	27dc1d

0x27dba9 MOV	0x1f8(%RSP),%RSI

0x27dbb1 MOV	0xe0(%RSP),%R8

0x27dbb9 MOV	0x90(%RSP),%R11

0x27dbc1 MOV	0x128(%RSP),%RBX

0x27dbc9 MOV	0x158(%RSP),%R14

0x27dbd1 MOV	(%RSI),%RSI

0x27dbd4 MOV	(%R8),%R8

0x27dbd7 JMP	27dbe8

  (1249) 0x27dbe0 INC	%RCX

  (1249) 0x27dbe3 CMP	%RCX,%RDX

  (1249) 0x27dbe6 JE	27dc3a

  (1249) 0x27dbe8 MOV	0x38(%RSP),%R10

  (1249) 0x27dbed MOV	(%R10,%RCX,8),%R10

  (1249) 0x27dbf1 MOV	(%R12,%R10,8),%R10

  (1249) 0x27dbf5 CMP	%RAX,%R10

  (1249) 0x27dbf8 JL	27dbe0

  (1249) 0x27dbfa VMOVSD	(%RSI,%RCX,8),%XMM15

  (1249) 0x27dbff VMULSD	%XMM13,%XMM15,%XMM0

  (1249) 0x27dc04 VUCOMISD	%XMM5,%XMM0

  (1249) 0x27dc08 JAE	27dbe0

  (1249) 0x27dc0a VFMADD213SD	(%R8,%R10,8),%XMM14,%XMM15

  (1249) 0x27dc10 VMOVSD	%XMM15,(%R8,%R10,8)

  (1249) 0x27dc16 JMP	27dbe0

0x27dc18 VADDSD	%XMM8,%XMM15,%XMM8

0x27dc1d MOV	0x90(%RSP),%R11

0x27dc25 MOV	0x128(%RSP),%RBX

0x27dc2d MOV	0x158(%RSP),%R14

0x27dc35 JMP	27cbd7

0x27dc3a MOV	0xd8(%RSP),%R10

0x27dc42 JMP	27cbd7

0x27dc47 VMOVDQA64	0x400(%RSP),%ZMM3

0x27dc4f VMOVDQA	-0x6e7b7(%RIP),%XMM4

0x27dc57 VMOVSD	-0x6e937(%RIP),%XMM6

0x27dc5f VMOVDQA	0x2a0(%RSP),%YMM7

0x27dc68 VMOVSD	0x110(%RSP),%XMM8

0x27dc71 VMOVDQA	0x2c0(%RSP),%YMM11

0x27dc7a VMOVDQA64	0x3c0(%RSP),%ZMM12

0x27dc82 MOV	0xd8(%RSP),%R10

0x27dc8a ADD	%R14,%RSI

0x27dc8d VPXOR	%XMM5,%XMM5,%XMM5

0x27dc91 VPXOR	%XMM10,%XMM10,%XMM10

0x27dc96 MOV	%RSI,%RCX

0x27dc99 JMP	27dcac

  (1254) 0x27dca0 INC	%RCX

  (1254) 0x27dca3 CMP	%RCX,%R11

  (1254) 0x27dca6 JE	27d3b0

  (1254) 0x27dcac MOV	0xa0(%RSP),%RDX

  (1254) 0x27dcb4 MOV	(%RDX,%RCX,8),%RSI

  (1254) 0x27dcb8 CMP	%R13,%RSI

  (1254) 0x27dcbb JE	27dcc3

  (1254) 0x27dcbd CMP	%R9,(%R15,%RSI,8)

  (1254) 0x27dcc1 JL	27dca0

  (1254) 0x27dcc3 MOV	0x48(%RSP),%RDX

  (1254) 0x27dcc8 VMOVSD	(%RDX,%RCX,8),%XMM15

  (1254) 0x27dccd VMULSD	%XMM13,%XMM15,%XMM0

  (1254) 0x27dcd2 VUCOMISD	%XMM5,%XMM0

  (1254) 0x27dcd6 JAE	27dca0

  (1254) 0x27dcd8 VADDSD	%XMM14,%XMM15,%XMM14

  (1254) 0x27dcdd JMP	27dca0

0x27dcdf ADD	%R10,%RBX

0x27dce2 MOV	0xd8(%RSP),%R10

0x27dcea MOV	0x340(%RSP),%R8

0x27dcf2 MOV	%RBX,%RCX

0x27dcf5 JMP	27dd0c

  (1251) 0x27dd00 INC	%RCX

  (1251) 0x27dd03 CMP	%RCX,%RSI

  (1251) 0x27dd06 JE	27dae0

  (1251) 0x27dd0c MOV	0x38(%RSP),%RDX

  (1251) 0x27dd11 MOV	(%RDX,%RCX,8),%RDX

  (1251) 0x27dd15 CMP	%RAX,(%R12,%RDX,8)

  (1251) 0x27dd19 JL	27dd00

  (1251) 0x27dd1b VMOVSD	(%R8,%RCX,8),%XMM15

  (1251) 0x27dd21 VMULSD	%XMM13,%XMM15,%XMM0

  (1251) 0x27dd26 VUCOMISD	%XMM5,%XMM0

  (1251) 0x27dd2a JAE	27dd00

  (1251) 0x27dd2c VADDSD	%XMM14,%XMM15,%XMM14

  (1251) 0x27dd31 JMP	27dd00

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1609 - 1675

--------------------------------------------------------------------------------

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

Coverage (%)	Name	Source Location	Module
►94.51+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:847	exec
○	hypre_PCGSetup	pcg.c:234	exec
►1.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1624,par_lr_interp.c:1628-1632,par_lr_interp.c:1640-1644,par_lr_interp.c:1651-1655,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.38
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	34.22
CQA cycles if fully vectorized	26.01
Front-end cycles	35.38
P0 cycles	13.67
P1 cycles	13.67
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	13.67
P5 cycles	13.67
P6 cycles	32.25
P7 cycles	32.25
P8 cycles	32.25
P9 cycles	32.25
P10 cycles	9.75
P11 cycles	9.75
P12 cycles	11.00
P13 cycles	10.50
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	279.00
Nb uops	283.00
Nb loads	109.00
Nb stores	19.00
Nb stack references	37.00
FLOP/cycle	2.26
Nb FLOP add-sub	79.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	57.44
Bytes prefetched	0.00
Bytes loaded	1712.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	52.08
Vectorization ratio store	15.79
Vectorization ratio mul	NA
Vectorization ratio add_sub	63.16
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	48.21
Vector-efficiency ratio all	32.74
Vector-efficiency ratio load	39.84
Vector-efficiency ratio store	26.32
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	51.97
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.42

Metric	Value
CQA speedup if no scalar integer	1.91
CQA speedup if FP arith vectorized	1.03
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1612-1621,par_lr_interp.c:1624-1624,par_lr_interp.c:1628-1632,par_lr_interp.c:1640-1644,par_lr_interp.c:1651-1655,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	35.38
CQA cycles if no scalar integer	18.50
CQA cycles if FP arith vectorized	34.22
CQA cycles if fully vectorized	26.01
Front-end cycles	35.38
P0 cycles	13.67
P1 cycles	13.67
P2 cycles	13.67
P3 cycles	13.67
P4 cycles	13.67
P5 cycles	13.67
P6 cycles	32.25
P7 cycles	32.25
P8 cycles	32.25
P9 cycles	32.25
P10 cycles	9.75
P11 cycles	9.75
P12 cycles	11.00
P13 cycles	10.50
P14 cycles	5.00
P15 cycles	5.00
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	279.00
Nb uops	283.00
Nb loads	109.00
Nb stores	19.00
Nb stack references	37.00
FLOP/cycle	2.26
Nb FLOP add-sub	79.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	57.44
Bytes prefetched	0.00
Bytes loaded	1712.00
Bytes stored	320.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	52.08
Vectorization ratio store	15.79
Vectorization ratio mul	NA
Vectorization ratio add_sub	63.16
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	48.21
Vector-efficiency ratio all	32.74
Vector-efficiency ratio load	39.84
Vector-efficiency ratio store	26.32
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	51.97
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	19.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609-1660,1667-1675.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609,1612-1621,1624,1628-1632,1640-1644,1651-1655,1667,1672-1675.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.38 to 18.50 cycles (1.91x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 32% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 35.38 to 26.01 cycles (1.36x speedup).

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

52% of SSE/AVX loads are used in vector version.
15% of SSE/AVX stores are used in vector version.
63% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
48% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VCMPSD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621
VMOVAPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VMOVDQA64: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1640

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

10 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 8 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

79: addition or subtraction
1: divide

The binary loop is loading 1712 bytes (214 double precision FP elements). The binary loop is storing 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	283
loop length	1566
used x86 registers	13
used mmx registers	0
used xmm registers	13
used ymm registers	6
used zmm registers	13
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	35.38 cycles
front end	35.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.67	13.67	13.67	13.67	13.67	13.67	32.25	32.25	32.25	32.25	9.75	9.75	11.00	10.50	5.00	5.00
cycles	13.67	13.67	13.67	13.67	13.67	13.67	32.25	32.25	32.25	32.25	9.75	9.75	11.00	10.50	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	35.38
Dispatch	32.25
DIV/SQRT	4.00
Overall L1	35.38

Vectorization ratios

INT

all	47%
load	75%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	52%
load	15%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	72%

INT+FP

all	50%
load	52%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	48%

Vector efficiency ratios

INT

all	32%
load	53%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	32%
load	18%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	32%
load	39%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.38 cycles. At this rate:

18% of peak load performance is reached (48.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.05 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 35.38 to 32.25 cycles (1.10x speedup).

ASM code

In the binary file, the address of the loop is: 27cbe3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x48(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R14,%RCX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX,%R11,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 27dd33 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xa0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R11,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27cbc0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,0x70(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27cc80 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x1a0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI,%RDX,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ (%RCX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0xe,(%RDX,%R8,8),%XMM5,%K1	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%R8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD -0x6d9b0(%RIP),%XMM13{%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27d3b0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x25f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27cccf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1f0f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMPQ $-0x3,(%RCX,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,0x1d0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 27ccbf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1eff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R8,%R13,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,(%R8,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDSD (%RCX,%R11,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27ccdc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1f1c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d280 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x24c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %ZMM0,0x340(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
MOV 0x310(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x308(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%R8,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27cd93 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1fd3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPD %ZMM23,%ZMM24,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM25,%ZMM26,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 27d228 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2468>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6dd47(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6dec7(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 27d3b0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x25f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST $0x1c,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 27dc47 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6dda4(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6df24(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x148(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RCX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM13,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x328(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x320(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDX,%R8,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R8,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 27d306 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2546>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VEXTRACTF128 $0x1,%YMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %XMM0,%XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP $0x2,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x198(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RDX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27d3f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2638>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RSI,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x340(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27d416 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2656>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d9a7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2be7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 %ZMM9,0x440(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVSD %XMM8,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R8,%RSI,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPXORD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %ZMM0,0x240(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
MOV 0x38(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x2e8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d4e4 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2724>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPD %ZMM19,%ZMM20,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM21,%ZMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x148(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 27d94f <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2b8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e46e(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e5ee(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 0x440(%RSP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e4bf(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e63f(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 0x440(%RSP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2e8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 27dcdf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f1f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM13,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RDX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x330(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDX,%RBX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RBX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 27da37 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2c77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VEXTRACTF128 $0x1,%YMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x148(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %XMM0,%XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD %XMM5,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RCX,%RDX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JE 27dc18 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
CMP %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27db81 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2dc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27db28 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d68>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x2,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 27dc1d <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x198(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%RSI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27dc1d <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f8(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27dbe8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e28>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDSD %XMM8,%XMM15,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e7b7(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e937(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildExtPIInterp.omp_outlined
Source file and lines	par_lr_interp.c:1609-1675
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

50% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

52% of SSE/AVX loads are used in vector version.
15% of SSE/AVX stores are used in vector version.
63% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
48% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VCMPSD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1621
VMOVAPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VMOVDQA64: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1640

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632
VEXTRACTF64X4: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1624
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1632

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 80 FP arithmetical operations:

79: addition or subtraction
1: divide

The binary loop is loading 1712 bytes (214 double precision FP elements). The binary loop is storing 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	279
nb uops	283
loop length	1566
used x86 registers	13
used mmx registers	0
used xmm registers	13
used ymm registers	6
used zmm registers	13
nb stack references	37

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	35.38 cycles
front end	35.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	13.67	13.67	13.67	13.67	13.67	13.67	32.25	32.25	32.25	32.25	9.75	9.75	11.00	10.50	5.00	5.00
cycles	13.67	13.67	13.67	13.67	13.67	13.67	32.25	32.25	32.25	32.25	9.75	9.75	11.00	10.50	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	35.38
Dispatch	32.25
DIV/SQRT	4.00
Overall L1	35.38

Vectorization ratios

INT

all	47%
load	75%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	32%

all	52%
load	15%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	72%

INT+FP

all	50%
load	52%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	63%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	48%

Vector efficiency ratios

INT

all	32%
load	53%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	32%
load	18%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	23%

INT+FP

all	32%
load	39%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 35.38 cycles. At this rate:

18% of peak load performance is reached (48.40 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.05 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 27cbe3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV 0x48(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R14,%RCX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VADDSD (%RDX,%R11,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD %XMM13,(%R14,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 27dd33 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f73>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xa0(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R11,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27cbc0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e00>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RCX,0x70(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27cc80 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R11,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %XMM6,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x1a0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xa8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RSI,%RDX,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ (%RCX),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VCMPSD $0xe,(%RDX,%R8,8),%XMM5,%K1	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	3	0.50	scal (12.5%)
LEA 0x1(%R8),%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD -0x6d9b0(%RIP),%XMM13{%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
CMP %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27d3b0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x25f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOT %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27cccf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1f0f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0x78(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMPQ $-0x3,(%RCX,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0x1,0x1d0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 27ccbf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1eff>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R8,%R13,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RCX,(%R8,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDSD (%RCX,%R11,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x20,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27ccdc <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1f1c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d280 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x24c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VXORPD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %ZMM0,0x340(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
MOV 0x310(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x308(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%R8,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RDX,%R8,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27cd93 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1fd3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPD %ZMM23,%ZMM24,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM25,%ZMM26,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RSI,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 27d228 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2468>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6dd47(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6dec7(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 27d3b0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x25f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST $0x1c,%CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 27dc47 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6dda4(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6df24(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0x148(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RCX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM13,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %RCX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %R14,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x328(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x320(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDX,%R8,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R11,%R8,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 27d306 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2546>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VEXTRACTF128 $0x1,%YMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %XMM0,%XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP $0x2,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x198(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%RDX,8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%RDX,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RBX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27d3f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2638>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RSI,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x340(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 27d416 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2656>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d9a7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2be7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VBROADCASTSD %XMM13,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 %ZMM9,0x440(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
VMOVSD %XMM8,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc0(%R8,%RSI,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %XMM14,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPXORD %XMM16,%XMM16,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VXORPD %XMM17,%XMM17,%XMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %ZMM0,0x240(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	1	4	1	vect (100.0%)
MOV 0x38(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RSI,0x2e8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RCX,%RSI,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 27d4e4 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2724>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDPD %ZMM19,%ZMM20,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VADDPD %ZMM21,%ZMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
MOV 0x148(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 27d94f <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2b8f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e46e(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e5ee(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 0x440(%RSP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 27dae0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d20>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e4bf(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e63f(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVAPD 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA64 0x440(%RSP),%ZMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2e8(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 27dcdf <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f1f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VBROADCASTSD %XMM13,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
LEA (%RBX,%RDX,1),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV 0x330(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RDX,%RBX,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RBX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RDX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 27da37 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2c77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VEXTRACTF128 $0x1,%YMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV 0x60(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x148(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VADDPD %XMM0,%XMM14,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
CMP %RDX,0xc0(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JNE 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x48(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VUCOMISD %XMM5,%XMM14	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RCX,%RDX,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
JE 27dc18 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e58>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VDIVSD %XMM14,%XMM15,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
CMP %R11,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27db81 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2dc1>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xe8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27db28 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2d68>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
CMP $0x2,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 27dc1d <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x198(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x98(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%RSI,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 27dc1d <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1f8(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xe0(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27dbe8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2e28>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VADDSD %XMM8,%XMM15,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x90(%RSP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x128(%RSP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x158(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 27cbd7 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1e17>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVDQA64 0x400(%RSP),%ZMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVDQA -0x6e7b7(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSD -0x6e937(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2a0(%RSP),%YMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD 0x110(%RSP),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x2c0(%RSP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA64 0x3c0(%RSP),%ZMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (100.0%)
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R14,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
MOV %RSI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dcac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2eec>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x340(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 27dd0c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x2f4c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code