OV - exec - Loop 1066

	Loop Id: 1066	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.04%

0x2729f0 MOV	-0xe8(%RBP),%RSI

0x2729f7 INC	%RSI

0x2729fa CMP	%RSI,-0xe0(%RBP)

0x272a01 JLE	272c5b

0x272a07 MOV	-0xd8(%RBP),%RDX

0x272a0e MOV	%RSI,-0xe8(%RBP)

0x272a15 MOV	-0x40(%RBP),%R8

0x272a19 MOV	-0x78(%RBP),%RDI

0x272a1d MOV	(%RDX,%RSI,8),%RSI

0x272a21 MOV	%RAX,(%R8,%RSI,8)

0x272a25 MOV	%RCX,(%RDI,%RSI,8)

0x272a29 MOV	(%R12,%RSI,8),%RDI

0x272a2d CMP	%RDI,0x8(%R12,%RSI,8)

0x272a32 JLE	272b50

0x272a38 MOV	-0xf0(%RBP),%RDX

0x272a3f MOV	(%RDX),%RDX

0x272a42 MOV	%RDX,-0x30(%RBP)

0x272a46 MOV	-0xf8(%RBP),%R10

0x272a4d MOV	-0x90(%RBP),%RDX

0x272a54 MOV	-0x80(%RBP),%R8

0x272a58 MOV	(%RDX),%R9

0x272a5b MOV	(%R10),%R10

0x272a5e MOV	(%R8),%RDX

0x272a61 MOV	%R10,-0x50(%RBP)

0x272a65 JMP	272a82

  (1069) 0x272a70 MOV	-0x48(%RBP),%R12

  (1069) 0x272a74 INC	%RDI

  (1069) 0x272a77 CMP	%RDI,0x8(%R12,%RSI,8)

  (1069) 0x272a7c JLE	272b50

  (1069) 0x272a82 MOV	-0x98(%RBP),%R8

  (1069) 0x272a89 MOV	(%RBX),%R10

  (1069) 0x272a8c MOV	-0x110(%RBP),%R11

  (1069) 0x272a93 MOV	(%R8,%RDI,8),%R13

  (1069) 0x272a97 DEC	%R10

  (1069) 0x272a9a CMP	%R10,(%R11,%R13,8)

  (1069) 0x272a9e JNE	272a74

  (1069) 0x272aa0 MOV	-0x30(%RBP),%R8

  (1069) 0x272aa4 MOV	0x8(%R8,%R13,8),%R12

  (1069) 0x272aa9 TEST	%R12,%R12

  (1069) 0x272aac JLE	272af0

  (1069) 0x272aae MOV	-0x40(%RBP),%R8

  (1069) 0x272ab2 MOV	(%R8,%R13,8),%R8

  (1069) 0x272ab6 ADD	%R8,%R12

  (1069) 0x272ab9 JMP	272ac8

    (1071) 0x272ac0 INC	%R8

    (1071) 0x272ac3 CMP	%R12,%R8

    (1071) 0x272ac6 JGE	272af0

    (1071) 0x272ac8 MOV	(%RBX),%R11

    (1071) 0x272acb MOV	-0x8(%R9,%R11,8),%R11

    (1071) 0x272ad0 MOV	(%R11,%R8,8),%R11

    (1071) 0x272ad4 CMP	%RSI,(%R14,%R11,8)

    (1071) 0x272ad8 JE	272ac0

    (1071) 0x272ada MOV	-0x30(%RBP),%R10

    (1071) 0x272ade INC	%RAX

    (1071) 0x272ae1 INCQ	0x8(%R10,%RSI,8)

    (1071) 0x272ae6 MOV	%RSI,(%R14,%R11,8)

    (1071) 0x272aea JMP	272ac0

  (1069) 0x272af0 MOV	-0x50(%RBP),%R8

  (1069) 0x272af4 MOV	0x8(%R8,%R13,8),%R12

  (1069) 0x272af9 TEST	%R12,%R12

  (1069) 0x272afc JLE	272a70

  (1069) 0x272b02 MOV	-0x78(%RBP),%R8

  (1069) 0x272b06 MOV	-0x50(%RBP),%R10

  (1069) 0x272b0a MOV	(%R8,%R13,8),%R8

  (1069) 0x272b0e ADD	%R8,%R12

  (1069) 0x272b11 JMP	272b2c

    (1070) 0x272b20 INC	%R8

    (1070) 0x272b23 CMP	%R12,%R8

    (1070) 0x272b26 JGE	272a70

    (1070) 0x272b2c MOV	(%RBX),%R11

    (1070) 0x272b2f MOV	-0x8(%RDX,%R11,8),%R11

    (1070) 0x272b34 MOV	(%R11,%R8,8),%R11

    (1070) 0x272b38 CMP	%RSI,(%R15,%R11,8)

    (1070) 0x272b3c JE	272b20

    (1070) 0x272b3e INCQ	0x8(%R10,%RSI,8)

    (1070) 0x272b43 INC	%RCX

    (1070) 0x272b46 MOV	%RSI,(%R15,%R11,8)

    (1070) 0x272b4a JMP	272b20

0x272b50 MOV	-0x88(%RBP),%RDX

0x272b57 MOV	(%RDX,%RSI,8),%RDI

0x272b5b MOV	0x8(%RDX,%RSI,8),%RDX

0x272b60 CMP	%RDX,%RDI

0x272b63 JGE	2729f0

0x272b69 MOV	-0x150(%RBP),%R8

0x272b70 MOV	(%R8),%R8

0x272b73 MOV	%R8,-0x50(%RBP)

0x272b77 MOV	-0x158(%RBP),%R8

0x272b7e MOV	(%R8),%R8

0x272b81 MOV	%R8,-0x30(%RBP)

0x272b85 MOV	-0x160(%RBP),%R8

0x272b8c MOV	(%R8),%R10

0x272b8f JMP	272bb8

  (1067) 0x272ba0 MOV	-0x88(%RBP),%RDX

  (1067) 0x272ba7 MOV	0x8(%RDX,%RSI,8),%RDX

  (1067) 0x272bac INC	%RDI

  (1067) 0x272baf CMP	%RDX,%RDI

  (1067) 0x272bb2 JGE	2729f0

  (1067) 0x272bb8 MOV	-0x108(%RBP),%R8

  (1067) 0x272bbf MOV	(%RBX),%R9

  (1067) 0x272bc2 MOV	-0x100(%RBP),%R11

  (1067) 0x272bc9 MOV	(%R8,%RDI,8),%R8

  (1067) 0x272bcd DEC	%R9

  (1067) 0x272bd0 CMP	%R9,(%R11,%R8,8)

  (1067) 0x272bd4 JNE	272bac

  (1067) 0x272bd6 MOV	-0x30(%RBP),%R9

  (1067) 0x272bda MOV	0x8(%R9,%R8,8),%R11

  (1067) 0x272bdf TEST	%R11,%R11

  (1067) 0x272be2 JLE	272bac

  (1067) 0x272be4 MOV	-0x50(%RBP),%RDX

  (1067) 0x272be8 MOV	-0xf8(%RBP),%R13

  (1067) 0x272bef MOV	-0xf0(%RBP),%R9

  (1067) 0x272bf6 MOV	(%RDX,%R8,8),%RDX

  (1067) 0x272bfa MOV	(%R13),%R13

  (1067) 0x272bfe MOV	(%R9),%R9

  (1067) 0x272c01 ADD	%RDX,%R11

  (1067) 0x272c04 JMP	272c18

    (1068) 0x272c10 INC	%RDX

    (1068) 0x272c13 CMP	%R11,%RDX

    (1068) 0x272c16 JGE	272ba0

    (1068) 0x272c18 MOV	(%RBX),%R8

    (1068) 0x272c1b MOV	(%R10,%R8,8),%R8

    (1068) 0x272c1f MOV	(%R8,%RDX,8),%R8

    (1068) 0x272c23 TEST	%R8,%R8

    (1068) 0x272c26 JS	272c40

    (1068) 0x272c28 CMP	%RSI,(%R15,%R8,8)

    (1068) 0x272c2c JE	272c10

    (1068) 0x272c2e INCQ	0x8(%R13,%RSI,8)

    (1068) 0x272c33 INC	%RCX

    (1068) 0x272c36 MOV	%RSI,(%R15,%R8,8)

    (1068) 0x272c3a JMP	272c10

    (1068) 0x272c40 NOT	%R8

    (1068) 0x272c43 CMP	%RSI,(%R14,%R8,8)

    (1068) 0x272c47 JE	272c10

    (1068) 0x272c49 INCQ	0x8(%R9,%RSI,8)

    (1068) 0x272c4e INC	%RAX

    (1068) 0x272c51 MOV	%RSI,(%R14,%R8,8)

    (1068) 0x272c55 JMP	272c10

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►97.28+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.72+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:939-944,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.00
Front-end cycles	4.88
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	25.00
Nb stores	7.00
Nb stack references	15.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.64
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:939-944,par_multi_interp.c:970-970,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	1.00
Front-end cycles	4.88
P0 cycles	1.33
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	25.00
Nb stores	7.00
Nb stack references	15.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	200.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,970,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 77 paths individually, rerun with max-paths=77
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 77 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 4.88 cycles (1.64x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 200 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	39
nb uops	39
loop length	184
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.67	1.67	1.67	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.67	1.67	1.67	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

9% of peak load performance is reached (25.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 272a07

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0xe8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RSI,-0xe0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 272c5b <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x5ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xd8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,(%R8,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,(%RDI,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,0x8(%R12,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 272b50 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x4a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x80(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 272a82 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x3d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 2729f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x340>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x158(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x160(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 272bb8 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x508>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 77 paths individually, rerun with max-paths=77
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.00 to 1.00 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 8.00 to 4.88 cycles (1.64x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 200 bytes. The binary loop is storing 56 bytes.

General properties

nb instructions	39
nb uops	39
loop length	184
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.88 cycles
front end	4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.33	1.33	1.33	1.67	1.67	1.67	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.33	1.33	1.33	1.67	1.67	1.67	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.88
Dispatch	8.00
Overall L1	8.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

9% of peak load performance is reached (25.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 272a07

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0xe8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RSI,-0xe0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 272c5b <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x5ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xd8(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x78(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,(%R8,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,(%RDI,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,0x8(%R12,%RSI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 272b50 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x4a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x80(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 272a82 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x3d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX,%RSI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 2729f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x340>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x158(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R8,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x160(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 272bb8 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x508>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code