OV - exec - Function hypre_SeqVectorScale.omp

	Function: hypre_SeqVectorScale.omp_outlined	Module: exec	Source: vector.c:413-416	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 413 - 416

--------------------------------------------------------------------------------

413: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

414: #endif

415:    for (i = 0; i < size; i++)

416:       y_data[i] *= alpha;

0x2fc1f0 PUSH	%RBP

0x2fc1f1 MOV	%RSP,%RBP

0x2fc1f4 PUSH	%R15

0x2fc1f6 PUSH	%R14

0x2fc1f8 PUSH	%R12

0x2fc1fa PUSH	%RBX

0x2fc1fb SUB	$0x20,%RSP

0x2fc1ff MOV	(%RDX),%R12

0x2fc202 TEST	%R12,%R12

0x2fc205 JLE	2fc38a

0x2fc20b MOV	(%RDI),%R14D

0x2fc20e DEC	%R12

0x2fc211 MOV	%R8,%RBX

0x2fc214 MOV	%RCX,%R15

0x2fc217 MOVQ	$0,-0x38(%RBP)

0x2fc21f MOVQ	$0x1,-0x40(%RBP)

0x2fc227 MOVL	$0,-0x2c(%RBP)

0x2fc22e MOV	%R12,-0x28(%RBP)

0x2fc232 SUB	$0x8,%RSP

0x2fc236 LEA	-0x40(%RBP),%RAX

0x2fc23a LEA	0xf917(%RIP),%RDI

0x2fc241 LEA	-0x2c(%RBP),%RCX

0x2fc245 LEA	-0x38(%RBP),%R8

0x2fc249 LEA	-0x28(%RBP),%R9

0x2fc24d MOV	%R14D,%ESI

0x2fc250 MOV	$0x22,%EDX

0x2fc255 PUSH	$0x1

0x2fc257 PUSH	$0x1

0x2fc259 PUSH	%RAX

0x2fc25a CALL	305fa0 <@plt_start@+0x90>

0x2fc25f ADD	$0x20,%RSP

0x2fc263 MOV	-0x28(%RBP),%RAX

0x2fc267 CMP	%R12,%RAX

0x2fc26a CMOVL	%RAX,%R12

0x2fc26e MOV	-0x38(%RBP),%RAX

0x2fc272 MOV	%R12,-0x28(%RBP)

0x2fc276 CMP	%R12,%RAX

0x2fc279 JG	2fc378

0x2fc27f MOV	(%R15),%RCX

0x2fc282 MOV	%R12,%RDX

0x2fc285 SUB	%RAX,%RDX

0x2fc288 INC	%RDX

0x2fc28b CMP	$0x4,%RDX

0x2fc28f JB	2fc35d

0x2fc295 LEA	(%RCX,%RAX,8),%RSI

0x2fc299 LEA	0x8(%RBX),%RDI

0x2fc29d CMP	%RDI,%RSI

0x2fc2a0 JAE	2fc2b0

0x2fc2a2 LEA	0x8(%RCX,%R12,8),%RDI

0x2fc2a7 CMP	%RBX,%RDI

0x2fc2aa JA	2fc35d

0x2fc2b0 CMP	$0x20,%RDX

0x2fc2b4 JAE	2fc2ba

0x2fc2b6 XOR	%EDI,%EDI

0x2fc2b8 JMP	2fc331

0x2fc2ba VBROADCASTSD	(%RBX),%ZMM0

0x2fc2c0 LEA	0xc0(%RCX,%RAX,8),%R8

0x2fc2c8 MOV	%RDX,%RDI

0x2fc2cb AND	$-0x20,%RDI

0x2fc2cf XOR	%R9D,%R9D

0x2fc2d2 NOPW	%CS:(%RAX,%RAX,1)

(3687) 0x2fc2e0 VMULPD	-0xc0(%R8,%R9,8),%ZMM0,%ZMM1

(3687) 0x2fc2e8 VMULPD	-0x80(%R8,%R9,8),%ZMM0,%ZMM2

(3687) 0x2fc2f0 VMULPD	-0x40(%R8,%R9,8),%ZMM0,%ZMM3

(3687) 0x2fc2f8 VMULPD	(%R8,%R9,8),%ZMM0,%ZMM4

(3687) 0x2fc2ff VMOVUPD	%ZMM1,-0xc0(%R8,%R9,8)

(3687) 0x2fc307 VMOVUPD	%ZMM2,-0x80(%R8,%R9,8)

(3687) 0x2fc30f VMOVUPD	%ZMM3,-0x40(%R8,%R9,8)

(3687) 0x2fc317 VMOVUPD	%ZMM4,(%R8,%R9,8)

(3687) 0x2fc31e ADD	$0x20,%R9

(3687) 0x2fc322 CMP	%R9,%RDI

(3687) 0x2fc325 JNE	2fc2e0

0x2fc327 CMP	%RDI,%RDX

0x2fc32a JE	2fc378

0x2fc32c TEST	$0x1c,%DL

0x2fc32f JE	2fc35a

0x2fc331 VBROADCASTSD	(%RBX),%YMM0

0x2fc336 MOV	%RDX,%R8

0x2fc339 AND	$-0x4,%R8

0x2fc33d ADD	%R8,%RAX

(3688) 0x2fc340 VMULPD	(%RSI,%RDI,8),%YMM0,%YMM1

(3688) 0x2fc345 VMOVUPD	%YMM1,(%RSI,%RDI,8)

(3688) 0x2fc34a ADD	$0x4,%RDI

(3688) 0x2fc34e CMP	%RDI,%R8

(3688) 0x2fc351 JNE	2fc340

0x2fc353 CMP	%R8,%RDX

0x2fc356 JNE	2fc35d

0x2fc358 JMP	2fc378

0x2fc35a ADD	%RDI,%RAX

0x2fc35d DEC	%RAX

(3686) 0x2fc360 VMOVSD	0x8(%RCX,%RAX,8),%XMM0

(3686) 0x2fc366 VMULSD	(%RBX),%XMM0,%XMM0

(3686) 0x2fc36a VMOVSD	%XMM0,0x8(%RCX,%RAX,8)

(3686) 0x2fc370 INC	%RAX

(3686) 0x2fc373 CMP	%R12,%RAX

(3686) 0x2fc376 JL	2fc360

0x2fc378 LEA	0xf7f1(%RIP),%RDI

0x2fc37f MOV	%R14D,%ESI

0x2fc382 VZEROUPPER

0x2fc385 CALL	305fb0 <@plt_start@+0xa0>

0x2fc38a ADD	$0x20,%RSP

0x2fc38e POP	%RBX

0x2fc38f POP	%R12

0x2fc391 POP	%R14

0x2fc393 POP	%R15

0x2fc395 POP	%RBP

0x2fc396 RET

0x2fc397 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

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Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
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Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 3.00 cycles (3.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 11.13 to 0.83 cycles (13.36x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	86
nb uops	89
loop length	318
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Dispatch	8.17
Overall L1	11.13

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	11%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.13 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 11.13 to 8.17 cycles (1.36x speedup).

ASM code

In the binary file, the address of the function is: 2fc1f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R12,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2fc38a <hypre_SeqVectorScale.omp_outlined+0x19a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R12,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xf917(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA (%RCX,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 2fc2b0 <hypre_SeqVectorScale.omp_outlined+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%RCX,%R12,8),%RDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 2fc2ba <hypre_SeqVectorScale.omp_outlined+0xca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2fc331 <hypre_SeqVectorScale.omp_outlined+0x141>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0xc0(%RCX,%RAX,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JE 2fc35a <hypre_SeqVectorScale.omp_outlined+0x16a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0xf7f1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.13 to 3.00 cycles (3.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/vector.c:415

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 36 bytes.

General properties

nb instructions	86
nb uops	89
loop length	318
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	1
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.13 cycles
front end	11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	8.17	8.17	8.17	8.17	8.17	8.17	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Dispatch	8.17
Overall L1	11.13

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	11%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 11.13 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.24 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2fc1f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
TEST %R12,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2fc38a <hypre_SeqVectorScale.omp_outlined+0x19a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R12,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xf917(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x2c(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,-0x28(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R15),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JB 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA (%RCX,%RAX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x8(%RBX),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %RDI,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 2fc2b0 <hypre_SeqVectorScale.omp_outlined+0xc0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%RCX,%R12,8),%RDI	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
CMP %RBX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JA 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JAE 2fc2ba <hypre_SeqVectorScale.omp_outlined+0xca>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2fc331 <hypre_SeqVectorScale.omp_outlined+0x141>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
VBROADCASTSD (%RBX),%ZMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA 0xc0(%RCX,%RAX,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JE 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%DL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JE 2fc35a <hypre_SeqVectorScale.omp_outlined+0x16a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD (%RBX),%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
AND $-0x4,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
ADD %R8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 2fc35d <hypre_SeqVectorScale.omp_outlined+0x16d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 2fc378 <hypre_SeqVectorScale.omp_outlined+0x188>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD %RDI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0xf7f1(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorScale.omp_outlined–	0.34	0.18
○Loop 3687 - vector.c:415-416 - exec	0.34	0.17
○Loop 3688 - vector.c:415-416 - exec	0.00	0.00
○Loop 3686 - vector.c:415-416 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code