OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace.omp

	Function: hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x2f74e0 PUSH	%RBP

0x2f74e1 MOV	%RSP,%RBP

0x2f74e4 PUSH	%R15

0x2f74e6 PUSH	%R14

0x2f74e8 PUSH	%R13

0x2f74ea PUSH	%R12

0x2f74ec PUSH	%RBX

0x2f74ed SUB	$0x88,%RSP

0x2f74f4 MOV	(%RDX),%R13

0x2f74f7 TEST	%R13,%R13

0x2f74fa JLE	2f758a

0x2f7500 MOV	(%RDI),%ESI

0x2f7502 DEC	%R13

0x2f7505 MOV	%R9,%R14

0x2f7508 MOV	%R8,%R15

0x2f750b MOV	%RCX,%R12

0x2f750e MOVQ	$0,-0x70(%RBP)

0x2f7516 MOVQ	$0x1,-0xa8(%RBP)

0x2f7521 MOVL	$0,-0x40(%RBP)

0x2f7528 MOV	%R13,-0x38(%RBP)

0x2f752c SUB	$0x8,%RSP

0x2f7530 LEA	-0xa8(%RBP),%RAX

0x2f7537 LEA	0x1416a(%RIP),%RDI

0x2f753e LEA	-0x40(%RBP),%RCX

0x2f7542 LEA	-0x70(%RBP),%R8

0x2f7546 LEA	-0x38(%RBP),%R9

0x2f754a MOV	%ESI,-0x3c(%RBP)

0x2f754d MOV	$0x22,%EDX

0x2f7552 PUSH	$0x1

0x2f7554 PUSH	$0x1

0x2f7556 PUSH	%RAX

0x2f7557 CALL	305fa0 <@plt_start@+0x90>

0x2f755c ADD	$0x20,%RSP

0x2f7560 MOV	-0x38(%RBP),%RAX

0x2f7564 MOV	-0x70(%RBP),%RSI

0x2f7568 CMP	%R13,%RAX

0x2f756b CMOVL	%RAX,%R13

0x2f756f MOV	%R13,-0x38(%RBP)

0x2f7573 CMP	%R13,%RSI

0x2f7576 JLE	2f759c

0x2f7578 MOV	-0x3c(%RBP),%ESI

0x2f757b LEA	0x1413e(%RIP),%RDI

0x2f7582 VZEROUPPER

0x2f7585 CALL	305fb0 <@plt_start@+0xa0>

0x2f758a ADD	$0x88,%RSP

0x2f7591 POP	%RBX

0x2f7592 POP	%R12

0x2f7594 POP	%R13

0x2f7596 POP	%R14

0x2f7598 POP	%R15

0x2f759a POP	%RBP

0x2f759b RET

0x2f759c MOV	0x28(%RBP),%RAX

0x2f75a0 MOV	(%R14),%R9

0x2f75a3 MOV	(%R12),%RCX

0x2f75a7 MOV	0x20(%RBP),%RDI

0x2f75ab MOV	0x18(%RBP),%RDX

0x2f75af MOV	0x10(%RBP),%R8

0x2f75b3 MOV	(%R15),%R10

0x2f75b6 MOV	%R13,-0x48(%RBP)

0x2f75ba MOV	(%RAX),%R14

0x2f75bd MOV	%RCX,-0x58(%RBP)

0x2f75c1 MOV	%R9,-0x50(%RBP)

0x2f75c5 MOV	%R14,-0x60(%RBP)

0x2f75c9 CMP	$0x1,%R10

0x2f75cd JNE	2f779c

0x2f75d3 MOV	(%R8),%RCX

0x2f75d6 MOV	(%RDI),%RDI

0x2f75d9 MOV	(%RDX),%RDX

0x2f75dc LEA	0x60(%RCX),%RAX

0x2f75e0 LEA	0x60(%RDI),%R9

0x2f75e4 MOV	%RAX,-0x30(%RBP)

0x2f75e8 JMP	2f7609

0x2f75ea NOPW	(%RAX,%RAX,1)

(3590) 0x2f75f0 VADDSD	(%R14,%RAX,8),%XMM0,%XMM0

(3590) 0x2f75f6 LEA	0x1(%R8),%RSI

(3590) 0x2f75fa VMOVSD	%XMM0,(%R14,%RAX,8)

(3590) 0x2f7600 CMP	%R13,%R8

(3590) 0x2f7603 JGE	2f7578

(3590) 0x2f7609 MOV	-0x58(%RBP),%RAX

(3590) 0x2f760d MOV	-0x50(%RBP),%R10

(3590) 0x2f7611 VXORPD	%XMM0,%XMM0,%XMM0

(3590) 0x2f7615 MOV	%RSI,%R8

(3590) 0x2f7618 MOV	(%RAX,%RSI,8),%RAX

(3590) 0x2f761c MOV	(%R10,%RAX,8),%R11

(3590) 0x2f7620 MOV	0x8(%R10,%RAX,8),%R10

(3590) 0x2f7625 MOV	%R10,%RBX

(3590) 0x2f7628 SUB	%R11,%RBX

(3590) 0x2f762b JLE	2f75f0

(3590) 0x2f762d CMP	$0x10,%RBX

(3590) 0x2f7631 JB	2f7780

(3590) 0x2f7637 MOV	-0x30(%RBP),%RSI

(3590) 0x2f763b MOV	%RBX,%R14

(3590) 0x2f763e AND	$-0x10,%R14

(3590) 0x2f7642 LEA	(%R9,%R11,8),%R15

(3590) 0x2f7646 VXORPD	%XMM0,%XMM0,%XMM0

(3590) 0x2f764a VXORPD	%XMM1,%XMM1,%XMM1

(3590) 0x2f764e VXORPD	%XMM2,%XMM2,%XMM2

(3590) 0x2f7652 VXORPD	%XMM3,%XMM3,%XMM3

(3590) 0x2f7656 XOR	%R12D,%R12D

(3590) 0x2f7659 LEA	(%RSI,%R11,8),%RSI

(3590) 0x2f765d ADD	%R14,%R11

  (3592) 0x2f7660 MOV	-0x50(%R15,%R12,8),%R13

  (3592) 0x2f7665 VMOVSD	(%RDX,%R13,8),%XMM4

  (3592) 0x2f766b MOV	-0x48(%R15,%R12,8),%R13

  (3592) 0x2f7670 VMOVHPD	(%RDX,%R13,8),%XMM4,%XMM4

  (3592) 0x2f7676 MOV	-0x60(%R15,%R12,8),%R13

  (3592) 0x2f767b VMOVSD	(%RDX,%R13,8),%XMM5

  (3592) 0x2f7681 MOV	-0x58(%R15,%R12,8),%R13

  (3592) 0x2f7686 VMOVHPD	(%RDX,%R13,8),%XMM5,%XMM5

  (3592) 0x2f768c MOV	-0x30(%R15,%R12,8),%R13

  (3592) 0x2f7691 VMOVSD	(%RDX,%R13,8),%XMM6

  (3592) 0x2f7697 MOV	-0x28(%R15,%R12,8),%R13

  (3592) 0x2f769c VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

  (3592) 0x2f76a2 VFMADD231PD	-0x60(%RSI,%R12,8),%YMM4,%YMM0

  (3592) 0x2f76a9 VMOVHPD	(%RDX,%R13,8),%XMM6,%XMM6

  (3592) 0x2f76af MOV	-0x40(%R15,%R12,8),%R13

  (3592) 0x2f76b4 VMOVSD	(%RDX,%R13,8),%XMM7

  (3592) 0x2f76ba MOV	-0x38(%R15,%R12,8),%R13

  (3592) 0x2f76bf VMOVHPD	(%RDX,%R13,8),%XMM7,%XMM7

  (3592) 0x2f76c5 MOV	-0x10(%R15,%R12,8),%R13

  (3592) 0x2f76ca VMOVSD	(%RDX,%R13,8),%XMM8

  (3592) 0x2f76d0 MOV	-0x8(%R15,%R12,8),%R13

  (3592) 0x2f76d5 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM5

  (3592) 0x2f76db VFMADD231PD	-0x40(%RSI,%R12,8),%YMM5,%YMM1

  (3592) 0x2f76e2 VMOVHPD	(%RDX,%R13,8),%XMM8,%XMM8

  (3592) 0x2f76e8 MOV	-0x20(%R15,%R12,8),%R13

  (3592) 0x2f76ed VMOVSD	(%RDX,%R13,8),%XMM9

  (3592) 0x2f76f3 MOV	-0x18(%R15,%R12,8),%R13

  (3592) 0x2f76f8 VMOVHPD	(%RDX,%R13,8),%XMM9,%XMM9

  (3592) 0x2f76fe MOV	0x10(%R15,%R12,8),%R13

  (3592) 0x2f7703 VMOVSD	(%RDX,%R13,8),%XMM10

  (3592) 0x2f7709 MOV	0x18(%R15,%R12,8),%R13

  (3592) 0x2f770e VINSERTF128	$0x1,%XMM8,%YMM9,%YMM6

  (3592) 0x2f7714 VFMADD231PD	-0x20(%RSI,%R12,8),%YMM6,%YMM2

  (3592) 0x2f771b VMOVHPD	(%RDX,%R13,8),%XMM10,%XMM10

  (3592) 0x2f7721 MOV	(%R15,%R12,8),%R13

  (3592) 0x2f7725 VMOVSD	(%RDX,%R13,8),%XMM11

  (3592) 0x2f772b MOV	0x8(%R15,%R12,8),%R13

  (3592) 0x2f7730 VMOVHPD	(%RDX,%R13,8),%XMM11,%XMM11

  (3592) 0x2f7736 VINSERTF128	$0x1,%XMM10,%YMM11,%YMM7

  (3592) 0x2f773c VFMADD231PD	(%RSI,%R12,8),%YMM7,%YMM3

  (3592) 0x2f7742 ADD	$0x10,%R12

  (3592) 0x2f7746 CMP	%R12,%R14

  (3592) 0x2f7749 JNE	2f7660

(3590) 0x2f774f VADDPD	%YMM0,%YMM1,%YMM0

(3590) 0x2f7753 VADDPD	%YMM2,%YMM3,%YMM1

(3590) 0x2f7757 MOV	-0x48(%RBP),%R13

(3590) 0x2f775b VADDPD	%YMM0,%YMM1,%YMM0

(3590) 0x2f775f VEXTRACTF128	$0x1,%YMM0,%XMM1

(3590) 0x2f7765 VADDPD	%XMM1,%XMM0,%XMM0

(3590) 0x2f7769 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

(3590) 0x2f776e VADDSD	%XMM1,%XMM0,%XMM0

(3590) 0x2f7772 CMP	%R14,%RBX

(3590) 0x2f7775 MOV	-0x60(%RBP),%R14

(3590) 0x2f7779 JE	2f75f0

(3590) 0x2f777f NOP

  (3591) 0x2f7780 MOV	(%RDI,%R11,8),%RSI

  (3591) 0x2f7784 VMOVSD	(%RDX,%RSI,8),%XMM1

  (3591) 0x2f7789 VFMADD231SD	(%RCX,%R11,8),%XMM1,%XMM0

  (3591) 0x2f778f INC	%R11

  (3591) 0x2f7792 CMP	%R11,%R10

  (3591) 0x2f7795 JNE	2f7780

(3590) 0x2f7797 JMP	2f75f0

0x2f779c JL	2f7578

0x2f77a2 MOV	0x48(%RBP),%RAX

0x2f77a6 MOV	0x40(%RBP),%RCX

0x2f77aa MOV	%R10,-0x98(%RBP)

0x2f77b1 MOV	(%RCX),%RCX

0x2f77b4 MOV	(%RAX),%RAX

0x2f77b7 MOV	%RCX,-0x90(%RBP)

0x2f77be MOV	%RAX,-0x78(%RBP)

0x2f77c2 JMP	2f77e2

0x2f77c4 NOPW	%CS:(%RAX,%RAX,1)

(3586) 0x2f77d0 MOV	-0x80(%RBP),%RCX

(3586) 0x2f77d4 LEA	0x1(%RCX),%RSI

(3586) 0x2f77d8 CMP	%RCX,-0x48(%RBP)

(3586) 0x2f77dc JLE	2f7578

(3586) 0x2f77e2 MOV	-0x58(%RBP),%RAX

(3586) 0x2f77e6 MOV	%RSI,-0x80(%RBP)

(3586) 0x2f77ea MOV	(%RAX,%RSI,8),%RCX

(3586) 0x2f77ee MOV	-0x50(%RBP),%RSI

(3586) 0x2f77f2 MOV	(%RSI,%RCX,8),%RDX

(3586) 0x2f77f6 MOV	0x8(%RSI,%RCX,8),%RDI

(3586) 0x2f77fb MOV	%RCX,-0x30(%RBP)

(3586) 0x2f77ff MOV	%RDI,%R13

(3586) 0x2f7802 SUB	%RDX,%R13

(3586) 0x2f7805 MOV	%RDX,-0x68(%RBP)

(3586) 0x2f7809 JLE	2f77d0

(3586) 0x2f780b MOV	-0x30(%RBP),%RAX

(3586) 0x2f780f MOV	%R13,%R8

(3586) 0x2f7812 AND	$-0x10,%R8

(3586) 0x2f7816 IMUL	-0x78(%RBP),%RAX

(3586) 0x2f781b MOV	%RAX,-0x30(%RBP)

(3586) 0x2f781f MOV	0x10(%RBP),%RAX

(3586) 0x2f7823 MOV	(%RAX),%R9

(3586) 0x2f7826 MOV	0x18(%RBP),%RAX

(3586) 0x2f782a MOV	(%RAX),%RBX

(3586) 0x2f782d MOV	0x30(%RBP),%RAX

(3586) 0x2f7831 MOV	(%RAX),%RAX

(3586) 0x2f7834 MOV	%RAX,-0xa0(%RBP)

(3586) 0x2f783b MOV	0x20(%RBP),%RAX

(3586) 0x2f783f MOV	(%RAX),%RCX

(3586) 0x2f7842 MOV	0x38(%RBP),%RAX

(3586) 0x2f7846 MOV	(%RAX),%RDX

(3586) 0x2f7849 MOV	-0x68(%RBP),%RAX

(3586) 0x2f784d LEA	0x60(%R9,%RAX,8),%R15

(3586) 0x2f7852 LEA	0x60(%RCX,%RAX,8),%R12

(3586) 0x2f7857 LEA	(%RAX,%R8,1),%RSI

(3586) 0x2f785b VPBROADCASTQ	%RDX,%YMM0

(3586) 0x2f7861 XOR	%EAX,%EAX

(3586) 0x2f7863 MOV	%RSI,-0x88(%RBP)

(3586) 0x2f786a JMP	2f789e

0x2f786c NOPL	(%RAX)

  (3588) 0x2f7870 MOV	%RAX,%RSI

  (3588) 0x2f7873 IMUL	-0x90(%RBP),%RSI

  (3588) 0x2f787b MOV	-0x98(%RBP),%R10

  (3588) 0x2f7882 INC	%RAX

  (3588) 0x2f7885 ADD	-0x30(%RBP),%RSI

  (3588) 0x2f7889 VADDSD	(%R14,%RSI,8),%XMM1,%XMM1

  (3588) 0x2f788f VMOVSD	%XMM1,(%R14,%RSI,8)

  (3588) 0x2f7895 CMP	%R10,%RAX

  (3588) 0x2f7898 JE	2f77d0

  (3588) 0x2f789e MOV	%RAX,%R10

  (3588) 0x2f78a1 IMUL	-0xa0(%RBP),%R10

  (3588) 0x2f78a9 MOV	-0x68(%RBP),%RSI

  (3588) 0x2f78ad VXORPD	%XMM1,%XMM1,%XMM1

  (3588) 0x2f78b1 CMP	$0x10,%R13

  (3588) 0x2f78b5 JB	2f7a60

  (3588) 0x2f78bb VPBROADCASTQ	%R10,%YMM2

  (3588) 0x2f78c1 VXORPD	%XMM1,%XMM1,%XMM1

  (3588) 0x2f78c5 VXORPD	%XMM3,%XMM3,%XMM3

  (3588) 0x2f78c9 VXORPD	%XMM4,%XMM4,%XMM4

  (3588) 0x2f78cd VXORPD	%XMM5,%XMM5,%XMM5

  (3588) 0x2f78d1 XOR	%ESI,%ESI

  (3588) 0x2f78d3 NOPW	%CS:(%RAX,%RAX,1)

    (3589) 0x2f78e0 VPMULLQ	-0x60(%R12,%RSI,8),%YMM0,%YMM6

    (3589) 0x2f78e8 VPMULLQ	-0x40(%R12,%RSI,8),%YMM0,%YMM7

    (3589) 0x2f78f0 VPMULLQ	-0x20(%R12,%RSI,8),%YMM0,%YMM8

    (3589) 0x2f78f8 VPMULLQ	(%R12,%RSI,8),%YMM0,%YMM9

    (3589) 0x2f78ff VPADDQ	%YMM2,%YMM6,%YMM6

    (3589) 0x2f7903 VPADDQ	%YMM2,%YMM7,%YMM7

    (3589) 0x2f7907 VPADDQ	%YMM2,%YMM8,%YMM8

    (3589) 0x2f790b VPADDQ	%YMM2,%YMM9,%YMM9

    (3589) 0x2f790f VEXTRACTI128	$0x1,%YMM6,%XMM10

    (3589) 0x2f7915 VMOVQ	%XMM6,%R14

    (3589) 0x2f791a VMOVQ	%XMM10,%R11

    (3589) 0x2f791f VMOVSD	(%RBX,%R11,8),%XMM11

    (3589) 0x2f7925 VPEXTRQ	$0x1,%XMM10,%R11

    (3589) 0x2f792b VMOVHPD	(%RBX,%R11,8),%XMM11,%XMM10

    (3589) 0x2f7931 VPEXTRQ	$0x1,%XMM6,%R11

    (3589) 0x2f7937 VMOVSD	(%RBX,%R14,8),%XMM6

    (3589) 0x2f793d VEXTRACTI128	$0x1,%YMM7,%XMM11

    (3589) 0x2f7943 VMOVQ	%XMM7,%R14

    (3589) 0x2f7948 VMOVHPD	(%RBX,%R11,8),%XMM6,%XMM6

    (3589) 0x2f794e VMOVQ	%XMM11,%R11

    (3589) 0x2f7953 VMOVSD	(%RBX,%R11,8),%XMM12

    (3589) 0x2f7959 VPEXTRQ	$0x1,%XMM11,%R11

    (3589) 0x2f795f VMOVHPD	(%RBX,%R11,8),%XMM12,%XMM11

    (3589) 0x2f7965 VPEXTRQ	$0x1,%XMM7,%R11

    (3589) 0x2f796b VMOVSD	(%RBX,%R14,8),%XMM7

    (3589) 0x2f7971 VEXTRACTI128	$0x1,%YMM8,%XMM12

    (3589) 0x2f7977 VPEXTRQ	$0x1,%XMM8,%R14

    (3589) 0x2f797d VMOVHPD	(%RBX,%R11,8),%XMM7,%XMM7

    (3589) 0x2f7983 VMOVQ	%XMM12,%R11

    (3589) 0x2f7988 VMOVSD	(%RBX,%R11,8),%XMM13

    (3589) 0x2f798e VPEXTRQ	$0x1,%XMM12,%R11

    (3589) 0x2f7994 VMOVHPD	(%RBX,%R11,8),%XMM13,%XMM12

    (3589) 0x2f799a VMOVQ	%XMM8,%R11

    (3589) 0x2f799f VEXTRACTI128	$0x1,%YMM9,%XMM8

    (3589) 0x2f79a5 VMOVSD	(%RBX,%R11,8),%XMM13

    (3589) 0x2f79ab VPEXTRQ	$0x1,%XMM8,%R11

    (3589) 0x2f79b1 VMOVHPD	(%RBX,%R14,8),%XMM13,%XMM13

    (3589) 0x2f79b7 VMOVQ	%XMM8,%R14

    (3589) 0x2f79bc VMOVSD	(%RBX,%R14,8),%XMM8

    (3589) 0x2f79c2 VMOVQ	%XMM9,%R14

    (3589) 0x2f79c7 VINSERTF128	$0x1,%XMM10,%YMM6,%YMM6

    (3589) 0x2f79cd VFMADD231PD	-0x60(%R15,%RSI,8),%YMM6,%YMM1

    (3589) 0x2f79d4 VMOVHPD	(%RBX,%R11,8),%XMM8,%XMM8

    (3589) 0x2f79da VPEXTRQ	$0x1,%XMM9,%R11

    (3589) 0x2f79e0 VMOVSD	(%RBX,%R14,8),%XMM9

    (3589) 0x2f79e6 VMOVHPD	(%RBX,%R11,8),%XMM9,%XMM9

    (3589) 0x2f79ec VINSERTF128	$0x1,%XMM11,%YMM7,%YMM7

    (3589) 0x2f79f2 VFMADD231PD	-0x40(%R15,%RSI,8),%YMM7,%YMM3

    (3589) 0x2f79f9 VINSERTF128	$0x1,%XMM12,%YMM13,%YMM10

    (3589) 0x2f79ff VFMADD231PD	-0x20(%R15,%RSI,8),%YMM10,%YMM4

    (3589) 0x2f7a06 VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

    (3589) 0x2f7a0c VFMADD231PD	(%R15,%RSI,8),%YMM8,%YMM5

    (3589) 0x2f7a12 ADD	$0x10,%RSI

    (3589) 0x2f7a16 CMP	%RSI,%R8

    (3589) 0x2f7a19 JNE	2f78e0

  (3588) 0x2f7a1f VADDPD	%YMM1,%YMM3,%YMM1

  (3588) 0x2f7a23 VADDPD	%YMM4,%YMM5,%YMM2

  (3588) 0x2f7a27 MOV	-0x88(%RBP),%RSI

  (3588) 0x2f7a2e MOV	-0x60(%RBP),%R14

  (3588) 0x2f7a32 VADDPD	%YMM1,%YMM2,%YMM1

  (3588) 0x2f7a36 VEXTRACTF128	$0x1,%YMM1,%XMM2

  (3588) 0x2f7a3c VADDPD	%XMM2,%XMM1,%XMM1

  (3588) 0x2f7a40 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (3588) 0x2f7a45 VADDSD	%XMM2,%XMM1,%XMM1

  (3588) 0x2f7a49 CMP	%R8,%R13

  (3588) 0x2f7a4c JE	2f7870

  (3588) 0x2f7a52 NOPW	%CS:(%RAX,%RAX,1)

    (3587) 0x2f7a60 MOV	(%RCX,%RSI,8),%R11

    (3587) 0x2f7a64 IMUL	%RDX,%R11

    (3587) 0x2f7a68 ADD	%R10,%R11

    (3587) 0x2f7a6b VMOVSD	(%RBX,%R11,8),%XMM2

    (3587) 0x2f7a71 VFMADD231SD	(%R9,%RSI,8),%XMM2,%XMM1

    (3587) 0x2f7a77 INC	%RSI

    (3587) 0x2f7a7a CMP	%RSI,%RDI

    (3587) 0x2f7a7d JNE	2f7a60

  (3588) 0x2f7a7f JMP	2f7870

0x2f7a84 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,194-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.63 to 0.85 cycles (12.51x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	86
nb uops	85
loop length	340
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.63
Dispatch	9.00
Overall L1	10.63

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.63 cycles. At this rate:

5% of peak load performance is reached (14.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.63 to 9.00 cycles (1.18x speedup).

ASM code

In the binary file, the address of the function is: 2f74e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2f758a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1416a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2f759c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x1413e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R12),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 2f779c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x2bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x60(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x60(%RDI),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2f7609 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x129>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JL 2f7578 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x98>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2f77e2 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x302>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,194-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	86
nb uops	85
loop length	340
used x86 registers	15
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.83	4.83	4.83	4.83	4.83	4.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.83	4.83	4.83	4.83	4.83	4.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.63
Dispatch	9.00
Overall L1	10.63

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.63 cycles. At this rate:

5% of peak load performance is reached (14.31 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.79 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2f74e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2f758a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1416a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %R13,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2f759c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x1413e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R12),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JNE 2f779c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x2bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x60(%RCX),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x60(%RDI),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2f7609 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x129>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JL 2f7578 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x98>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R10,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2f77e2 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x302>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9–	0.05	0.03
▼Loop 3590 - csr_matvec.c:181-196 - exec–	0.01	0.01
○Loop 3591 - csr_matvec.c:194-195 - exec	0.04	0.02
○Loop 3592 - csr_matvec.c:194-195 - exec	0.00	0.00
▼Loop 3586 - csr_matvec.c:181-204 - exec–	0.00	0.00
▼Loop 3588 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 3589 - csr_matvec.c:202-203 - exec	0.00	0.00
○Loop 3587 - csr_matvec.c:202-203 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code