OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 1.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

3412:                                  hypre_printf("Error in row %d ! Too many elements!\n",

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x2ee760 PUSH	%RBP

0x2ee761 MOV	%RSP,%RBP

0x2ee764 PUSH	%R15

0x2ee766 PUSH	%R14

0x2ee768 PUSH	%R13

0x2ee76a PUSH	%R12

0x2ee76c PUSH	%RBX

0x2ee76d SUB	$0x68,%RSP

0x2ee771 MOV	%R9,%R12

0x2ee774 MOV	%R8,-0x80(%RBP)

0x2ee778 MOV	%RCX,%RBX

0x2ee77b MOV	%RDX,%R13

0x2ee77e MOV	%RDI,-0x30(%RBP)

0x2ee782 CALL	303450 <hypre_NumActiveThreads>

0x2ee787 MOV	%RAX,%R15

0x2ee78a CALL	303460 <hypre_GetThreadNum>

0x2ee78f MOV	%RAX,%R14

0x2ee792 MOV	(%R13),%RAX

0x2ee796 LEA	0x1(%R14),%RCX

0x2ee79a CQTO

0x2ee79c IDIV	%R15

0x2ee79f CMP	%RDX,%R14

0x2ee7a2 JGE	2ee7b5

0x2ee7a4 LEA	0x1(%RAX),%R15

0x2ee7a8 MOV	%R15,%RSI

0x2ee7ab IMUL	%R14,%RSI

0x2ee7af IMUL	%RCX,%R15

0x2ee7b3 JMP	2ee7c9

0x2ee7b5 MOV	%RAX,%RSI

0x2ee7b8 IMUL	%R14,%RSI

0x2ee7bc IMUL	%RAX,%RCX

0x2ee7c0 ADD	%RDX,%RCX

0x2ee7c3 ADD	%RDX,%RSI

0x2ee7c6 MOV	%RCX,%R15

0x2ee7c9 MOV	(%RBX),%R8

0x2ee7cc MOV	%RBX,-0x48(%RBP)

0x2ee7d0 MOV	%RSI,%RBX

0x2ee7d3 MOVQ	$0,(%R8,%R14,8)

0x2ee7db CMP	%R15,%RSI

0x2ee7de JGE	2ee83f

0x2ee7e0 MOV	-0x80(%RBP),%RSI

0x2ee7e4 IMUL	%R14,%RAX

0x2ee7e8 CMP	%RDX,%R14

0x2ee7eb LEA	(%R8,%R14,8),%RCX

0x2ee7ef MOV	%R15,%RDI

0x2ee7f2 CMOVL	%R14,%RDX

0x2ee7f6 SUB	%RAX,%RDI

0x2ee7f9 SUB	%RDX,%RDI

0x2ee7fc MOV	(%RSI),%RSI

0x2ee7ff CMP	$0x4,%RDI

0x2ee803 JB	2ee824

0x2ee805 LEA	(%RSI,%R15,8),%R9

0x2ee809 CMP	%R9,%RCX

0x2ee80c JAE	2ef07f

0x2ee812 LEA	0x8(%R8,%R14,8),%R8

0x2ee817 LEA	(%RSI,%RBX,8),%R9

0x2ee81b CMP	%R8,%R9

0x2ee81e JAE	2ef07f

0x2ee824 XOR	%R10D,%R10D

0x2ee827 MOV	%RBX,%R9

0x2ee82a NOPW	(%RAX,%RAX,1)

(3404) 0x2ee830 ADD	(%RSI,%R9,8),%R10

(3404) 0x2ee834 INC	%R9

(3404) 0x2ee837 MOV	%R10,(%RCX)

(3404) 0x2ee83a CMP	%R15,%R9

(3404) 0x2ee83d JL	2ee830

0x2ee83f MOV	-0x30(%RBP),%RAX

0x2ee843 LEA	0x1c996(%RIP),%RDI

0x2ee84a MOV	(%RAX),%R13D

0x2ee84d MOV	%R13D,%ESI

0x2ee850 VZEROUPPER

0x2ee853 CALL	305f90 <@plt_start@+0x80>

0x2ee858 TEST	%R14,%R14

0x2ee85b JNE	2ee887

0x2ee85d CMPQ	$0,(%R12)

0x2ee862 JLE	2ee887

0x2ee864 MOV	-0x48(%RBP),%RAX

0x2ee868 XOR	%EDX,%EDX

0x2ee86a MOV	(%RAX),%RAX

0x2ee86d MOV	(%RAX),%RCX

(3403) 0x2ee870 ADD	0x8(%RAX,%RDX,8),%RCX

(3403) 0x2ee875 LEA	0x1(%RDX),%RSI

(3403) 0x2ee879 MOV	%RCX,0x8(%RAX,%RDX,8)

(3403) 0x2ee87e MOV	%RSI,%RDX

(3403) 0x2ee881 CMP	%RSI,(%R12)

(3403) 0x2ee885 JG	2ee870

0x2ee887 LEA	0x1c96a(%RIP),%RDI

0x2ee88e MOV	%R13D,%ESI

0x2ee891 CALL	305f90 <@plt_start@+0x80>

0x2ee896 TEST	%R14,%R14

0x2ee899 JE	2ee8b4

0x2ee89b MOV	-0x48(%RBP),%RAX

0x2ee89f MOV	(%RAX),%RAX

0x2ee8a2 MOV	-0x8(%RAX,%R14,8),%R12

0x2ee8a7 MOV	%RBX,%RDX

0x2ee8aa CMP	%R15,%RBX

0x2ee8ad JL	2ee8c3

0x2ee8af JMP	2ef070

0x2ee8b4 XOR	%R12D,%R12D

0x2ee8b7 MOV	%RBX,%RDX

0x2ee8ba CMP	%R15,%RBX

0x2ee8bd JGE	2ef070

0x2ee8c3 MOV	0x60(%RBP),%RSI

0x2ee8c7 XOR	%EAX,%EAX

0x2ee8c9 MOV	%RAX,-0x40(%RBP)

0x2ee8cd MOV	%R15,-0x38(%RBP)

0x2ee8d1 JMP	2ee910

(3390) 0x2ee8d3 MOV	%RCX,-0x30(%RBP)

(3390) 0x2ee8d7 MOV	%RAX,%RDI

(3390) 0x2ee8da MOV	0x60(%RBP),%RSI

(3390) 0x2ee8de MOV	-0x68(%RBP),%RDX

(3390) 0x2ee8e2 MOV	-0x30(%RBP),%R8

(3390) 0x2ee8e6 MOV	(%RSI),%RAX

(3390) 0x2ee8e9 MOV	0x38(%RAX),%RCX

(3390) 0x2ee8ed MOV	%R8,(%RCX,%RDX,8)

(3390) 0x2ee8f1 MOV	0x40(%RAX),%RAX

(3390) 0x2ee8f5 MOV	%RDI,(%RAX,%RDX,8)

(3390) 0x2ee8f9 MOV	-0x60(%RBP),%RDX

(3390) 0x2ee8fd NOPL	(%RAX)

(3390) 0x2ee900 MOV	-0x38(%RBP),%R15

(3390) 0x2ee904 INC	%RDX

(3390) 0x2ee907 CMP	%R15,%RDX

(3390) 0x2ee90a JGE	2ef070

(3390) 0x2ee910 MOV	0x10(%RBP),%RAX

(3390) 0x2ee914 MOV	-0x80(%RBP),%RDI

(3390) 0x2ee918 MOV	0x18(%RBP),%RCX

(3390) 0x2ee91c MOV	(%RAX),%RAX

(3390) 0x2ee91f MOV	(%RAX,%RDX,8),%RBX

(3390) 0x2ee923 MOV	(%RDI),%RAX

(3390) 0x2ee926 MOV	(%RAX,%RDX,8),%R15

(3390) 0x2ee92a MOV	(%RCX),%RAX

(3390) 0x2ee92d MOV	0x20(%RBP),%RCX

(3390) 0x2ee931 MOV	%RBX,%R8

(3390) 0x2ee934 MOV	(%RCX),%RCX

(3390) 0x2ee937 SUB	(%RAX,%RCX,8),%R8

(3390) 0x2ee93b JL	2eea00

(3390) 0x2ee941 CMP	%RBX,0x8(%RAX,%RCX,8)

(3390) 0x2ee946 JLE	2eea00

(3390) 0x2ee94c MOV	0x28(%RBP),%RAX

(3390) 0x2ee950 MOV	%RDX,-0x60(%RBP)

(3390) 0x2ee954 CMPQ	$0,(%RAX)

(3390) 0x2ee958 JE	2eeae1

(3390) 0x2ee95e MOV	0x30(%RBP),%RAX

(3390) 0x2ee962 MOV	0x38(%RBP),%RDX

(3390) 0x2ee966 MOV	0x40(%RBP),%RCX

(3390) 0x2ee96a MOV	(%RAX),%RAX

(3390) 0x2ee96d MOV	(%RAX,%R8,8),%RBX

(3390) 0x2ee971 MOV	(%RDX),%RAX

(3390) 0x2ee974 MOV	0x48(%RBP),%RDX

(3390) 0x2ee978 MOV	(%RAX,%R8,8),%RAX

(3390) 0x2ee97c MOV	%RAX,-0x30(%RBP)

(3390) 0x2ee980 MOV	(%RCX),%RAX

(3390) 0x2ee983 MOV	(%RAX,%R8,8),%RCX

(3390) 0x2ee987 MOV	(%RDX),%RAX

(3390) 0x2ee98a MOV	(%RAX,%R8,8),%R13

(3390) 0x2ee98e MOV	%RCX,%RAX

(3390) 0x2ee991 MOV	%RCX,-0x48(%RBP)

(3390) 0x2ee995 MOV	%R15,%RCX

(3390) 0x2ee998 SUB	%R13,%RAX

(3390) 0x2ee99b SUB	%RAX,%RCX

(3390) 0x2ee99e JLE	2eec88

(3390) 0x2ee9a4 MOV	$0x8,%ESI

(3390) 0x2ee9a9 MOV	%RCX,%RDI

(3390) 0x2ee9ac MOV	%RCX,-0x50(%RBP)

(3390) 0x2ee9b0 MOV	%R8,-0x68(%RBP)

(3390) 0x2ee9b4 CALL	301880 <hypre_CAlloc>

(3390) 0x2ee9b9 MOV	-0x50(%RBP),%RDI

(3390) 0x2ee9bd MOV	$0x8,%ESI

(3390) 0x2ee9c2 MOV	%RAX,-0x58(%RBP)

(3390) 0x2ee9c6 CALL	301880 <hypre_CAlloc>

(3390) 0x2ee9cb MOV	-0x58(%RBP),%RDI

(3390) 0x2ee9cf MOV	-0x68(%RBP),%R8

(3390) 0x2ee9d3 MOV	%RAX,%RDX

(3390) 0x2ee9d6 MOV	%RDX,-0x40(%RBP)

(3390) 0x2ee9da TEST	%R15,%R15

(3390) 0x2ee9dd JG	2eec9b

(3390) 0x2ee9e3 MOV	0x48(%RBP),%RAX

(3390) 0x2ee9e7 MOV	(%RAX),%RAX

(3390) 0x2ee9ea MOV	%R13,(%RAX,%R8,8)

(3390) 0x2ee9ee MOV	-0x38(%RBP),%R15

(3390) 0x2ee9f2 TEST	%RDI,%RDI

(3390) 0x2ee9f5 JNE	2ef04c

(3390) 0x2ee9fb JMP	2ef063

(3390) 0x2eea00 ADD	%R15,%R12

(3390) 0x2eea03 CMPQ	$0,(%RSI)

(3390) 0x2eea07 JE	2ee900

(3390) 0x2eea0d MOV	0xb8(%RBP),%RAX

(3390) 0x2eea14 MOV	(%RAX),%RDI

(3390) 0x2eea17 TEST	%RDI,%RDI

(3390) 0x2eea1a JLE	2ee900

(3390) 0x2eea20 TEST	%R15,%R15

(3390) 0x2eea23 JLE	2ee900

(3390) 0x2eea29 MOV	0xc0(%RBP),%RAX

(3390) 0x2eea30 MOV	%RDX,-0x60(%RBP)

(3390) 0x2eea34 XOR	%ECX,%ECX

(3390) 0x2eea36 XOR	%EDX,%EDX

(3390) 0x2eea38 MOV	(%RAX),%RAX

(3390) 0x2eea3b JMP	2eea56

0x2eea3d NOPL	(%RAX)

  (3391) 0x2eea40 MOV	0xb8(%RBP),%RDI

  (3391) 0x2eea47 MOV	(%RDI),%RDI

  (3391) 0x2eea4a ADD	%RSI,%RCX

  (3391) 0x2eea4d ADD	$0x2,%RDX

  (3391) 0x2eea51 CMP	%RDI,%RDX

  (3391) 0x2eea54 JGE	2eead0

  (3391) 0x2eea56 LEA	(,%RDX,8),%RSI

  (3391) 0x2eea5e OR	$0x8,%RSI

  (3391) 0x2eea62 MOV	(%RAX,%RSI,1),%RSI

  (3391) 0x2eea66 CMP	%RBX,(%RAX,%RDX,8)

  (3391) 0x2eea6a JNE	2eea4a

  (3391) 0x2eea6c TEST	%RSI,%RSI

  (3391) 0x2eea6f JLE	2eea4a

  (3391) 0x2eea71 MOV	0xc8(%RBP),%RDI

  (3391) 0x2eea78 MOV	0x50(%RBP),%R10

  (3391) 0x2eea7c XOR	%R9D,%R9D

  (3391) 0x2eea7f MOV	(%RDI),%R8

  (3391) 0x2eea82 MOV	(%R10),%RDI

  (3391) 0x2eea85 LEA	(%R8,%RCX,8),%R8

  (3391) 0x2eea89 JMP	2eea98

0x2eea8b NOPL	(%RAX,%RAX,1)

    (3392) 0x2eea90 INC	%R9

    (3392) 0x2eea93 CMP	%R15,%R9

    (3392) 0x2eea96 JE	2eea40

    (3392) 0x2eea98 MOV	0xd0(%RBP),%R10

    (3392) 0x2eea9f XOR	%R11D,%R11D

    (3392) 0x2eeaa2 MOV	(%R10),%R10

    (3392) 0x2eeaa5 JMP	2eeab8

0x2eeaa7 NOPW	(%RAX,%RAX,1)

      (3393) 0x2eeab0 INC	%R11

      (3393) 0x2eeab3 CMP	%R11,%RSI

      (3393) 0x2eeab6 JE	2eea90

      (3393) 0x2eeab8 MOV	(%R8,%R11,8),%R13

      (3393) 0x2eeabc CMP	%R13,(%RDI,%R9,8)

      (3393) 0x2eeac0 JNE	2eeab0

      (3393) 0x2eeac2 MOVQ	$-0x1,(%R8,%R11,8)

      (3393) 0x2eeaca INCQ	(%R10,%R14,8)

      (3393) 0x2eeace JMP	2eeab0

(3390) 0x2eead0 MOV	-0x60(%RBP),%RDX

(3390) 0x2eead4 MOV	-0x38(%RBP),%R15

(3390) 0x2eead8 MOV	0x60(%RBP),%RSI

(3390) 0x2eeadc JMP	2ee904

(3390) 0x2eeae1 MOV	(%RSI),%RAX

(3390) 0x2eeae4 MOV	%R8,-0x68(%RBP)

(3390) 0x2eeae8 MOV	0x38(%RAX),%RCX

(3390) 0x2eeaec MOV	0x40(%RAX),%RAX

(3390) 0x2eeaf0 MOV	(%RAX,%R8,8),%RAX

(3390) 0x2eeaf4 MOV	(%RCX,%R8,8),%RCX

(3390) 0x2eeaf8 TEST	%R15,%R15

(3390) 0x2eeafb JLE	2ee8d3

(3390) 0x2eeb01 MOV	0x68(%RBP),%RDX

(3390) 0x2eeb05 MOV	0x70(%RBP),%RDI

(3390) 0x2eeb09 MOV	%RCX,-0x30(%RBP)

(3390) 0x2eeb0d XOR	%ESI,%ESI

(3390) 0x2eeb0f MOV	(%RDX),%RDX

(3390) 0x2eeb12 MOV	%RDX,-0x58(%RBP)

(3390) 0x2eeb16 MOV	0x8(%RDX,%R8,8),%RDX

(3390) 0x2eeb1b MOV	%RDX,-0x90(%RBP)

(3390) 0x2eeb22 MOV	(%RDI),%RDX

(3390) 0x2eeb25 MOV	0xa8(%RBP),%RDI

(3390) 0x2eeb2c MOV	%RDX,-0x50(%RBP)

(3390) 0x2eeb30 MOV	0x8(%RDX,%R8,8),%RDX

(3390) 0x2eeb35 MOV	0x50(%RBP),%R8

(3390) 0x2eeb39 MOV	(%RDI),%R10

(3390) 0x2eeb3c MOV	0xb0(%RBP),%RDI

(3390) 0x2eeb43 MOV	%RDX,-0x88(%RBP)

(3390) 0x2eeb4a MOV	(%R8),%RDX

(3390) 0x2eeb4d MOV	0x58(%RBP),%R8

(3390) 0x2eeb51 MOV	%RDX,-0x48(%RBP)

(3390) 0x2eeb55 MOV	(%RDI),%RDX

(3390) 0x2eeb58 MOV	(%R8),%R11

(3390) 0x2eeb5b MOV	0x88(%RBP),%R8

(3390) 0x2eeb62 MOV	0x90(%RBP),%RDI

(3390) 0x2eeb69 MOV	%RDX,-0x78(%RBP)

(3390) 0x2eeb6d MOV	(%RDI),%RDX

(3390) 0x2eeb70 MOV	(%R8),%R8

(3390) 0x2eeb73 MOV	%RAX,%RDI

(3390) 0x2eeb76 MOV	%RDX,-0x70(%RBP)

(3390) 0x2eeb7a JMP	2eeb9d

  (3394) 0x2eeb7c VMOVQ	(%R11,%R12,8),%XMM0

  (3394) 0x2eeb82 MOV	-0x78(%RBP),%RDX

  (3394) 0x2eeb86 VMOVQ	%XMM0,(%RDX,%RDI,8)

  (3394) 0x2eeb8b MOV	%R13,%RDI

  (3394) 0x2eeb8e INC	%R12

  (3394) 0x2eeb91 INC	%RSI

  (3394) 0x2eeb94 CMP	%R15,%RSI

  (3394) 0x2eeb97 JE	2ee8da

  (3394) 0x2eeb9d MOV	-0x48(%RBP),%RDX

  (3394) 0x2eeba1 MOV	%RDI,%R13

  (3394) 0x2eeba4 MOV	0x78(%RBP),%RDI

  (3394) 0x2eeba8 MOV	(%RDX,%R12,8),%RDX

  (3394) 0x2eebac CMP	%RDX,(%RDI)

  (3394) 0x2eebaf JG	2eec10

  (3394) 0x2eebb1 MOV	0x80(%RBP),%RDI

  (3394) 0x2eebb8 CMP	%RDX,(%RDI)

  (3394) 0x2eebbb JL	2eec10

  (3394) 0x2eebbd MOV	-0x68(%RBP),%RDI

  (3394) 0x2eebc1 MOV	-0x58(%RBP),%R9

  (3394) 0x2eebc5 MOV	(%R9,%RDI,8),%RDI

  (3394) 0x2eebc9 CMP	%RCX,%RDI

  (3394) 0x2eebcc JGE	2eebde

  (3394) 0x2eebce XCHG	%AX,%AX

    (3396) 0x2eebd0 CMP	%RDX,(%R10,%RDI,8)

    (3396) 0x2eebd4 JE	2eeb7c

    (3396) 0x2eebd6 INC	%RDI

    (3396) 0x2eebd9 CMP	%RDI,%RCX

    (3396) 0x2eebdc JNE	2eebd0

  (3394) 0x2eebde MOV	-0x30(%RBP),%RDI

  (3394) 0x2eebe2 CMP	%RDI,-0x90(%RBP)

  (3394) 0x2eebe9 JLE	2eeeb1

  (3394) 0x2eebef MOV	%RDX,(%R10,%RDI,8)

  (3394) 0x2eebf3 MOV	-0x78(%RBP),%RDX

  (3394) 0x2eebf7 VMOVQ	(%R11,%R12,8),%XMM0

  (3394) 0x2eebfd VMOVQ	%XMM0,(%RDX,%RDI,8)

  (3394) 0x2eec02 INC	%RDI

  (3394) 0x2eec05 MOV	%RDI,-0x30(%RBP)

  (3394) 0x2eec09 JMP	2eeb8b

0x2eec0e XCHG	%AX,%AX

  (3394) 0x2eec10 MOV	-0x68(%RBP),%RDI

  (3394) 0x2eec14 MOV	-0x50(%RBP),%R9

  (3394) 0x2eec18 MOV	(%R9,%RDI,8),%RDI

  (3394) 0x2eec1c CMP	%RAX,%RDI

  (3394) 0x2eec1f JGE	2eec3e

  (3394) 0x2eec21 NOPW	%CS:(%RAX,%RAX,1)

    (3395) 0x2eec30 CMP	%RDX,(%R8,%RDI,8)

    (3395) 0x2eec34 JE	2eec79

    (3395) 0x2eec36 INC	%RDI

    (3395) 0x2eec39 CMP	%RDI,%RAX

    (3395) 0x2eec3c JNE	2eec30

  (3394) 0x2eec3e CMP	%R13,-0x88(%RBP)

  (3394) 0x2eec45 JLE	2eeeea

  (3394) 0x2eec4b MOV	%RDX,(%R8,%R13,8)

  (3394) 0x2eec4f MOV	-0x70(%RBP),%RDX

  (3394) 0x2eec53 MOV	%R13,%RDI

  (3394) 0x2eec56 INC	%RDI

  (3394) 0x2eec59 VMOVQ	(%R11,%R12,8),%XMM0

  (3394) 0x2eec5f VMOVQ	%XMM0,(%RDX,%R13,8)

  (3394) 0x2eec65 INC	%R12

  (3394) 0x2eec68 INC	%RSI

  (3394) 0x2eec6b CMP	%R15,%RSI

  (3394) 0x2eec6e JNE	2eeb9d

(3390) 0x2eec74 JMP	2ee8da

  (3394) 0x2eec79 VMOVQ	(%R11,%R12,8),%XMM0

  (3394) 0x2eec7f MOV	-0x70(%RBP),%RDX

  (3394) 0x2eec83 JMP	2eeb86

(3390) 0x2eec88 MOV	-0x40(%RBP),%RDX

(3390) 0x2eec8c XOR	%EDI,%EDI

(3390) 0x2eec8e MOV	%RDX,-0x40(%RBP)

(3390) 0x2eec92 TEST	%R15,%R15

(3390) 0x2eec95 JLE	2ee9e3

(3390) 0x2eec9b MOV	0x50(%RBP),%RAX

(3390) 0x2eec9f MOV	0x58(%RBP),%RCX

(3390) 0x2eeca3 MOV	(%RAX),%RAX

(3390) 0x2eeca6 MOV	(%RCX),%RCX

(3390) 0x2eeca9 TEST	%R13,%R13

(3390) 0x2eecac JLE	2eed39

(3390) 0x2eecb2 MOV	%R13,%R11

(3390) 0x2eecb5 XOR	%R10D,%R10D

(3390) 0x2eecb8 XOR	%EDX,%EDX

(3390) 0x2eecba JMP	2eecdf

0x2eecbc NOPL	(%RAX)

  (3401) 0x2eecc0 VMOVQ	(%RCX,%R12,8),%XMM0

  (3401) 0x2eecc6 MOV	-0x30(%RBP),%RSI

  (3401) 0x2eecca VMOVQ	%XMM0,(%RSI,%R9,8)

  (3401) 0x2eecd0 INC	%R12

  (3401) 0x2eecd3 INC	%RDX

  (3401) 0x2eecd6 CMP	%R15,%RDX

  (3401) 0x2eecd9 JE	2eed98

  (3401) 0x2eecdf MOV	(%RAX,%R12,8),%RSI

  (3401) 0x2eece3 XOR	%R9D,%R9D

  (3401) 0x2eece6 NOPW	%CS:(%RAX,%RAX,1)

    (3402) 0x2eecf0 CMP	%RSI,(%RBX,%R9,8)

    (3402) 0x2eecf4 JE	2eecc0

    (3402) 0x2eecf6 INC	%R9

    (3402) 0x2eecf9 CMP	%R9,%R13

    (3402) 0x2eecfc JNE	2eecf0

  (3401) 0x2eecfe CMP	%R11,-0x48(%RBP)

  (3401) 0x2eed02 JLE	2eed20

  (3401) 0x2eed04 MOV	%RSI,(%RBX,%R11,8)

  (3401) 0x2eed08 MOV	-0x30(%RBP),%RSI

  (3401) 0x2eed0c VMOVQ	(%RCX,%R12,8),%XMM0

  (3401) 0x2eed12 VMOVQ	%XMM0,(%RSI,%R11,8)

  (3401) 0x2eed18 INC	%R11

  (3401) 0x2eed1b JMP	2eecd0

0x2eed1d NOPL	(%RAX)

  (3401) 0x2eed20 MOV	%RSI,(%RDI,%R10,8)

  (3401) 0x2eed24 MOV	-0x40(%RBP),%RSI

  (3401) 0x2eed28 VMOVQ	(%RCX,%R12,8),%XMM0

  (3401) 0x2eed2e VMOVQ	%XMM0,(%RSI,%R10,8)

  (3401) 0x2eed34 INC	%R10

  (3401) 0x2eed37 JMP	2eecd0

(3390) 0x2eed39 MOV	%R13,%R11

(3390) 0x2eed3c XOR	%R10D,%R10D

(3390) 0x2eed3f JMP	2eed6f

0x2eed41 NOPW	%CS:(%RAX,%RAX,1)

  (3400) 0x2eed50 MOV	%RDX,(%RDI,%R10,8)

  (3400) 0x2eed54 MOV	-0x40(%RBP),%RDX

  (3400) 0x2eed58 VMOVQ	(%RCX,%R12,8),%XMM0

  (3400) 0x2eed5e VMOVQ	%XMM0,(%RDX,%R10,8)

  (3400) 0x2eed64 INC	%R10

  (3400) 0x2eed67 INC	%R12

  (3400) 0x2eed6a DEC	%R15

  (3400) 0x2eed6d JE	2eed98

  (3400) 0x2eed6f MOV	(%RAX,%R12,8),%RDX

  (3400) 0x2eed73 CMP	%R11,-0x48(%RBP)

  (3400) 0x2eed77 JLE	2eed50

  (3400) 0x2eed79 MOV	%RDX,(%RBX,%R11,8)

  (3400) 0x2eed7d MOV	-0x30(%RBP),%RDX

  (3400) 0x2eed81 VMOVQ	(%RCX,%R12,8),%XMM0

  (3400) 0x2eed87 VMOVQ	%XMM0,(%RDX,%R11,8)

  (3400) 0x2eed8d INC	%R11

  (3400) 0x2eed90 INC	%R12

  (3400) 0x2eed93 DEC	%R15

  (3400) 0x2eed96 JNE	2eed6f

(3390) 0x2eed98 MOV	0x48(%RBP),%RAX

(3390) 0x2eed9c LEA	(%R11,%R10,1),%RBX

(3390) 0x2eeda0 MOV	(%RAX),%RAX

(3390) 0x2eeda3 MOV	%RBX,(%RAX,%R8,8)

(3390) 0x2eeda7 TEST	%R10,%R10

(3390) 0x2eedaa JE	2eee3b

(3390) 0x2eedb0 MOV	0x30(%RBP),%R15

(3390) 0x2eedb4 MOV	%RDI,-0x58(%RBP)

(3390) 0x2eedb8 LEA	(,%RBX,8),%RSI

(3390) 0x2eedc0 MOV	%R11,-0x50(%RBP)

(3390) 0x2eedc4 MOV	%R8,%R13

(3390) 0x2eedc7 MOV	%R10,-0x48(%RBP)

(3390) 0x2eedcb MOV	%RSI,-0x30(%RBP)

(3390) 0x2eedcf MOV	(%R15),%RAX

(3390) 0x2eedd2 MOV	(%RAX,%R8,8),%RDI

(3390) 0x2eedd6 CALL	3018f0 <hypre_ReAlloc>

(3390) 0x2eeddb MOV	(%R15),%RCX

(3390) 0x2eedde MOV	0x38(%RBP),%R15

(3390) 0x2eede2 MOV	-0x30(%RBP),%RSI

(3390) 0x2eede6 MOV	%RAX,(%RCX,%R13,8)

(3390) 0x2eedea MOV	(%R15),%RAX

(3390) 0x2eeded MOV	(%RAX,%R13,8),%RDI

(3390) 0x2eedf1 CALL	3018f0 <hypre_ReAlloc>

(3390) 0x2eedf6 MOV	(%R15),%RCX

(3390) 0x2eedf9 MOV	-0x48(%RBP),%R11

(3390) 0x2eedfd MOV	%RAX,(%RCX,%R13,8)

(3390) 0x2eee01 MOV	0x40(%RBP),%RCX

(3390) 0x2eee05 MOV	(%RCX),%RAX

(3390) 0x2eee08 MOV	%RBX,(%RAX,%R13,8)

(3390) 0x2eee0c TEST	%R11,%R11

(3390) 0x2eee0f JLE	2eee4d

(3390) 0x2eee11 MOV	0x30(%RBP),%RAX

(3390) 0x2eee15 MOV	(%R15),%RCX

(3390) 0x2eee18 MOV	%R15,%RDX

(3390) 0x2eee1b MOV	(%RAX),%RAX

(3390) 0x2eee1e MOV	(%RCX,%R13,8),%RCX

(3390) 0x2eee22 MOV	(%RAX,%R13,8),%RAX

(3390) 0x2eee26 CMP	$0x4,%R11

(3390) 0x2eee2a JAE	2eee63

(3390) 0x2eee2c MOV	-0x38(%RBP),%R15

(3390) 0x2eee30 MOV	-0x58(%RBP),%RDI

(3390) 0x2eee34 XOR	%EDX,%EDX

(3390) 0x2eee36 JMP	2ef00c

(3390) 0x2eee3b MOV	-0x38(%RBP),%R15

(3390) 0x2eee3f TEST	%RDI,%RDI

(3390) 0x2eee42 JNE	2ef04c

(3390) 0x2eee48 JMP	2ef063

(3390) 0x2eee4d MOV	-0x38(%RBP),%R15

(3390) 0x2eee51 MOV	-0x58(%RBP),%RDI

(3390) 0x2eee55 TEST	%RDI,%RDI

(3390) 0x2eee58 JNE	2ef04c

(3390) 0x2eee5e JMP	2ef063

(3390) 0x2eee63 MOV	-0x50(%RBP),%RSI

(3390) 0x2eee67 MOV	-0x58(%RBP),%RDI

(3390) 0x2eee6b MOV	-0x38(%RBP),%R15

(3390) 0x2eee6f LEA	(%RAX,%RSI,8),%RDX

(3390) 0x2eee73 SUB	%RDI,%RDX

(3390) 0x2eee76 CMP	$0x80,%RDX

(3390) 0x2eee7d JB	2eef33

(3390) 0x2eee83 LEA	(%RCX,%RSI,8),%RDX

(3390) 0x2eee87 SUB	-0x40(%RBP),%RDX

(3390) 0x2eee8b CMP	$0x80,%RDX

(3390) 0x2eee92 JB	2eef33

(3390) 0x2eee98 LEA	(,%RSI,8),%RSI

(3390) 0x2eeea0 CMP	$0x10,%R11

(3390) 0x2eeea4 JAE	2eef42

(3390) 0x2eeeaa XOR	%EDX,%EDX

(3390) 0x2eeeac JMP	2eefb8

(3390) 0x2eeeb1 MOV	$0xd70,%ESI

(3390) 0x2eeeb6 MOV	$0x1,%EDX

(3390) 0x2eeebb LEA	-0xd6e8c(%RIP),%RDI

(3390) 0x2eeec2 XOR	%ECX,%ECX

(3390) 0x2eeec4 CALL	303e80 <hypre_error_handler>

(3390) 0x2eeec9 MOV	0x98(%RBP),%RAX

(3390) 0x2eeed0 MOV	0xa0(%RBP),%RCX

(3390) 0x2eeed7 LOCK INCQ	(%RAX)

(3390) 0x2eeedb CMPQ	$0,(%RCX)

(3390) 0x2eeedf JE	2eef3a

(3390) 0x2eeee1 LEA	-0xd9611(%RIP),%RDI

(3390) 0x2eeee8 JMP	2eef21

(3390) 0x2eeeea MOV	$0xd4e,%ESI

(3390) 0x2eeeef MOV	$0x1,%EDX

(3390) 0x2eeef4 LEA	-0xd6ec5(%RIP),%RDI

(3390) 0x2eeefb XOR	%ECX,%ECX

(3390) 0x2eeefd CALL	303e80 <hypre_error_handler>

(3390) 0x2eef02 MOV	0x98(%RBP),%RAX

(3390) 0x2eef09 MOV	0xa0(%RBP),%RCX

(3390) 0x2eef10 LOCK INCQ	(%RAX)

(3390) 0x2eef14 CMPQ	$0,(%RCX)

(3390) 0x2eef18 JE	2eef3a

(3390) 0x2eef1a LEA	-0xdaa8b(%RIP),%RDI

(3390) 0x2eef21 MOV	%RBX,%RSI

(3390) 0x2eef24 XOR	%EAX,%EAX

(3390) 0x2eef26 CALL	301a80 <hypre_printf>

(3390) 0x2eef2b MOV	%R13,%RDI

(3390) 0x2eef2e JMP	2ee8da

(3390) 0x2eef33 XOR	%EDX,%EDX

(3390) 0x2eef35 JMP	2ef00c

(3390) 0x2eef3a MOV	%R13,%RDI

(3390) 0x2eef3d JMP	2ee8da

(3390) 0x2eef42 MOV	-0x40(%RBP),%R10

(3390) 0x2eef46 MOV	%R11,%RDX

(3390) 0x2eef49 LEA	0x40(%RAX,%RSI,1),%R11

(3390) 0x2eef4e LEA	0x40(%RCX,%RSI,1),%R8

(3390) 0x2eef53 AND	$-0x10,%RDX

(3390) 0x2eef57 XOR	%R9D,%R9D

(3390) 0x2eef5a NOPW	(%RAX,%RAX,1)

  (3398) 0x2eef60 VMOVUPS	(%RDI,%R9,8),%ZMM0

  (3398) 0x2eef67 VMOVUPS	0x40(%RDI,%R9,8),%ZMM1

  (3398) 0x2eef6f VMOVUPS	%ZMM0,-0x40(%R11,%R9,8)

  (3398) 0x2eef77 VMOVUPS	%ZMM1,(%R11,%R9,8)

  (3398) 0x2eef7e VMOVDQU64	(%R10,%R9,8),%ZMM0

  (3398) 0x2eef85 VMOVDQU64	0x40(%R10,%R9,8),%ZMM1

  (3398) 0x2eef8d VMOVDQU64	%ZMM0,-0x40(%R8,%R9,8)

  (3398) 0x2eef95 VMOVDQU64	%ZMM1,(%R8,%R9,8)

  (3398) 0x2eef9c ADD	$0x10,%R9

  (3398) 0x2eefa0 CMP	%R9,%RDX

  (3398) 0x2eefa3 JNE	2eef60

(3390) 0x2eefa5 MOV	-0x48(%RBP),%R11

(3390) 0x2eefa9 CMP	%RDX,%R11

(3390) 0x2eefac JE	2ef04c

(3390) 0x2eefb2 TEST	$0xc,%R11B

(3390) 0x2eefb6 JE	2ef008

(3390) 0x2eefb8 MOV	%RDX,%R10

(3390) 0x2eefbb MOV	%R11,%RDX

(3390) 0x2eefbe AND	$-0x4,%RDX

(3390) 0x2eefc2 MOV	-0x40(%RBP),%R9

(3390) 0x2eefc6 LEA	(%RAX,%RSI,1),%R8

(3390) 0x2eefca ADD	%RCX,%RSI

(3390) 0x2eefcd ADD	%RDX,-0x50(%RBP)

(3390) 0x2eefd1 NOPW	%CS:(%RAX,%RAX,1)

  (3399) 0x2eefe0 VMOVUPS	(%RDI,%R10,8),%YMM0

  (3399) 0x2eefe6 VMOVUPS	%YMM0,(%R8,%R10,8)

  (3399) 0x2eefec VMOVDQU	(%R9,%R10,8),%YMM0

  (3399) 0x2eeff2 VMOVDQU	%YMM0,(%RSI,%R10,8)

  (3399) 0x2eeff8 ADD	$0x4,%R10

  (3399) 0x2eeffc CMP	%R10,%RDX

  (3399) 0x2eefff JNE	2eefe0

(3390) 0x2ef001 CMP	%RDX,%R11

(3390) 0x2ef004 JNE	2ef00c

(3390) 0x2ef006 JMP	2ef04c

(3390) 0x2ef008 ADD	%RDX,-0x50(%RBP)

(3390) 0x2ef00c MOV	-0x50(%RBP),%RSI

(3390) 0x2ef010 MOV	-0x40(%RBP),%R8

(3390) 0x2ef014 SUB	%RDX,%R11

(3390) 0x2ef017 XOR	%R9D,%R9D

(3390) 0x2ef01a LEA	(%RCX,%RSI,8),%RCX

(3390) 0x2ef01e LEA	(%RAX,%RSI,8),%RAX

(3390) 0x2ef022 LEA	(%R8,%RDX,8),%RSI

(3390) 0x2ef026 LEA	(%RDI,%RDX,8),%RDX

(3390) 0x2ef02a NOPW	(%RAX,%RAX,1)

  (3397) 0x2ef030 MOV	(%RDX,%R9,8),%R8

  (3397) 0x2ef034 MOV	%R8,(%RAX,%R9,8)

  (3397) 0x2ef038 VMOVQ	(%RSI,%R9,8),%XMM0

  (3397) 0x2ef03e VMOVQ	%XMM0,(%RCX,%R9,8)

  (3397) 0x2ef044 INC	%R9

  (3397) 0x2ef047 CMP	%R9,%R11

  (3397) 0x2ef04a JNE	2ef030

(3390) 0x2ef04c VZEROUPPER

(3390) 0x2ef04f CALL	301970 <hypre_Free>

(3390) 0x2ef054 MOV	-0x40(%RBP),%RDI

(3390) 0x2ef058 CALL	301970 <hypre_Free>

(3390) 0x2ef05d XOR	%EAX,%EAX

(3390) 0x2ef05f MOV	%RAX,-0x40(%RBP)

(3390) 0x2ef063 MOV	-0x60(%RBP),%RDX

(3390) 0x2ef067 MOV	0x60(%RBP),%RSI

(3390) 0x2ef06b JMP	2ee904

0x2ef070 ADD	$0x68,%RSP

0x2ef074 POP	%RBX

0x2ef075 POP	%R12

0x2ef077 POP	%R13

0x2ef079 POP	%R14

0x2ef07b POP	%R15

0x2ef07d POP	%RBP

0x2ef07e RET

0x2ef07f CMP	$0x20,%RDI

0x2ef083 JAE	2ef090

0x2ef085 XOR	%R10D,%R10D

0x2ef088 XOR	%R8D,%R8D

0x2ef08b JMP	2ef132

0x2ef090 LEA	0xc0(%RSI,%RBX,8),%R9

0x2ef098 MOV	%RDI,%R8

0x2ef09b AND	$-0x20,%R8

0x2ef09f VPXOR	%XMM0,%XMM0,%XMM0

0x2ef0a3 VPXOR	%XMM1,%XMM1,%XMM1

0x2ef0a7 VPXOR	%XMM2,%XMM2,%XMM2

0x2ef0ab VPXOR	%XMM3,%XMM3,%XMM3

0x2ef0af XOR	%R10D,%R10D

0x2ef0b2 NOPW	%CS:(%RAX,%RAX,1)

(3405) 0x2ef0c0 VPADDQ	-0xc0(%R9,%R10,8),%ZMM0,%ZMM0

(3405) 0x2ef0c8 VPADDQ	-0x80(%R9,%R10,8),%ZMM1,%ZMM1

(3405) 0x2ef0d0 VPADDQ	-0x40(%R9,%R10,8),%ZMM2,%ZMM2

(3405) 0x2ef0d8 VPADDQ	(%R9,%R10,8),%ZMM3,%ZMM3

(3405) 0x2ef0df ADD	$0x20,%R10

(3405) 0x2ef0e3 CMP	%R10,%R8

(3405) 0x2ef0e6 JNE	2ef0c0

0x2ef0e8 VPADDQ	%ZMM0,%ZMM1,%ZMM0

0x2ef0ee VPADDQ	%ZMM2,%ZMM3,%ZMM2

0x2ef0f4 VPADDQ	%ZMM0,%ZMM2,%ZMM0

0x2ef0fa VEXTRACTI64X4	$0x1,%ZMM0,%YMM1

0x2ef101 VPADDQ	%ZMM1,%ZMM0,%ZMM0

0x2ef107 VEXTRACTI128	$0x1,%YMM0,%XMM1

0x2ef10d VPADDQ	%XMM1,%XMM0,%XMM0

0x2ef111 VPSHUFD	$0x4e,%XMM0,%XMM1

0x2ef116 VPADDQ	%XMM1,%XMM0,%XMM0

0x2ef11a VMOVQ	%XMM0,(%RCX)

0x2ef11e CMP	%R8,%RDI

0x2ef121 JE	2ee83f

0x2ef127 VMOVQ	%XMM0,%R10

0x2ef12c TEST	$0x1c,%DIL

0x2ef130 JE	2ef189

0x2ef132 SAL	$0x3,%RDX

0x2ef136 MOV	%RDI,%R11

0x2ef139 AND	$-0x4,%R11

0x2ef13d VMOVQ	%R10,%XMM0

0x2ef142 LEA	(%RDX,%RAX,8),%RAX

0x2ef146 LEA	(%RBX,%R11,1),%R9

0x2ef14a ADD	%RSI,%RAX

0x2ef14d NOPL	(%RAX)

(3406) 0x2ef150 VPADDQ	(%RAX,%R8,8),%YMM0,%YMM0

(3406) 0x2ef156 ADD	$0x4,%R8

(3406) 0x2ef15a CMP	%R8,%R11

(3406) 0x2ef15d JNE	2ef150

0x2ef15f VEXTRACTI128	$0x1,%YMM0,%XMM1

0x2ef165 VPADDQ	%XMM1,%XMM0,%XMM0

0x2ef169 VPSHUFD	$0x4e,%XMM0,%XMM1

0x2ef16e VPADDQ	%XMM1,%XMM0,%XMM0

0x2ef172 VMOVQ	%XMM0,(%RCX)

0x2ef176 CMP	%R11,%RDI

0x2ef179 JE	2ee83f

0x2ef17f VMOVQ	%XMM0,%R10

0x2ef184 JMP	2ee830

0x2ef189 ADD	%RBX,%R8

0x2ef18c MOV	%R8,%R9

0x2ef18f JMP	2ee830

0x2ef194 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3352,3359-3368,3376-3377,3383-3392,3399-3412,3422-3426,3433-3446,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 5.75 cycles (3.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.63 to 15.75 cycles (1.25x speedup).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	161
nb uops	157
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00
cycles	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	12.00
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

all	32%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	29%

Vector efficiency ratios

all	22%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

2% of peak load performance is reached (5.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2ee760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 303450 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 303460 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																				scal (12.5%)
IDIV %R15	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ee7b5 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RAX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
JMP 2ee7c9 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x69>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%R8,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R8,%R14,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVL %R14,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2ee824 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xc4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef07f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%R14,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
LEA (%RSI,%RBX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef07f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1c996(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305f90 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 2ee887 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 2ee887 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1c96a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 305f90 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee8b4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x154>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 2ee8c3 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2ef070 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ef070 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2ee910 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP $0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef090 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x930>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2ef132 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA 0xc0(%RSI,%RBX,8),%R9	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VPADDQ %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST $0x1c,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 2ef189 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 2ee830 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2ee830 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 5.75 cycles (3.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	161
nb uops	157
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00
cycles	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	12.00
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

all	32%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	29%

Vector efficiency ratios

all	22%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

2% of peak load performance is reached (5.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2ee760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 303450 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 303460 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																				scal (12.5%)
IDIV %R15	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ee7b5 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RAX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
JMP 2ee7c9 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x69>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%R8,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R8,%R14,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVL %R14,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2ee824 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xc4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef07f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%R14,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
LEA (%RSI,%RBX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef07f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1c996(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305f90 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 2ee887 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 2ee887 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1c96a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 305f90 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee8b4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x154>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 2ee8c3 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2ef070 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ef070 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2ee910 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP $0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2ef090 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x930>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2ef132 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA 0xc0(%RSI,%RBX,8),%R9	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VPADDQ %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST $0x1c,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 2ef189 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2ee83f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 2ee830 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2ee830 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15–	1.07	0.57
▼Loop 3390 - IJMatrix_parcsr.c:3291-3484 - exec–	0.24	0.12
▼Loop 3394 - IJMatrix_parcsr.c:3383-3454 - exec–	0.82	0.41
○Loop 3396 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3395 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 3398 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3401 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
○Loop 3402 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 3399 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3397 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3400 - IJMatrix_parcsr.c:3316-3341 - exec	0.00	0.00
▼Loop 3391 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3392 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3393 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3405 - IJMatrix_parcsr.c:3275-3275 - exec	0.01	0.00
○Loop 3403 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 3406 - IJMatrix_parcsr.c:3275-3275 - exec	0.00	0.00
○Loop 3404 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00

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