OV - exec - Function hypre_BoomerAMGCoarsenPMIS.omp

	Function: hypre_BoomerAMGCoarsenPMIS.omp_outlined.19	Module: exec	Source: par_coarsen.c:2354-2381	Coverage (incl. loops): 0.93% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

0x259ac0 PUSH	%RBP

0x259ac1 MOV	%RSP,%RBP

0x259ac4 PUSH	%R15

0x259ac6 PUSH	%R14

0x259ac8 PUSH	%R13

0x259aca PUSH	%R12

0x259acc PUSH	%RBX

0x259acd SUB	$0x28,%RSP

0x259ad1 MOV	(%RDX),%R13

0x259ad4 TEST	%R13,%R13

0x259ad7 JLE	259b5e

0x259add MOV	(%RDI),%ESI

0x259adf DEC	%R13

0x259ae2 MOV	%R9,%R14

0x259ae5 MOV	%R8,%R15

0x259ae8 MOV	%RCX,%R12

0x259aeb MOVQ	$0,-0x40(%RBP)

0x259af3 MOVQ	$0x1,-0x48(%RBP)

0x259afb MOVL	$0,-0x38(%RBP)

0x259b02 MOV	%R13,-0x30(%RBP)

0x259b06 SUB	$0x8,%RSP

0x259b0a LEA	-0x48(%RBP),%RAX

0x259b0e LEA	0xade5b(%RIP),%RDI

0x259b15 LEA	-0x38(%RBP),%RCX

0x259b19 LEA	-0x40(%RBP),%R8

0x259b1d LEA	-0x30(%RBP),%R9

0x259b21 MOV	%ESI,-0x34(%RBP)

0x259b24 MOV	$0x22,%EDX

0x259b29 PUSH	$0x1

0x259b2b PUSH	$0x1

0x259b2d PUSH	%RAX

0x259b2e CALL	305fa0 <@plt_start@+0x90>

0x259b33 ADD	$0x20,%RSP

0x259b37 MOV	-0x30(%RBP),%RAX

0x259b3b CMP	%R13,%RAX

0x259b3e CMOVL	%RAX,%R13

0x259b42 MOV	-0x40(%RBP),%RAX

0x259b46 MOV	%R13,-0x30(%RBP)

0x259b4a CMP	%R13,%RAX

0x259b4d JLE	259b6d

0x259b4f MOV	-0x34(%RBP),%ESI

0x259b52 LEA	0xade2f(%RIP),%RDI

0x259b59 CALL	305fb0 <@plt_start@+0xa0>

0x259b5e ADD	$0x28,%RSP

0x259b62 POP	%RBX

0x259b63 POP	%R12

0x259b65 POP	%R13

0x259b67 POP	%R14

0x259b69 POP	%R15

0x259b6b POP	%RBP

0x259b6c RET

0x259b6d MOV	0x20(%RBP),%R11

0x259b71 MOV	0x10(%RBP),%R10

0x259b75 MOV	0x28(%RBP),%RCX

0x259b79 VMOVSD	-0x4a859(%RIP),%XMM0

0x259b81 MOV	(%R14),%R9

0x259b84 MOV	0x30(%RBP),%RDX

0x259b88 MOV	(%R12),%RDI

0x259b8c MOV	(%R15),%R8

0x259b8f MOV	(%R10),%R10

0x259b92 MOV	(%R11),%R11

0x259b95 MOV	(%RCX),%R14

0x259b98 JMP	259bb0

0x259b9a NOPW	(%RAX,%RAX,1)

(616) 0x259ba0 MOV	-0x30(%RBP),%R13

(616) 0x259ba4 LEA	0x1(%RAX),%RCX

(616) 0x259ba8 CMP	%R13,%RAX

(616) 0x259bab MOV	%RCX,%RAX

(616) 0x259bae JGE	259b4f

(616) 0x259bb0 MOV	(%RDI,%RAX,8),%R15

(616) 0x259bb4 VMOVSD	(%R8,%R15,8),%XMM1

(616) 0x259bba VUCOMISD	%XMM1,%XMM0

(616) 0x259bbe JAE	259ba4

(616) 0x259bc0 MOV	(%R9,%R15,8),%R12

(616) 0x259bc4 CMP	%R12,0x8(%R9,%R15,8)

(616) 0x259bc9 JLE	259c20

(616) 0x259bcb MOV	0x18(%RBP),%RCX

(616) 0x259bcf MOV	(%RCX),%RCX

(616) 0x259bd2 JMP	259bf2

0x259bd4 NOPW	%CS:(%RAX,%RAX,1)

  (618) 0x259be0 MOVQ	$0,(%RCX,%RBX,8)

  (618) 0x259be8 INC	%R12

  (618) 0x259beb CMP	%R12,0x8(%R9,%R15,8)

  (618) 0x259bf0 JLE	259c20

  (618) 0x259bf2 MOV	(%R10,%R12,8),%RBX

  (618) 0x259bf6 VMOVSD	(%R8,%RBX,8),%XMM2

  (618) 0x259bfc VUCOMISD	%XMM2,%XMM0

  (618) 0x259c00 JAE	259be8

  (618) 0x259c02 VUCOMISD	%XMM2,%XMM1

  (618) 0x259c06 JA	259be0

  (618) 0x259c08 VUCOMISD	%XMM1,%XMM2

  (618) 0x259c0c JBE	259be8

  (618) 0x259c0e MOVQ	$0,(%RCX,%R15,8)

  (618) 0x259c16 JMP	259be8

0x259c18 NOPL	(%RAX,%RAX,1)

(616) 0x259c20 MOV	(%R11,%R15,8),%R12

(616) 0x259c24 CMP	%R12,0x8(%R11,%R15,8)

(616) 0x259c29 JLE	259ba0

(616) 0x259c2f MOV	0x18(%RBP),%RCX

(616) 0x259c33 MOV	0x38(%RBP),%RSI

(616) 0x259c37 MOV	(%RCX),%R13

(616) 0x259c3a MOV	(%RSI),%RCX

(616) 0x259c3d JMP	259c56

0x259c3f NOP

  (617) 0x259c40 MOVQ	$0,(%RCX,%RBX,8)

  (617) 0x259c48 INC	%R12

  (617) 0x259c4b CMP	%R12,0x8(%R11,%R15,8)

  (617) 0x259c50 JLE	259ba0

  (617) 0x259c56 MOV	(%R14,%R12,8),%RBX

  (617) 0x259c5a MOV	(%RDX),%RSI

  (617) 0x259c5d ADD	%RBX,%RSI

  (617) 0x259c60 VMOVSD	(%R8,%RSI,8),%XMM2

  (617) 0x259c66 VUCOMISD	%XMM2,%XMM0

  (617) 0x259c6a JAE	259c48

  (617) 0x259c6c VUCOMISD	%XMM2,%XMM1

  (617) 0x259c70 JA	259c40

  (617) 0x259c72 VUCOMISD	%XMM1,%XMM2

  (617) 0x259c76 JBE	259c48

  (617) 0x259c78 MOVQ	$0,(%R13,%R15,8)

  (617) 0x259c81 JMP	259c48

0x259c83 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►97.07+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.70+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGCoarsenPMIS	par_coarsen.c:2354	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:601	exec
○	hypre_PCGSetup	pcg.c:234	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 1.00 cycles (8.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.25 to 0.59 cycles (13.95x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2356

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	68
nb uops	66
loop length	258
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	6.00
Overall L1	8.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.25 cycles. At this rate:

5% of peak load performance is reached (14.55 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.25 to 6.00 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 259ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 259b5e <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0x9e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xade5b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 259b6d <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0xad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0xade2f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD -0x4a859(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV (%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 259bb0 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.25 to 1.00 cycles (8.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2356

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 120 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	68
nb uops	66
loop length	258
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.25 cycles
front end	8.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.25
Dispatch	6.00
Overall L1	8.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.25 cycles. At this rate:

5% of peak load performance is reached (14.55 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 259ac0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 259b5e <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0x9e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x48(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xade5b(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 259b6d <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0xad>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0xade2f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x28,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x20(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD -0x4a859(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV (%R14),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 259bb0 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.19+0xf0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS.omp_outlined.19–	0.93	0.49
▼Loop 616 - par_coarsen.c:2356-2381 - exec–	0.07	0.03
○Loop 618 - par_coarsen.c:2361-2369 - exec	0.86	0.43
○Loop 617 - par_coarsen.c:2372-2381 - exec	0.00	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code