OV - exec - Function hypre_ParCSRComputeL1NormsThreads.omp

	Function: hypre_ParCSRComputeL1NormsThreads.omp_outlined	Module: exec	Source: ams.c:3363-3540 [...]	Coverage (incl. loops): 0.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3363 - 3540

--------------------------------------------------------------------------------

3363: #pragma omp parallel for private(i,ii,j,k,ns,ne,rest,size,diag,cf_diag) HYPRE_SMP_SCHEDULE

3364: #endif

3365:    for (k = 0; k < num_threads; k++)

3366:    {

3367:       size = num_rows/num_threads;

3368:       rest = num_rows - size*num_threads;

3369:       if (k < rest)

3370:       {

3371:          ns = k*size+k;

3372:          ne = (k+1)*size+k+1;

3373:       }

3374:       else

3375:       {

3376:          ns = k*size+rest;

3377:          ne = (k+1)*size+rest;

3378:       }

3379:

3380:       if (option == 1)

3381:       {

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

3395:                }

3396:             }

3397:             else

3398:             {

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3416:          for (i = ns; i < ne; i++)

3417:          {

3418:             l1_norm[i] = 0.0;

3419:             if (cf_marker == NULL)

3420:             {

3421:                /* Add the diagonal and the local off-thread part of the ith row */

3422:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3423:                {

3424:                   ii = A_diag_J[j];

3425:                   if (ii == i || ii < ns || ii >= ne)

3426:                      l1_norm[i] += fabs(A_diag_data[j]);

3427:                }

3428:                /* Add the l1 norm of the offd part of the ith row */

3429:                if (num_cols_offd)

3430:                {

3431:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3432:                      l1_norm[i] += fabs(A_offd_data[j]);

3433:                }

3434:             }

3435:             else

3436:             {

3437:                cf_diag = cf_marker[i];

3438:                /* Add the diagonal and the local off-thread part of the ith row */

3439:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3440:                {

3441:                   ii = A_diag_J[j];

3442:                   if ((ii == i || ii < ns || ii >= ne) &&

3443:                       (cf_diag == cf_marker[A_diag_J[j]]))

3444:                      l1_norm[i] += fabs(A_diag_data[j]);

3445:                }

3446:                /* Add the CF l1 norm of the offd part of the ith row */

3447:                if (num_cols_offd)

3448:                {

3449:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3450:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3451:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3458:          for (i = ns; i < ne; i++)

3459:          {

3460:             l1_norm[i] = 0.0;

3461:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3462:                l1_norm[i] += A_diag_data[j] * A_diag_data[j];

3463:             if (num_cols_offd)

3464:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3465:                   l1_norm[i] += A_offd_data[j] * A_offd_data[j];

3466:          }

3467:       }

3468:       else if (option == 4)

3469:       {

3470:          for (i = ns; i < ne; i++)

3471:          {

3472:             l1_norm[i] = 0.0;

3473:             if (cf_marker == NULL)

3474:             {

3475:                /* Add the diagonal and the local off-thread part of the ith row */

3476:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3477:                {

3478:                   ii = A_diag_J[j];

3479:                   if (ii == i || ii < ns || ii >= ne)

3480:                   {

3481:                      if (ii == i)

3482:                      {

3483:                         diag = fabs(A_diag_data[j]);

3484:                         l1_norm[i] += fabs(A_diag_data[j]);

3485:                      }

3486:                      else

3487:                         l1_norm[i] += 0.5*fabs(A_diag_data[j]);

3488:                   }

3489:                }

3490:                /* Add the l1 norm of the offd part of the ith row */

3491:                if (num_cols_offd)

3492:                {

3493:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3494:                      l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3495:                }

3496:             }

3497:             else

3498:             {

3499:                cf_diag = cf_marker[i];

3500:                /* Add the diagonal and the local off-thread part of the ith row */

3501:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3502:                {

3503:                   ii = A_diag_J[j];

3504:                   if ((ii == i || ii < ns || ii >= ne) &&

3505:                       (cf_diag == cf_marker[A_diag_J[j]]))

3506:                   {

3507:                      if (ii == i)

3508:                      {

3509:                         diag = fabs(A_diag_data[j]);

3510:                         l1_norm[i] += fabs(A_diag_data[j]);

3511:                      }

3512:                      else

3513:                         l1_norm[i] += 0.5*fabs(A_diag_data[j]);

3514:                   }

3515:                }

3516:                /* Add the CF l1 norm of the offd part of the ith row */

3517:                if (num_cols_offd)

3518:                {

3519:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3520:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3521:                         l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3522:                }

3523:             }

3524:

3525:             /* Truncate according to Remark 6.2 */

3526:             if (l1_norm[i] <= 4.0/3.0*diag)

3527:                l1_norm[i] = diag;

3528:          }

3529:       }

3530:

3531:       /* Handle negative definite matrices */

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

3535:

3536:       for (i = ns; i < ne; i++)

3537:          /* if (fabs(l1_norm[i]) < DBL_EPSILON) */

3538:          if (fabs(l1_norm[i]) == 0.0)

3539:          {

3540:             hypre_error_in_arg(1);

0x24efe0 PUSH	%RBP

0x24efe1 MOV	%RSP,%RBP

0x24efe4 PUSH	%R15

0x24efe6 PUSH	%R14

0x24efe8 PUSH	%R13

0x24efea PUSH	%R12

0x24efec PUSH	%RBX

0x24efed SUB	$0xa8,%RSP

0x24eff4 MOV	(%RDX),%RBX

0x24eff7 MOV	%R9,-0x70(%RBP)

0x24effb MOV	%R8,-0xc8(%RBP)

0x24f002 MOV	%RCX,-0xc0(%RBP)

0x24f009 MOV	%RDX,-0xb8(%RBP)

0x24f010 TEST	%RBX,%RBX

0x24f013 JLE	25089a

0x24f019 MOV	(%RDI),%ESI

0x24f01b DEC	%RBX

0x24f01e MOVQ	$0,-0xb0(%RBP)

0x24f029 MOVQ	$0x1,-0xd0(%RBP)

0x24f034 MOVL	$0,-0x90(%RBP)

0x24f03e MOV	%RBX,-0x88(%RBP)

0x24f045 SUB	$0x8,%RSP

0x24f049 LEA	-0xd0(%RBP),%RAX

0x24f050 LEA	0xb8571(%RIP),%RDI

0x24f057 LEA	-0x90(%RBP),%RCX

0x24f05e LEA	-0xb0(%RBP),%R8

0x24f065 LEA	-0x88(%RBP),%R9

0x24f06c MOV	%ESI,-0x8c(%RBP)

0x24f072 MOV	$0x22,%EDX

0x24f077 PUSH	$0x1

0x24f079 PUSH	$0x1

0x24f07b PUSH	%RAX

0x24f07c CALL	305fa0 <@plt_start@+0x90>

0x24f081 ADD	$0x20,%RSP

0x24f085 MOV	-0x88(%RBP),%RAX

0x24f08c MOV	-0xb0(%RBP),%R15

0x24f093 CMP	%RBX,%RAX

0x24f096 CMOVL	%RAX,%RBX

0x24f09a MOV	%RBX,-0x88(%RBP)

0x24f0a1 CMP	%RBX,%R15

0x24f0a4 JG	250885

0x24f0aa VMOVSD	-0x3fd32(%RIP),%XMM11

0x24f0b2 VMOVSD	-0x3fda2(%RIP),%XMM12

0x24f0ba VXORPD	%XMM10,%XMM10,%XMM10

0x24f0bf JMP	24f0ee

0x24f0c1 NOPW	%CS:(%RAX,%RAX,1)

(375) 0x24f0d0 MOV	-0x98(%RBP),%RBX

(375) 0x24f0d7 MOV	-0xa8(%RBP),%R15

(375) 0x24f0de MOV	-0xa0(%RBP),%R12

(375) 0x24f0e5 CMP	%RBX,%R12

(375) 0x24f0e8 JGE	250885

(375) 0x24f0ee MOV	-0xc0(%RBP),%RAX

(375) 0x24f0f5 MOV	-0xb8(%RBP),%RCX

(375) 0x24f0fc MOV	%RBX,-0x98(%RBP)

(375) 0x24f103 LEA	0x1(%R15),%R8

(375) 0x24f107 MOV	(%RAX),%RAX

(375) 0x24f10a CQTO

(375) 0x24f10c IDIVQ	(%RCX)

(375) 0x24f10f MOV	%RAX,%R14

(375) 0x24f112 CMP	%RDX,%R15

(375) 0x24f115 JGE	24f130

(375) 0x24f117 INC	%R14

(375) 0x24f11a MOV	%R14,%RAX

(375) 0x24f11d IMUL	%R15,%RAX

(375) 0x24f121 IMUL	%R8,%R14

(375) 0x24f125 JMP	24f141

0x24f127 NOPW	(%RAX,%RAX,1)

(375) 0x24f130 MOV	%R14,%RAX

(375) 0x24f133 IMUL	%R15,%RAX

(375) 0x24f137 IMUL	%R8,%R14

(375) 0x24f13b ADD	%RDX,%RAX

(375) 0x24f13e ADD	%RDX,%R14

(375) 0x24f141 MOV	-0xc8(%RBP),%RCX

(375) 0x24f148 MOV	%R8,-0xa8(%RBP)

(375) 0x24f14f MOV	%R15,-0xa0(%RBP)

(375) 0x24f156 MOV	(%RCX),%RCX

(375) 0x24f159 CMP	$0x3,%RCX

(375) 0x24f15d JE	24f2c0

(375) 0x24f163 CMP	$0x2,%RCX

(375) 0x24f167 JE	24f670

(375) 0x24f16d CMP	$0x1,%RCX

(375) 0x24f171 JNE	24f7d0

(375) 0x24f177 CMP	%R14,%RAX

(375) 0x24f17a JGE	250790

(375) 0x24f180 MOV	-0x70(%RBP),%RCX

(375) 0x24f184 MOV	0x18(%RBP),%RSI

(375) 0x24f188 MOV	0x28(%RBP),%R8

(375) 0x24f18c MOV	0x30(%RBP),%RDI

(375) 0x24f190 MOV	(%RSI),%R12

(375) 0x24f193 MOV	(%RCX),%RDX

(375) 0x24f196 MOV	0x10(%RBP),%RCX

(375) 0x24f19a MOV	(%RDI),%RSI

(375) 0x24f19d MOV	(%R8),%R9

(375) 0x24f1a0 MOV	(%RCX),%RCX

(375) 0x24f1a3 MOV	(%R12,%RAX,8),%RDI

(375) 0x24f1a7 MOV	%RSI,-0x48(%RBP)

(375) 0x24f1ab MOV	%R12,-0x38(%RBP)

(375) 0x24f1af TEST	%RCX,%RCX

(375) 0x24f1b2 JE	24fc1d

(375) 0x24f1b8 MOV	0x40(%RBP),%RSI

(375) 0x24f1bc MOV	(%RSI),%RSI

(375) 0x24f1bf TEST	%R9,%R9

(375) 0x24f1c2 JE	250437

(375) 0x24f1c8 MOV	0x48(%RBP),%R8

(375) 0x24f1cc MOV	0x50(%RBP),%R9

(375) 0x24f1d0 MOV	%RAX,%R10

(375) 0x24f1d3 MOV	(%R8),%R8

(375) 0x24f1d6 MOV	(%R9),%R9

(375) 0x24f1d9 JMP	24f1f7

0x24f1db NOPL	(%RAX,%RAX,1)

  (421) 0x24f1e0 MOV	-0x40(%RBP),%RBX

  (421) 0x24f1e4 MOV	-0x38(%RBP),%R12

  (421) 0x24f1e8 MOV	%R11,%RDI

  (421) 0x24f1eb MOV	%RBX,%R10

  (421) 0x24f1ee CMP	%R14,%RBX

  (421) 0x24f1f1 JE	250790

  (421) 0x24f1f7 MOVQ	$0,(%RDX,%R10,8)

  (421) 0x24f1ff VXORPD	%XMM0,%XMM0,%XMM0

  (421) 0x24f203 MOV	(%RCX,%R10,8),%RBX

  (421) 0x24f207 MOV	0x8(%R12,%R10,8),%R11

  (421) 0x24f20c CMP	%R11,%RDI

  (421) 0x24f20f JGE	24f250

  (421) 0x24f211 MOV	0x20(%RBP),%R15

  (421) 0x24f215 MOV	(%R15),%R15

  (421) 0x24f218 JMP	24f228

0x24f21a NOPW	(%RAX,%RAX,1)

    (423) 0x24f220 INC	%RDI

    (423) 0x24f223 CMP	%RDI,%R11

    (423) 0x24f226 JE	24f250

    (423) 0x24f228 MOV	(%RSI,%RDI,8),%R12

    (423) 0x24f22c CMP	%RBX,(%RCX,%R12,8)

    (423) 0x24f230 JNE	24f220

    (423) 0x24f232 VMOVSD	(%R15,%RDI,8),%XMM1

    (423) 0x24f238 VANDPD	-0x3ff0a(%RIP){1to2},%XMM1,%XMM1

    (423) 0x24f242 VADDSD	%XMM0,%XMM1,%XMM0

    (423) 0x24f246 VMOVSD	%XMM0,(%RDX,%R10,8)

    (423) 0x24f24c JMP	24f220

0x24f24e XCHG	%AX,%AX

  (421) 0x24f250 MOV	-0x48(%RBP),%R15

  (421) 0x24f254 LEA	0x1(%R10),%R12

  (421) 0x24f258 MOV	%R12,-0x40(%RBP)

  (421) 0x24f25c MOV	(%R15,%R10,8),%RDI

  (421) 0x24f260 MOV	(%R15,%R12,8),%R12

  (421) 0x24f264 CMP	%R12,%RDI

  (421) 0x24f267 JGE	24f1e0

  (421) 0x24f26d MOV	0x38(%RBP),%R15

  (421) 0x24f271 MOV	(%R15),%R13

  (421) 0x24f274 JMP	24f28c

0x24f276 NOPW	%CS:(%RAX,%RAX,1)

    (422) 0x24f280 INC	%RDI

    (422) 0x24f283 CMP	%RDI,%R12

    (422) 0x24f286 JE	24f1e0

    (422) 0x24f28c MOV	(%R9,%RDI,8),%R15

    (422) 0x24f290 CMP	%RBX,(%R8,%R15,8)

    (422) 0x24f294 JNE	24f280

    (422) 0x24f296 VMOVSD	(%R13,%RDI,8),%XMM1

    (422) 0x24f29d VANDPD	-0x3ff6f(%RIP){1to2},%XMM1,%XMM1

    (422) 0x24f2a7 VADDSD	%XMM1,%XMM0,%XMM0

    (422) 0x24f2ab VMOVSD	%XMM0,(%RDX,%R10,8)

    (422) 0x24f2b1 JMP	24f280

0x24f2b3 NOPW	%CS:(%RAX,%RAX,1)

(375) 0x24f2c0 CMP	%R14,%RAX

(375) 0x24f2c3 JGE	250790

(375) 0x24f2c9 MOV	0x18(%RBP),%RSI

(375) 0x24f2cd MOV	0x20(%RBP),%RDI

(375) 0x24f2d1 MOV	-0x70(%RBP),%RCX

(375) 0x24f2d5 MOV	0x28(%RBP),%R8

(375) 0x24f2d9 LEA	(,%RAX,8),%R9

(375) 0x24f2e1 MOV	%R9,-0x48(%RBP)

(375) 0x24f2e5 MOV	(%RSI),%RSI

(375) 0x24f2e8 MOV	(%RCX),%RDX

(375) 0x24f2eb MOV	(%RDI),%RDI

(375) 0x24f2ee CMPQ	$0,(%R8)

(375) 0x24f2f2 LEA	0x8(,%RAX,8),%RCX

(375) 0x24f2fa MOV	%RCX,-0x38(%RBP)

(375) 0x24f2fe MOV	(%RSI,%RAX,8),%R10

(375) 0x24f302 MOV	%RSI,-0x40(%RBP)

(375) 0x24f306 JE	24fff6

(375) 0x24f30c MOV	0x30(%RBP),%RCX

(375) 0x24f310 MOV	0x38(%RBP),%RSI

(375) 0x24f314 XOR	%R13D,%R13D

(375) 0x24f317 MOV	%RAX,%R9

(375) 0x24f31a MOV	(%RCX),%RCX

(375) 0x24f31d MOV	(%RSI),%R11

(375) 0x24f320 MOV	%RCX,-0x60(%RBP)

(375) 0x24f324 LEA	0xc0(%RDI),%RCX

(375) 0x24f32b MOV	%RCX,-0x68(%RBP)

(375) 0x24f32f LEA	0xc0(%R11),%RCX

(375) 0x24f336 MOV	%RCX,-0x78(%RBP)

(375) 0x24f33a JMP	24f34c

0x24f33c NOPL	(%RAX)

  (382) 0x24f340 INC	%R13

  (382) 0x24f343 CMP	%R14,%R9

  (382) 0x24f346 JE	250790

  (382) 0x24f34c MOV	-0x40(%RBP),%RSI

  (382) 0x24f350 MOV	-0x48(%RBP),%RCX

  (382) 0x24f354 MOV	-0x38(%RBP),%R8

  (382) 0x24f358 MOV	%R9,%RBX

  (382) 0x24f35b MOVQ	$0,(%RDX,%RBX,8)

  (382) 0x24f363 MOV	%R10,%R9

  (382) 0x24f366 VXORPD	%XMM0,%XMM0,%XMM0

  (382) 0x24f36a MOV	0x8(%RSI,%RBX,8),%R10

  (382) 0x24f36f LEA	(%RCX,%R13,8),%R12

  (382) 0x24f373 LEA	(%R8,%R13,8),%R15

  (382) 0x24f377 ADD	%RDX,%R12

  (382) 0x24f37a ADD	%RDX,%R15

  (382) 0x24f37d MOV	%R10,%RSI

  (382) 0x24f380 SUB	%R9,%RSI

  (382) 0x24f383 JLE	24f4e8

  (382) 0x24f389 CMP	$0x4,%RSI

  (382) 0x24f38d JB	24f4d0

  (382) 0x24f393 LEA	(%RDI,%R9,8),%R8

  (382) 0x24f397 LEA	(%RDI,%R10,8),%RCX

  (382) 0x24f39b CMP	%RCX,%R12

  (382) 0x24f39e JAE	24f3a9

  (382) 0x24f3a0 CMP	%R15,%R8

  (382) 0x24f3a3 JB	24f4d0

  (382) 0x24f3a9 MOV	%R8,-0x58(%RBP)

  (382) 0x24f3ad CMP	$0x20,%RSI

  (382) 0x24f3b1 JAE	24f3bf

  (382) 0x24f3b3 MOV	%R12,-0x30(%RBP)

  (382) 0x24f3b7 XOR	%R8D,%R8D

  (382) 0x24f3ba JMP	24f47a

  (382) 0x24f3bf MOV	-0x68(%RBP),%RCX

  (382) 0x24f3c3 MOV	%RSI,%R8

  (382) 0x24f3c6 AND	$-0x20,%R8

  (382) 0x24f3ca VXORPD	%XMM0,%XMM0,%XMM0

  (382) 0x24f3ce VXORPD	%XMM1,%XMM1,%XMM1

  (382) 0x24f3d2 VXORPD	%XMM2,%XMM2,%XMM2

  (382) 0x24f3d6 VXORPD	%XMM3,%XMM3,%XMM3

  (382) 0x24f3da MOV	%R15,-0x50(%RBP)

  (382) 0x24f3de XOR	%R15D,%R15D

  (382) 0x24f3e1 LEA	(%RCX,%R9,8),%RCX

  (382) 0x24f3e5 NOPW	%CS:(%RAX,%RAX,1)

    (387) 0x24f3f0 VMOVUPD	-0xc0(%RCX,%R15,8),%ZMM4

    (387) 0x24f3f8 VMOVUPD	-0x80(%RCX,%R15,8),%ZMM5

    (387) 0x24f400 VMOVUPD	-0x40(%RCX,%R15,8),%ZMM6

    (387) 0x24f408 VMOVUPD	(%RCX,%R15,8),%ZMM7

    (387) 0x24f40f ADD	$0x20,%R15

    (387) 0x24f413 VFMADD231PD	%ZMM4,%ZMM4,%ZMM0

    (387) 0x24f419 VFMADD231PD	%ZMM5,%ZMM5,%ZMM1

    (387) 0x24f41f VFMADD231PD	%ZMM6,%ZMM6,%ZMM2

    (387) 0x24f425 VFMADD231PD	%ZMM7,%ZMM7,%ZMM3

    (387) 0x24f42b CMP	%R15,%R8

    (387) 0x24f42e JNE	24f3f0

  (382) 0x24f430 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (382) 0x24f436 VADDPD	%ZMM2,%ZMM3,%ZMM2

  (382) 0x24f43c MOV	-0x50(%RBP),%R15

  (382) 0x24f440 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (382) 0x24f446 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (382) 0x24f44d VADDPD	%ZMM1,%ZMM0,%ZMM0

  (382) 0x24f453 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (382) 0x24f459 VADDPD	%XMM1,%XMM0,%XMM0

  (382) 0x24f45d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (382) 0x24f462 VADDSD	%XMM1,%XMM0,%XMM0

  (382) 0x24f466 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (382) 0x24f46b CMP	%R8,%RSI

  (382) 0x24f46e JE	24f4e8

  (382) 0x24f470 TEST	$0x1c,%SIL

  (382) 0x24f474 JE	24f4c7

  (382) 0x24f476 MOV	%R12,-0x30(%RBP)

  (382) 0x24f47a MOV	-0x58(%RBP),%R12

  (382) 0x24f47e MOV	%RSI,%RCX

  (382) 0x24f481 AND	$-0x4,%RCX

  (382) 0x24f485 VMOVQ	%XMM0,%XMM0

  (382) 0x24f489 ADD	%RCX,%R9

  (382) 0x24f48c NOPL	(%RAX)

    (388) 0x24f490 VMOVUPD	(%R12,%R8,8),%YMM1

    (388) 0x24f496 ADD	$0x4,%R8

    (388) 0x24f49a VFMADD231PD	%YMM1,%YMM1,%YMM0

    (388) 0x24f49f CMP	%R8,%RCX

    (388) 0x24f4a2 JNE	24f490

  (382) 0x24f4a4 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (382) 0x24f4aa MOV	-0x30(%RBP),%R12

  (382) 0x24f4ae VADDPD	%XMM1,%XMM0,%XMM0

  (382) 0x24f4b2 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (382) 0x24f4b7 VADDSD	%XMM1,%XMM0,%XMM0

  (382) 0x24f4bb VMOVSD	%XMM0,(%RDX,%RBX,8)

  (382) 0x24f4c0 CMP	%RCX,%RSI

  (382) 0x24f4c3 JNE	24f4d0

  (382) 0x24f4c5 JMP	24f4e8

  (382) 0x24f4c7 ADD	%R8,%R9

  (382) 0x24f4ca NOPW	(%RAX,%RAX,1)

    (386) 0x24f4d0 VMOVSD	(%RDI,%R9,8),%XMM1

    (386) 0x24f4d6 INC	%R9

    (386) 0x24f4d9 VFMADD231SD	%XMM1,%XMM1,%XMM0

    (386) 0x24f4de VMOVSD	%XMM0,(%RDX,%RBX,8)

    (386) 0x24f4e3 CMP	%R9,%R10

    (386) 0x24f4e6 JNE	24f4d0

  (382) 0x24f4e8 MOV	-0x60(%RBP),%RCX

  (382) 0x24f4ec LEA	0x1(%RBX),%R9

  (382) 0x24f4f0 MOV	(%RCX,%RBX,8),%R8

  (382) 0x24f4f4 MOV	(%RCX,%R9,8),%RSI

  (382) 0x24f4f8 MOV	%RSI,%RCX

  (382) 0x24f4fb SUB	%R8,%RCX

  (382) 0x24f4fe JLE	24f340

  (382) 0x24f504 CMP	$0x4,%RCX

  (382) 0x24f508 JB	24f650

  (382) 0x24f50e MOV	%R9,-0x30(%RBP)

  (382) 0x24f512 LEA	(%R11,%R8,8),%R9

  (382) 0x24f516 MOV	%R9,-0x58(%RBP)

  (382) 0x24f51a LEA	(%R11,%RSI,8),%R9

  (382) 0x24f51e CMP	%R9,%R12

  (382) 0x24f521 MOV	-0x58(%RBP),%R12

  (382) 0x24f525 JAE	24f535

  (382) 0x24f527 CMP	%R15,%R12

  (382) 0x24f52a JAE	24f535

  (382) 0x24f52c MOV	-0x30(%RBP),%R9

  (382) 0x24f530 JMP	24f650

  (382) 0x24f535 CMP	$0x20,%RCX

  (382) 0x24f539 JAE	24f543

  (382) 0x24f53b XOR	%R15D,%R15D

  (382) 0x24f53e JMP	24f5fd

  (382) 0x24f543 MOV	-0x78(%RBP),%R9

  (382) 0x24f547 MOV	%RCX,%R15

  (382) 0x24f54a AND	$-0x20,%R15

  (382) 0x24f54e VMOVQ	%XMM0,%XMM0

  (382) 0x24f552 VXORPD	%XMM1,%XMM1,%XMM1

  (382) 0x24f556 VXORPD	%XMM2,%XMM2,%XMM2

  (382) 0x24f55a VXORPD	%XMM3,%XMM3,%XMM3

  (382) 0x24f55e LEA	(%R9,%R8,8),%R12

  (382) 0x24f562 XOR	%R9D,%R9D

  (382) 0x24f565 NOPW	%CS:(%RAX,%RAX,1)

    (384) 0x24f570 VMOVUPD	-0xc0(%R12,%R9,8),%ZMM4

    (384) 0x24f578 VMOVUPD	-0x80(%R12,%R9,8),%ZMM5

    (384) 0x24f580 VMOVUPD	-0x40(%R12,%R9,8),%ZMM6

    (384) 0x24f588 VMOVUPD	(%R12,%R9,8),%ZMM7

    (384) 0x24f58f ADD	$0x20,%R9

    (384) 0x24f593 VFMADD231PD	%ZMM4,%ZMM4,%ZMM0

    (384) 0x24f599 VFMADD231PD	%ZMM5,%ZMM5,%ZMM1

    (384) 0x24f59f VFMADD231PD	%ZMM6,%ZMM6,%ZMM2

    (384) 0x24f5a5 VFMADD231PD	%ZMM7,%ZMM7,%ZMM3

    (384) 0x24f5ab CMP	%R9,%R15

    (384) 0x24f5ae JNE	24f570

  (382) 0x24f5b0 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (382) 0x24f5b6 VADDPD	%ZMM2,%ZMM3,%ZMM2

  (382) 0x24f5bc MOV	-0x30(%RBP),%R9

  (382) 0x24f5c0 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (382) 0x24f5c6 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (382) 0x24f5cd VADDPD	%ZMM1,%ZMM0,%ZMM0

  (382) 0x24f5d3 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (382) 0x24f5d9 VADDPD	%XMM1,%XMM0,%XMM0

  (382) 0x24f5dd VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (382) 0x24f5e2 VADDSD	%XMM1,%XMM0,%XMM0

  (382) 0x24f5e6 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (382) 0x24f5eb CMP	%R15,%RCX

  (382) 0x24f5ee JE	24f340

  (382) 0x24f5f4 TEST	$0x1c,%CL

  (382) 0x24f5f7 JE	24f64a

  (382) 0x24f5f9 MOV	-0x58(%RBP),%R12

  (382) 0x24f5fd MOV	%RCX,%R9

  (382) 0x24f600 AND	$-0x4,%R9

  (382) 0x24f604 VMOVQ	%XMM0,%XMM0

  (382) 0x24f608 ADD	%R9,%R8

  (382) 0x24f60b NOPL	(%RAX,%RAX,1)

    (385) 0x24f610 VMOVUPD	(%R12,%R15,8),%YMM1

    (385) 0x24f616 ADD	$0x4,%R15

    (385) 0x24f61a VFMADD231PD	%YMM1,%YMM1,%YMM0

    (385) 0x24f61f CMP	%R15,%R9

    (385) 0x24f622 JNE	24f610

  (382) 0x24f624 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (382) 0x24f62a VADDPD	%XMM1,%XMM0,%XMM0

  (382) 0x24f62e VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (382) 0x24f633 VADDSD	%XMM1,%XMM0,%XMM0

  (382) 0x24f637 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (382) 0x24f63c CMP	%R9,%RCX

  (382) 0x24f63f MOV	-0x30(%RBP),%R9

  (382) 0x24f643 JNE	24f650

  (382) 0x24f645 JMP	24f340

  (382) 0x24f64a ADD	%R15,%R8

  (382) 0x24f64d NOPL	(%RAX)

    (383) 0x24f650 VMOVSD	(%R11,%R8,8),%XMM1

    (383) 0x24f656 INC	%R8

    (383) 0x24f659 VFMADD231SD	%XMM1,%XMM1,%XMM0

    (383) 0x24f65e VMOVSD	%XMM0,(%RDX,%RBX,8)

    (383) 0x24f663 CMP	%R8,%RSI

    (383) 0x24f666 JNE	24f650

  (382) 0x24f668 JMP	24f340

0x24f66d NOPL	(%RAX)

(375) 0x24f670 CMP	%R14,%RAX

(375) 0x24f673 JGE	250790

(375) 0x24f679 MOV	-0x70(%RBP),%RCX

(375) 0x24f67d MOV	0x10(%RBP),%RDI

(375) 0x24f681 MOV	0x18(%RBP),%RSI

(375) 0x24f685 MOV	0x30(%RBP),%R8

(375) 0x24f689 MOV	(%RCX),%RDX

(375) 0x24f68c MOV	(%RDI),%R9

(375) 0x24f68f MOV	0x40(%RBP),%RDI

(375) 0x24f693 MOV	(%RSI),%R12

(375) 0x24f696 MOV	0x28(%RBP),%RSI

(375) 0x24f69a MOV	(%R8),%RCX

(375) 0x24f69d MOV	%RCX,-0x38(%RBP)

(375) 0x24f6a1 MOV	(%RDI),%RDI

(375) 0x24f6a4 MOV	(%RSI),%RSI

(375) 0x24f6a7 MOV	(%R12,%RAX,8),%RCX

(375) 0x24f6ab TEST	%R9,%R9

(375) 0x24f6ae JE	2501ad

(375) 0x24f6b4 TEST	%RSI,%RSI

(375) 0x24f6b7 JE	2504ae

(375) 0x24f6bd MOV	0x48(%RBP),%RSI

(375) 0x24f6c1 MOV	0x50(%RBP),%R8

(375) 0x24f6c5 MOV	%RAX,%R11

(375) 0x24f6c8 MOV	%R12,-0x60(%RBP)

(375) 0x24f6cc MOV	(%RSI),%RSI

(375) 0x24f6cf MOV	%RSI,-0x40(%RBP)

(375) 0x24f6d3 MOV	(%R8),%RSI

(375) 0x24f6d6 MOV	%RSI,-0x48(%RBP)

(375) 0x24f6da JMP	24f6f3

0x24f6dc NOPL	(%RAX)

  (398) 0x24f6e0 MOV	%RBX,%RCX

  (398) 0x24f6e3 MOV	%R12,%R11

  (398) 0x24f6e6 CMP	%R14,%R12

  (398) 0x24f6e9 MOV	-0x60(%RBP),%R12

  (398) 0x24f6ed JE	250790

  (398) 0x24f6f3 MOVQ	$0,(%RDX,%R11,8)

  (398) 0x24f6fb VXORPD	%XMM0,%XMM0,%XMM0

  (398) 0x24f6ff MOV	(%R9,%R11,8),%R15

  (398) 0x24f703 MOV	0x8(%R12,%R11,8),%RBX

  (398) 0x24f708 CMP	%RBX,%RCX

  (398) 0x24f70b JGE	24f760

  (398) 0x24f70d MOV	0x20(%RBP),%RSI

  (398) 0x24f711 MOV	(%RSI),%R12

  (398) 0x24f714 JMP	24f728

0x24f716 NOPW	%CS:(%RAX,%RAX,1)

    (400) 0x24f720 INC	%RCX

    (400) 0x24f723 CMP	%RCX,%RBX

    (400) 0x24f726 JE	24f760

    (400) 0x24f728 MOV	(%RDI,%RCX,8),%R8

    (400) 0x24f72c CMP	%RAX,%R8

    (400) 0x24f72f JL	24f73b

    (400) 0x24f731 CMP	%R11,%R8

    (400) 0x24f734 JE	24f73b

    (400) 0x24f736 CMP	%R14,%R8

    (400) 0x24f739 JL	24f720

    (400) 0x24f73b CMP	%R15,(%R9,%R8,8)

    (400) 0x24f73f JNE	24f720

    (400) 0x24f741 VMOVSD	(%R12,%RCX,8),%XMM1

    (400) 0x24f747 VANDPD	-0x40419(%RIP){1to2},%XMM1,%XMM1

    (400) 0x24f751 VADDSD	%XMM0,%XMM1,%XMM0

    (400) 0x24f755 VMOVSD	%XMM0,(%RDX,%R11,8)

    (400) 0x24f75b JMP	24f720

0x24f75d NOPL	(%RAX)

  (398) 0x24f760 MOV	-0x38(%RBP),%RSI

  (398) 0x24f764 LEA	0x1(%R11),%R12

  (398) 0x24f768 MOV	(%RSI,%R11,8),%RCX

  (398) 0x24f76c MOV	(%RSI,%R12,8),%R8

  (398) 0x24f770 CMP	%R8,%RCX

  (398) 0x24f773 JGE	24f6e0

  (398) 0x24f779 MOV	0x38(%RBP),%RSI

  (398) 0x24f77d MOV	(%RSI),%R13

  (398) 0x24f780 JMP	24f79c

0x24f782 NOPW	%CS:(%RAX,%RAX,1)

    (399) 0x24f790 INC	%RCX

    (399) 0x24f793 CMP	%RCX,%R8

    (399) 0x24f796 JE	24f6e0

    (399) 0x24f79c MOV	-0x48(%RBP),%RSI

    (399) 0x24f7a0 MOV	-0x40(%RBP),%R10

    (399) 0x24f7a4 MOV	(%RSI,%RCX,8),%RSI

    (399) 0x24f7a8 CMP	%R15,(%R10,%RSI,8)

    (399) 0x24f7ac JNE	24f790

    (399) 0x24f7ae VMOVSD	(%R13,%RCX,8),%XMM1

    (399) 0x24f7b5 VANDPD	-0x40487(%RIP){1to2},%XMM1,%XMM1

    (399) 0x24f7bf VADDSD	%XMM1,%XMM0,%XMM0

    (399) 0x24f7c3 VMOVSD	%XMM0,(%RDX,%R11,8)

    (399) 0x24f7c9 JMP	24f790

0x24f7cb NOPL	(%RAX,%RAX,1)

(375) 0x24f7d0 CMP	%R14,%RAX

(375) 0x24f7d3 JGE	250790

(375) 0x24f7d9 CMP	$0x4,%RCX

(375) 0x24f7dd JNE	250790

(375) 0x24f7e3 MOV	-0x70(%RBP),%RCX

(375) 0x24f7e7 MOV	0x18(%RBP),%R8

(375) 0x24f7eb MOV	0x40(%RBP),%RDI

(375) 0x24f7ef MOV	0x28(%RBP),%R9

(375) 0x24f7f3 MOV	0x10(%RBP),%RSI

(375) 0x24f7f7 XOR	%R13D,%R13D

(375) 0x24f7fa MOV	(%R8),%RBX

(375) 0x24f7fd MOV	(%RCX),%RDX

(375) 0x24f800 MOV	(%R9),%RCX

(375) 0x24f803 MOV	(%RDI),%R8

(375) 0x24f806 MOV	0x30(%RBP),%RDI

(375) 0x24f80a MOV	0x48(%RBP),%R9

(375) 0x24f80e MOV	(%RSI),%RSI

(375) 0x24f811 MOV	%RCX,-0x38(%RBP)

(375) 0x24f815 MOV	(%RDI),%RCX

(375) 0x24f818 MOV	0x50(%RBP),%RDI

(375) 0x24f81c MOV	%RBX,-0x30(%RBP)

(375) 0x24f820 MOV	%RCX,-0x58(%RBP)

(375) 0x24f824 MOV	(%R9),%RCX

(375) 0x24f827 LEA	(,%RAX,8),%R9

(375) 0x24f82f MOV	%R9,-0x50(%RBP)

(375) 0x24f833 MOV	%RCX,-0x40(%RBP)

(375) 0x24f837 MOV	(%RDI),%RCX

(375) 0x24f83a MOV	0x38(%RBP),%RDI

(375) 0x24f83e MOV	(%RDI),%R15

(375) 0x24f841 MOV	%RCX,-0x48(%RBP)

(375) 0x24f845 LEA	0x8(,%RAX,8),%RCX

(375) 0x24f84d MOV	%RCX,-0x68(%RBP)

(375) 0x24f851 LEA	0xc0(%R15),%RCX

(375) 0x24f858 MOV	%RCX,-0x78(%RBP)

(375) 0x24f85c MOV	%RAX,%RCX

(375) 0x24f85f JMP	24f87f

0x24f861 NOPW	%CS:(%RAX,%RAX,1)

  (401) 0x24f870 INC	%RCX

  (401) 0x24f873 INC	%R13

  (401) 0x24f876 CMP	%R14,%RCX

  (401) 0x24f879 JE	250790

  (401) 0x24f87f MOVQ	$0,(%RDX,%RCX,8)

  (401) 0x24f887 TEST	%RSI,%RSI

  (401) 0x24f88a JE	24f920

  (401) 0x24f890 MOV	(%RSI,%RCX,8),%R9

  (401) 0x24f894 MOV	(%RBX,%RCX,8),%RDI

  (401) 0x24f898 MOV	0x8(%RBX,%RCX,8),%R10

  (401) 0x24f89d VXORPD	%XMM0,%XMM0,%XMM0

  (401) 0x24f8a1 CMP	%R10,%RDI

  (401) 0x24f8a4 JGE	24f9a0

  (401) 0x24f8aa MOV	0x20(%RBP),%R11

  (401) 0x24f8ae MOV	(%R11),%R12

  (401) 0x24f8b1 JMP	24f8d4

    (407) 0x24f8b3 VFMADD231SD	%XMM11,%XMM1,%XMM0

    (407) 0x24f8b8 VMOVSD	%XMM0,(%RDX,%RCX,8)

    (407) 0x24f8bd NOPL	(%RAX)

    (407) 0x24f8c0 VMOVAPD	%XMM8,%XMM1

    (407) 0x24f8c4 INC	%RDI

    (407) 0x24f8c7 VMOVAPD	%XMM1,%XMM8

    (407) 0x24f8cb CMP	%RDI,%R10

    (407) 0x24f8ce JE	24f9a4

    (407) 0x24f8d4 MOV	(%R8,%RDI,8),%R11

    (407) 0x24f8d8 CMP	%R14,%R11

    (407) 0x24f8db JGE	24f8e7

    (407) 0x24f8dd CMP	%RAX,%R11

    (407) 0x24f8e0 JL	24f8e7

    (407) 0x24f8e2 CMP	%RCX,%R11

    (407) 0x24f8e5 JNE	24f8c0

    (407) 0x24f8e7 CMP	%R9,(%RSI,%R11,8)

    (407) 0x24f8eb JNE	24f8c0

    (407) 0x24f8ed VMOVSD	(%R12,%RDI,8),%XMM1

    (407) 0x24f8f3 VANDPD	-0x405c5(%RIP){1to2},%XMM1,%XMM1

    (407) 0x24f8fd CMP	%RCX,%R11

    (407) 0x24f900 JNE	24f8b3

    (407) 0x24f902 VADDSD	%XMM1,%XMM0,%XMM0

    (407) 0x24f906 VMOVSD	%XMM0,(%RDX,%RCX,8)

    (407) 0x24f90b INC	%RDI

    (407) 0x24f90e VMOVAPD	%XMM1,%XMM8

    (407) 0x24f912 CMP	%RDI,%R10

    (407) 0x24f915 JNE	24f8d4

  (401) 0x24f917 JMP	24f9a4

0x24f91c NOPL	(%RAX)

  (401) 0x24f920 MOV	(%RBX,%RCX,8),%RDI

  (401) 0x24f924 MOV	0x8(%RBX,%RCX,8),%R9

  (401) 0x24f929 VXORPD	%XMM0,%XMM0,%XMM0

  (401) 0x24f92d CMP	%R9,%RDI

  (401) 0x24f930 JGE	24fa0a

  (401) 0x24f936 MOV	0x20(%RBP),%R10

  (401) 0x24f93a MOV	(%R10),%R10

  (401) 0x24f93d JMP	24f95e

0x24f93f NOP

    (405) 0x24f940 VFMADD231SD	%XMM11,%XMM1,%XMM0

    (405) 0x24f945 VMOVSD	%XMM0,(%RDX,%RCX,8)

    (405) 0x24f94a VMOVAPD	%XMM8,%XMM1

    (405) 0x24f94e INC	%RDI

    (405) 0x24f951 VMOVAPD	%XMM1,%XMM8

    (405) 0x24f955 CMP	%RDI,%R9

    (405) 0x24f958 JE	24fa0e

    (405) 0x24f95e MOV	(%R8,%RDI,8),%R11

    (405) 0x24f962 CMP	%R14,%R11

    (405) 0x24f965 JGE	24f971

    (405) 0x24f967 CMP	%RAX,%R11

    (405) 0x24f96a JL	24f971

    (405) 0x24f96c CMP	%RCX,%R11

    (405) 0x24f96f JNE	24f94a

    (405) 0x24f971 VMOVSD	(%R10,%RDI,8),%XMM1

    (405) 0x24f977 VANDPD	-0x40649(%RIP){1to2},%XMM1,%XMM1

    (405) 0x24f981 CMP	%RCX,%R11

    (405) 0x24f984 JNE	24f940

    (405) 0x24f986 VADDSD	%XMM1,%XMM0,%XMM0

    (405) 0x24f98a VMOVSD	%XMM0,(%RDX,%RCX,8)

    (405) 0x24f98f INC	%RDI

    (405) 0x24f992 VMOVAPD	%XMM1,%XMM8

    (405) 0x24f996 CMP	%RDI,%R9

    (405) 0x24f999 JNE	24f95e

  (401) 0x24f99b JMP	24fa0e

0x24f99d NOPL	(%RAX)

  (401) 0x24f9a0 VMOVAPD	%XMM8,%XMM1

  (401) 0x24f9a4 CMPQ	$0,-0x38(%RBP)

  (401) 0x24f9a9 JE	24fc00

  (401) 0x24f9af MOV	-0x58(%RBP),%R10

  (401) 0x24f9b3 MOV	(%R10,%RCX,8),%RDI

  (401) 0x24f9b7 MOV	0x8(%R10,%RCX,8),%R10

  (401) 0x24f9bc CMP	%R10,%RDI

  (401) 0x24f9bf JGE	24fc00

  (401) 0x24f9c5 MOV	0x38(%RBP),%R11

  (401) 0x24f9c9 MOV	(%R11),%R11

  (401) 0x24f9cc JMP	24f9dc

0x24f9ce XCHG	%AX,%AX

    (406) 0x24f9d0 INC	%RDI

    (406) 0x24f9d3 CMP	%RDI,%R10

    (406) 0x24f9d6 JE	24fb40

    (406) 0x24f9dc MOV	-0x48(%RBP),%RBX

    (406) 0x24f9e0 MOV	-0x40(%RBP),%R12

    (406) 0x24f9e4 MOV	(%RBX,%RDI,8),%RBX

    (406) 0x24f9e8 CMP	%R9,(%R12,%RBX,8)

    (406) 0x24f9ec JNE	24f9d0

    (406) 0x24f9ee VMOVSD	(%R11,%RDI,8),%XMM2

    (406) 0x24f9f4 VANDPD	-0x406c6(%RIP){1to2},%XMM2,%XMM2

    (406) 0x24f9fe VFMADD231SD	%XMM11,%XMM2,%XMM0

    (406) 0x24fa03 VMOVSD	%XMM0,(%RDX,%RCX,8)

    (406) 0x24fa08 JMP	24f9d0

  (401) 0x24fa0a VMOVAPD	%XMM8,%XMM1

  (401) 0x24fa0e CMPQ	$0,-0x38(%RBP)

  (401) 0x24fa13 JE	24fc00

  (401) 0x24fa19 MOV	-0x58(%RBP),%RDI

  (401) 0x24fa1d MOV	(%RDI,%RCX,8),%R12

  (401) 0x24fa21 MOV	0x8(%RDI,%RCX,8),%R9

  (401) 0x24fa26 MOV	%R9,%RDI

  (401) 0x24fa29 SUB	%R12,%RDI

  (401) 0x24fa2c JLE	24fc00

  (401) 0x24fa32 CMP	$0x4,%RDI

  (401) 0x24fa36 JB	24fbd0

  (401) 0x24fa3c MOV	-0x50(%RBP),%R10

  (401) 0x24fa40 LEA	(%R15,%R12,8),%R11

  (401) 0x24fa44 MOV	%R11,-0x60(%RBP)

  (401) 0x24fa48 LEA	(%R15,%R9,8),%R11

  (401) 0x24fa4c LEA	(%R10,%R13,8),%R10

  (401) 0x24fa50 ADD	%RDX,%R10

  (401) 0x24fa53 CMP	%R11,%R10

  (401) 0x24fa56 MOV	-0x60(%RBP),%R11

  (401) 0x24fa5a JAE	24fa70

  (401) 0x24fa5c MOV	-0x68(%RBP),%R10

  (401) 0x24fa60 LEA	(%R10,%R13,8),%R10

  (401) 0x24fa64 ADD	%RDX,%R10

  (401) 0x24fa67 CMP	%R10,%R11

  (401) 0x24fa6a JB	24fbd0

  (401) 0x24fa70 CMP	$0x20,%RDI

  (401) 0x24fa74 JAE	24fa82

  (401) 0x24fa76 MOV	%R15,-0x80(%RBP)

  (401) 0x24fa7a XOR	%R10D,%R10D

  (401) 0x24fa7d JMP	24fb57

  (401) 0x24fa82 MOV	-0x78(%RBP),%R11

  (401) 0x24fa86 MOV	%RDI,%R10

  (401) 0x24fa89 AND	$-0x20,%R10

  (401) 0x24fa8d VMOVQ	%XMM0,%XMM0

  (401) 0x24fa91 VXORPD	%XMM2,%XMM2,%XMM2

  (401) 0x24fa95 VXORPD	%XMM3,%XMM3,%XMM3

  (401) 0x24fa99 VXORPD	%XMM4,%XMM4,%XMM4

  (401) 0x24fa9d XOR	%EBX,%EBX

  (401) 0x24fa9f LEA	(%R11,%R12,8),%R11

  (401) 0x24faa3 NOPW	%CS:(%RAX,%RAX,1)

    (403) 0x24fab0 VBROADCASTSD	-0x40782(%RIP),%ZMM5

    (403) 0x24faba VBROADCASTSD	-0x40744(%RIP),%ZMM9

    (403) 0x24fac4 VANDPD	-0xc0(%R11,%RBX,8),%ZMM5,%ZMM6

    (403) 0x24facc VANDPD	-0x80(%R11,%RBX,8),%ZMM5,%ZMM7

    (403) 0x24fad4 VANDPD	-0x40(%R11,%RBX,8),%ZMM5,%ZMM8

    (403) 0x24fadc VANDPD	(%R11,%RBX,8),%ZMM5,%ZMM5

    (403) 0x24fae3 ADD	$0x20,%RBX

    (403) 0x24fae7 VFMADD231PD	%ZMM6,%ZMM9,%ZMM0

    (403) 0x24faed VFMADD231PD	%ZMM7,%ZMM9,%ZMM2

    (403) 0x24faf3 VFMADD231PD	%ZMM8,%ZMM9,%ZMM3

    (403) 0x24faf9 VFMADD231PD	%ZMM5,%ZMM9,%ZMM4

    (403) 0x24faff CMP	%RBX,%R10

    (403) 0x24fb02 JNE	24fab0

  (401) 0x24fb04 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (401) 0x24fb0a VADDPD	%ZMM3,%ZMM4,%ZMM3

  (401) 0x24fb10 VADDPD	%ZMM0,%ZMM3,%ZMM0

  (401) 0x24fb16 VEXTRACTF64X4	$0x1,%ZMM0,%YMM2

  (401) 0x24fb1d VADDPD	%ZMM2,%ZMM0,%ZMM0

  (401) 0x24fb23 VEXTRACTF128	$0x1,%YMM0,%XMM2

  (401) 0x24fb29 VADDPD	%XMM2,%XMM0,%XMM0

  (401) 0x24fb2d VSHUFPD	$0x1,%XMM0,%XMM0,%XMM2

  (401) 0x24fb32 VADDSD	%XMM2,%XMM0,%XMM0

  (401) 0x24fb36 VMOVSD	%XMM0,(%RDX,%RCX,8)

  (401) 0x24fb3b CMP	%R10,%RDI

  (401) 0x24fb3e JNE	24fb49

  (401) 0x24fb40 MOV	-0x30(%RBP),%RBX

  (401) 0x24fb44 JMP	24fc00

  (401) 0x24fb49 TEST	$0x1c,%DIL

  (401) 0x24fb4d JE	24fbba

  (401) 0x24fb4f MOV	-0x30(%RBP),%RBX

  (401) 0x24fb53 MOV	%R15,-0x80(%RBP)

  (401) 0x24fb57 MOV	%RDI,%R11

  (401) 0x24fb5a AND	$-0x4,%R11

  (401) 0x24fb5e VMOVQ	%XMM0,%XMM0

  (401) 0x24fb62 ADD	%R11,%R12

  (401) 0x24fb65 NOPW	%CS:(%RAX,%RAX,1)

    (404) 0x24fb70 MOV	-0x60(%RBP),%R15

    (404) 0x24fb74 VMOVUPD	(%R15,%R10,8),%YMM2

    (404) 0x24fb7a ADD	$0x4,%R10

    (404) 0x24fb7e VANDPD	-0x40850(%RIP){1to4},%YMM2,%YMM2

    (404) 0x24fb88 VFMADD231PD	-0x40812(%RIP){1to4},%YMM2,%YMM0

    (404) 0x24fb92 CMP	%R10,%R11

    (404) 0x24fb95 JNE	24fb70

  (401) 0x24fb97 VEXTRACTF128	$0x1,%YMM0,%XMM2

  (401) 0x24fb9d MOV	-0x80(%RBP),%R15

  (401) 0x24fba1 VADDPD	%XMM2,%XMM0,%XMM0

  (401) 0x24fba5 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM2

  (401) 0x24fbaa VADDSD	%XMM2,%XMM0,%XMM0

  (401) 0x24fbae VMOVSD	%XMM0,(%RDX,%RCX,8)

  (401) 0x24fbb3 CMP	%R11,%RDI

  (401) 0x24fbb6 JNE	24fbd0

  (401) 0x24fbb8 JMP	24fc00

  (401) 0x24fbba MOV	-0x30(%RBP),%RBX

  (401) 0x24fbbe ADD	%R10,%R12

  (401) 0x24fbc1 NOPW	%CS:(%RAX,%RAX,1)

    (402) 0x24fbd0 VMOVSD	(%R15,%R12,8),%XMM2

    (402) 0x24fbd6 INC	%R12

    (402) 0x24fbd9 VANDPD	-0x408ab(%RIP){1to2},%XMM2,%XMM2

    (402) 0x24fbe3 VFMADD231SD	%XMM11,%XMM2,%XMM0

    (402) 0x24fbe8 VMOVSD	%XMM0,(%RDX,%RCX,8)

    (402) 0x24fbed CMP	%R12,%R9

    (402) 0x24fbf0 JNE	24fbd0

  (401) 0x24fbf2 NOPW	%CS:(%RAX,%RAX,1)

  (401) 0x24fc00 VMOVAPD	%XMM1,%XMM8

  (401) 0x24fc04 VMULSD	%XMM12,%XMM8,%XMM1

  (401) 0x24fc09 VUCOMISD	%XMM1,%XMM0

  (401) 0x24fc0d JA	24f870

  (401) 0x24fc13 VMOVSD	%XMM8,(%RDX,%RCX,8)

  (401) 0x24fc18 JMP	24f870

(375) 0x24fc1d MOV	0x20(%RBP),%RCX

(375) 0x24fc21 MOV	(%RCX),%R8

(375) 0x24fc24 LEA	(,%RAX,8),%RCX

(375) 0x24fc2c MOV	%RCX,-0x60(%RBP)

(375) 0x24fc30 LEA	0x8(,%RAX,8),%RCX

(375) 0x24fc38 MOV	%RCX,-0x58(%RBP)

(375) 0x24fc3c TEST	%R9,%R9

(375) 0x24fc3f JE	25053c

(375) 0x24fc45 MOV	0x38(%RBP),%RCX

(375) 0x24fc49 LEA	0xc0(%R8),%RSI

(375) 0x24fc50 XOR	%R13D,%R13D

(375) 0x24fc53 MOV	%RAX,%R10

(375) 0x24fc56 MOV	%RSI,-0x78(%RBP)

(375) 0x24fc5a MOV	(%RCX),%RCX

(375) 0x24fc5d LEA	0xc0(%RCX),%RSI

(375) 0x24fc64 MOV	%RSI,-0x80(%RBP)

(375) 0x24fc68 JMP	24fc7c

0x24fc6a NOPW	(%RAX,%RAX,1)

  (412) 0x24fc70 INC	%R13

  (412) 0x24fc73 CMP	%R14,%R10

  (412) 0x24fc76 JE	250790

  (412) 0x24fc7c MOV	-0x60(%RBP),%RSI

  (412) 0x24fc80 MOV	%R10,%RBX

  (412) 0x24fc83 MOVQ	$0,(%RDX,%RBX,8)

  (412) 0x24fc8b MOV	%RDI,%R10

  (412) 0x24fc8e VXORPD	%XMM0,%XMM0,%XMM0

  (412) 0x24fc92 MOV	0x8(%R12,%RBX,8),%RDI

  (412) 0x24fc97 LEA	(%RSI,%R13,8),%R15

  (412) 0x24fc9b MOV	-0x58(%RBP),%RSI

  (412) 0x24fc9f ADD	%RDX,%R15

  (412) 0x24fca2 LEA	(%RSI,%R13,8),%RSI

  (412) 0x24fca6 ADD	%RDX,%RSI

  (412) 0x24fca9 MOV	%RSI,-0x40(%RBP)

  (412) 0x24fcad MOV	%RDI,%RSI

  (412) 0x24fcb0 SUB	%R10,%RSI

  (412) 0x24fcb3 JLE	24fe41

  (412) 0x24fcb9 CMP	$0x4,%RSI

  (412) 0x24fcbd JB	24fe20

  (412) 0x24fcc3 LEA	(%R8,%R10,8),%R11

  (412) 0x24fcc7 LEA	(%R8,%RDI,8),%R9

  (412) 0x24fccb CMP	%R9,%R15

  (412) 0x24fcce JAE	24fcda

  (412) 0x24fcd0 CMP	-0x40(%RBP),%R11

  (412) 0x24fcd4 JB	24fe20

  (412) 0x24fcda MOV	%R11,-0x30(%RBP)

  (412) 0x24fcde CMP	$0x20,%RSI

  (412) 0x24fce2 JAE	24fcf0

  (412) 0x24fce4 MOV	%R15,-0x50(%RBP)

  (412) 0x24fce8 XOR	%R11D,%R11D

  (412) 0x24fceb JMP	24fdbd

  (412) 0x24fcf0 MOV	-0x78(%RBP),%R9

  (412) 0x24fcf4 MOV	%RSI,%R11

  (412) 0x24fcf7 AND	$-0x20,%R11

  (412) 0x24fcfb VXORPD	%XMM0,%XMM0,%XMM0

  (412) 0x24fcff VXORPD	%XMM1,%XMM1,%XMM1

  (412) 0x24fd03 VXORPD	%XMM2,%XMM2,%XMM2

  (412) 0x24fd07 VXORPD	%XMM3,%XMM3,%XMM3

  (412) 0x24fd0b XOR	%R12D,%R12D

  (412) 0x24fd0e LEA	(%R9,%R10,8),%R9

  (412) 0x24fd12 NOPW	%CS:(%RAX,%RAX,1)

    (417) 0x24fd20 VBROADCASTSD	-0x409f2(%RIP),%ZMM4

    (417) 0x24fd2a VANDPD	-0xc0(%R9,%R12,8),%ZMM4,%ZMM5

    (417) 0x24fd32 VANDPD	-0x80(%R9,%R12,8),%ZMM4,%ZMM7

    (417) 0x24fd3a VANDPD	-0x40(%R9,%R12,8),%ZMM4,%ZMM6

    (417) 0x24fd42 VANDPD	(%R9,%R12,8),%ZMM4,%ZMM4

    (417) 0x24fd49 ADD	$0x20,%R12

    (417) 0x24fd4d VADDPD	%ZMM0,%ZMM5,%ZMM0

    (417) 0x24fd53 VADDPD	%ZMM1,%ZMM7,%ZMM1

    (417) 0x24fd59 VADDPD	%ZMM2,%ZMM6,%ZMM2

    (417) 0x24fd5f VADDPD	%ZMM3,%ZMM4,%ZMM3

    (417) 0x24fd65 CMP	%R12,%R11

    (417) 0x24fd68 JNE	24fd20

  (412) 0x24fd6a VADDPD	%ZMM0,%ZMM1,%ZMM0

  (412) 0x24fd70 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (412) 0x24fd76 VADDPD	%ZMM0,%ZMM3,%ZMM0

  (412) 0x24fd7c VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (412) 0x24fd83 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (412) 0x24fd89 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (412) 0x24fd8f VADDPD	%XMM1,%XMM0,%XMM0

  (412) 0x24fd93 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (412) 0x24fd98 VADDSD	%XMM1,%XMM0,%XMM0

  (412) 0x24fd9c VMOVSD	%XMM0,(%RDX,%RBX,8)

  (412) 0x24fda1 CMP	%R11,%RSI

  (412) 0x24fda4 JNE	24fdaf

  (412) 0x24fda6 MOV	-0x38(%RBP),%R12

  (412) 0x24fdaa JMP	24fe41

  (412) 0x24fdaf TEST	$0x1c,%SIL

  (412) 0x24fdb3 JE	24fe10

  (412) 0x24fdb5 MOV	-0x38(%RBP),%R12

  (412) 0x24fdb9 MOV	%R15,-0x50(%RBP)

  (412) 0x24fdbd MOV	-0x30(%RBP),%R15

  (412) 0x24fdc1 MOV	%RSI,%R9

  (412) 0x24fdc4 AND	$-0x4,%R9

  (412) 0x24fdc8 VMOVQ	%XMM0,%XMM0

  (412) 0x24fdcc ADD	%R9,%R10

  (412) 0x24fdcf NOP

    (418) 0x24fdd0 VMOVUPD	(%R15,%R11,8),%YMM1

    (418) 0x24fdd6 ADD	$0x4,%R11

    (418) 0x24fdda VANDPD	-0x40aac(%RIP){1to4},%YMM1,%YMM1

    (418) 0x24fde4 VADDPD	%YMM0,%YMM1,%YMM0

    (418) 0x24fde8 CMP	%R11,%R9

    (418) 0x24fdeb JNE	24fdd0

  (412) 0x24fded VEXTRACTF128	$0x1,%YMM0,%XMM1

  (412) 0x24fdf3 MOV	-0x50(%RBP),%R15

  (412) 0x24fdf7 VADDPD	%XMM1,%XMM0,%XMM0

  (412) 0x24fdfb VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (412) 0x24fe00 VADDSD	%XMM1,%XMM0,%XMM0

  (412) 0x24fe04 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (412) 0x24fe09 CMP	%R9,%RSI

  (412) 0x24fe0c JNE	24fe20

  (412) 0x24fe0e JMP	24fe41

  (412) 0x24fe10 MOV	-0x38(%RBP),%R12

  (412) 0x24fe14 ADD	%R11,%R10

  (412) 0x24fe17 NOPW	(%RAX,%RAX,1)

    (416) 0x24fe20 VMOVSD	(%R8,%R10,8),%XMM1

    (416) 0x24fe26 INC	%R10

    (416) 0x24fe29 VANDPD	-0x40afb(%RIP){1to2},%XMM1,%XMM1

    (416) 0x24fe33 VADDSD	%XMM0,%XMM1,%XMM0

    (416) 0x24fe37 VMOVSD	%XMM0,(%RDX,%RBX,8)

    (416) 0x24fe3c CMP	%R10,%RDI

    (416) 0x24fe3f JNE	24fe20

  (412) 0x24fe41 MOV	-0x48(%RBP),%RSI

  (412) 0x24fe45 LEA	0x1(%RBX),%R10

  (412) 0x24fe49 MOV	(%RSI,%RBX,8),%R9

  (412) 0x24fe4d MOV	(%RSI,%R10,8),%RSI

  (412) 0x24fe51 MOV	%RSI,%R11

  (412) 0x24fe54 SUB	%R9,%R11

  (412) 0x24fe57 JLE	24fc70

  (412) 0x24fe5d CMP	$0x4,%R11

  (412) 0x24fe61 JB	24ffd0

  (412) 0x24fe67 MOV	%R13,-0x30(%RBP)

  (412) 0x24fe6b MOV	%R10,-0x50(%RBP)

  (412) 0x24fe6f LEA	(%RCX,%RSI,8),%R10

  (412) 0x24fe73 LEA	(%RCX,%R9,8),%R13

  (412) 0x24fe77 CMP	%R10,%R15

  (412) 0x24fe7a MOV	%R13,%R10

  (412) 0x24fe7d JAE	24fe92

  (412) 0x24fe7f CMP	-0x40(%RBP),%R10

  (412) 0x24fe83 JAE	24fe92

  (412) 0x24fe85 MOV	-0x50(%RBP),%R10

  (412) 0x24fe89 MOV	-0x30(%RBP),%R13

  (412) 0x24fe8d JMP	24ffd0

  (412) 0x24fe92 MOV	-0x30(%RBP),%R13

  (412) 0x24fe96 MOV	%R10,-0x68(%RBP)

  (412) 0x24fe9a CMP	$0x20,%R11

  (412) 0x24fe9e JAE	24fea8

  (412) 0x24fea0 XOR	%R15D,%R15D

  (412) 0x24fea3 JMP	24ff68

  (412) 0x24fea8 MOV	-0x80(%RBP),%R10

  (412) 0x24feac MOV	%R11,%R15

  (412) 0x24feaf AND	$-0x20,%R15

  (412) 0x24feb3 VMOVQ	%XMM0,%XMM0

  (412) 0x24feb7 VXORPD	%XMM1,%XMM1,%XMM1

  (412) 0x24febb VXORPD	%XMM2,%XMM2,%XMM2

  (412) 0x24febf VXORPD	%XMM3,%XMM3,%XMM3

  (412) 0x24fec3 LEA	(%R10,%R9,8),%R12

  (412) 0x24fec7 XOR	%R10D,%R10D

  (412) 0x24feca NOPW	(%RAX,%RAX,1)

    (414) 0x24fed0 VBROADCASTSD	-0x40ba2(%RIP),%ZMM4

    (414) 0x24feda VANDPD	-0xc0(%R12,%R10,8),%ZMM4,%ZMM5

    (414) 0x24fee2 VANDPD	-0x80(%R12,%R10,8),%ZMM4,%ZMM7

    (414) 0x24feea VANDPD	-0x40(%R12,%R10,8),%ZMM4,%ZMM6

    (414) 0x24fef2 VANDPD	(%R12,%R10,8),%ZMM4,%ZMM4

    (414) 0x24fef9 ADD	$0x20,%R10

    (414) 0x24fefd VADDPD	%ZMM0,%ZMM5,%ZMM0

    (414) 0x24ff03 VADDPD	%ZMM1,%ZMM7,%ZMM1

    (414) 0x24ff09 VADDPD	%ZMM2,%ZMM6,%ZMM2

    (414) 0x24ff0f VADDPD	%ZMM3,%ZMM4,%ZMM3

    (414) 0x24ff15 CMP	%R10,%R15

    (414) 0x24ff18 JNE	24fed0

  (412) 0x24ff1a VADDPD	%ZMM0,%ZMM1,%ZMM0

  (412) 0x24ff20 MOV	-0x38(%RBP),%R12

  (412) 0x24ff24 MOV	-0x50(%RBP),%R10

  (412) 0x24ff28 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (412) 0x24ff2e VADDPD	%ZMM0,%ZMM3,%ZMM0

  (412) 0x24ff34 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (412) 0x24ff3b VADDPD	%ZMM1,%ZMM0,%ZMM0

  (412) 0x24ff41 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (412) 0x24ff47 VADDPD	%XMM1,%XMM0,%XMM0

  (412) 0x24ff4b VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (412) 0x24ff50 VADDSD	%XMM1,%XMM0,%XMM0

  (412) 0x24ff54 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (412) 0x24ff59 CMP	%R15,%R11

  (412) 0x24ff5c JE	24fc70

  (412) 0x24ff62 TEST	$0x1c,%R11B

  (412) 0x24ff66 JE	24ffc8

  (412) 0x24ff68 MOV	-0x68(%RBP),%R13

  (412) 0x24ff6c MOV	%R11,%R10

  (412) 0x24ff6f AND	$-0x4,%R10

  (412) 0x24ff73 VMOVQ	%XMM0,%XMM0

  (412) 0x24ff77 ADD	%R10,%R9

  (412) 0x24ff7a NOPW	(%RAX,%RAX,1)

    (415) 0x24ff80 VMOVUPD	(%R13,%R15,8),%YMM1

    (415) 0x24ff87 ADD	$0x4,%R15

    (415) 0x24ff8b VANDPD	-0x40c5d(%RIP){1to4},%YMM1,%YMM1

    (415) 0x24ff95 VADDPD	%YMM0,%YMM1,%YMM0

    (415) 0x24ff99 CMP	%R15,%R10

    (415) 0x24ff9c JNE	24ff80

  (412) 0x24ff9e VEXTRACTF128	$0x1,%YMM0,%XMM1

  (412) 0x24ffa4 MOV	-0x30(%RBP),%R13

  (412) 0x24ffa8 VADDPD	%XMM1,%XMM0,%XMM0

  (412) 0x24ffac VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (412) 0x24ffb1 VADDSD	%XMM1,%XMM0,%XMM0

  (412) 0x24ffb5 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (412) 0x24ffba CMP	%R10,%R11

  (412) 0x24ffbd MOV	-0x50(%RBP),%R10

  (412) 0x24ffc1 JNE	24ffd0

  (412) 0x24ffc3 JMP	24fc70

  (412) 0x24ffc8 ADD	%R15,%R9

  (412) 0x24ffcb NOPL	(%RAX,%RAX,1)

    (413) 0x24ffd0 VMOVSD	(%RCX,%R9,8),%XMM1

    (413) 0x24ffd6 INC	%R9

    (413) 0x24ffd9 VANDPD	-0x40cab(%RIP){1to2},%XMM1,%XMM1

    (413) 0x24ffe3 VADDSD	%XMM0,%XMM1,%XMM0

    (413) 0x24ffe7 VMOVSD	%XMM0,(%RDX,%RBX,8)

    (413) 0x24ffec CMP	%R9,%RSI

    (413) 0x24ffef JNE	24ffd0

  (412) 0x24fff1 JMP	24fc70

(375) 0x24fff6 LEA	0xc0(%RDI),%RCX

(375) 0x24fffd XOR	%R11D,%R11D

(375) 0x250000 MOV	%RAX,%RBX

(375) 0x250003 JMP	25001f

0x250005 NOPW	%CS:(%RAX,%RAX,1)

  (378) 0x250010 INC	%RBX

  (378) 0x250013 INC	%R11

  (378) 0x250016 CMP	%R14,%RBX

  (378) 0x250019 JE	250790

  (378) 0x25001f MOV	-0x40(%RBP),%RSI

  (378) 0x250023 MOVQ	$0,(%RDX,%RBX,8)

  (378) 0x25002b MOV	%R10,%R9

  (378) 0x25002e MOV	0x8(%RSI,%RBX,8),%R10

  (378) 0x250033 MOV	%R10,%RSI

  (378) 0x250036 SUB	%R9,%RSI

  (378) 0x250039 JLE	250010

  (378) 0x25003b VXORPD	%XMM0,%XMM0,%XMM0

  (378) 0x25003f CMP	$0x4,%RSI

  (378) 0x250043 JB	250190

  (378) 0x250049 MOV	-0x48(%RBP),%R8

  (378) 0x25004d LEA	(%RDI,%R10,8),%R12

  (378) 0x250051 LEA	(%R8,%R11,8),%R15

  (378) 0x250055 LEA	(%RDI,%R9,8),%R8

  (378) 0x250059 ADD	%RDX,%R15

  (378) 0x25005c CMP	%R12,%R15

  (378) 0x25005f JAE	250075

  (378) 0x250061 MOV	-0x38(%RBP),%R15

  (378) 0x250065 LEA	(%R15,%R11,8),%R15

  (378) 0x250069 ADD	%RDX,%R15

  (378) 0x25006c CMP	%R15,%R8

  (378) 0x25006f JB	250190

  (378) 0x250075 CMP	$0x20,%RSI

  (378) 0x250079 JAE	250083

  (378) 0x25007b XOR	%R15D,%R15D

  (378) 0x25007e JMP	250136

  (378) 0x250083 LEA	(%RCX,%R9,8),%R12

  (378) 0x250087 MOV	%RSI,%R15

  (378) 0x25008a AND	$-0x20,%R15

  (378) 0x25008e VXORPD	%XMM0,%XMM0,%XMM0

  (378) 0x250092 VXORPD	%XMM1,%XMM1,%XMM1

  (378) 0x250096 VXORPD	%XMM2,%XMM2,%XMM2

  (378) 0x25009a VXORPD	%XMM3,%XMM3,%XMM3

  (378) 0x25009e XOR	%R13D,%R13D

  (378) 0x2500a1 NOPW	%CS:(%RAX,%RAX,1)

    (380) 0x2500b0 VMOVUPD	-0xc0(%R12,%R13,8),%ZMM4

    (380) 0x2500b8 VMOVUPD	-0x80(%R12,%R13,8),%ZMM5

    (380) 0x2500c0 VMOVUPD	-0x40(%R12,%R13,8),%ZMM6

    (380) 0x2500c8 VMOVUPD	(%R12,%R13,8),%ZMM7

    (380) 0x2500cf ADD	$0x20,%R13

    (380) 0x2500d3 VFMADD231PD	%ZMM4,%ZMM4,%ZMM0

    (380) 0x2500d9 VFMADD231PD	%ZMM5,%ZMM5,%ZMM1

    (380) 0x2500df VFMADD231PD	%ZMM6,%ZMM6,%ZMM2

    (380) 0x2500e5 VFMADD231PD	%ZMM7,%ZMM7,%ZMM3

    (380) 0x2500eb CMP	%R13,%R15

    (380) 0x2500ee JNE	2500b0

  (378) 0x2500f0 VADDPD	%ZMM0,%ZMM1,%ZMM0

  (378) 0x2500f6 VADDPD	%ZMM2,%ZMM3,%ZMM2

  (378) 0x2500fc VADDPD	%ZMM0,%ZMM2,%ZMM0

  (378) 0x250102 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (378) 0x250109 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (378) 0x25010f VEXTRACTF128	$0x1,%YMM0,%XMM1

  (378) 0x250115 VADDPD	%XMM1,%XMM0,%XMM0

  (378) 0x250119 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (378) 0x25011e VADDSD	%XMM1,%XMM0,%XMM0

  (378) 0x250122 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (378) 0x250127 CMP	%R15,%RSI

  (378) 0x25012a JE	250010

  (378) 0x250130 TEST	$0x1c,%SIL

  (378) 0x250134 JE	250186

  (378) 0x250136 MOV	%RSI,%R12

  (378) 0x250139 AND	$-0x4,%R12

  (378) 0x25013d VMOVQ	%XMM0,%XMM0

  (378) 0x250141 ADD	%R12,%R9

  (378) 0x250144 NOPW	%CS:(%RAX,%RAX,1)

    (381) 0x250150 VMOVUPD	(%R8,%R15,8),%YMM1

    (381) 0x250156 ADD	$0x4,%R15

    (381) 0x25015a VFMADD231PD	%YMM1,%YMM1,%YMM0

    (381) 0x25015f CMP	%R15,%R12

    (381) 0x250162 JNE	250150

  (378) 0x250164 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (378) 0x25016a VADDPD	%XMM1,%XMM0,%XMM0

  (378) 0x25016e VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (378) 0x250173 VADDSD	%XMM1,%XMM0,%XMM0

  (378) 0x250177 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (378) 0x25017c CMP	%R12,%RSI

  (378) 0x25017f JNE	250190

  (378) 0x250181 JMP	250010

  (378) 0x250186 ADD	%R15,%R9

  (378) 0x250189 NOPL	(%RAX)

    (379) 0x250190 VMOVSD	(%RDI,%R9,8),%XMM1

    (379) 0x250196 INC	%R9

    (379) 0x250199 VFMADD231SD	%XMM1,%XMM1,%XMM0

    (379) 0x25019e VMOVSD	%XMM0,(%RDX,%RBX,8)

    (379) 0x2501a3 CMP	%R9,%R10

    (379) 0x2501a6 JNE	250190

  (378) 0x2501a8 JMP	250010

(375) 0x2501ad TEST	%RSI,%RSI

(375) 0x2501b0 JE	250716

(375) 0x2501b6 MOV	0x38(%RBP),%R8

(375) 0x2501ba LEA	(,%RAX,8),%RSI

(375) 0x2501c2 XOR	%R15D,%R15D

(375) 0x2501c5 MOV	%R12,-0x60(%RBP)

(375) 0x2501c9 MOV	%RSI,-0x58(%RBP)

(375) 0x2501cd LEA	0x8(,%RAX,8),%RSI

(375) 0x2501d5 MOV	%RSI,-0x30(%RBP)

(375) 0x2501d9 MOV	(%R8),%R10

(375) 0x2501dc MOV	%RAX,%R8

(375) 0x2501df LEA	0xc0(%R10),%RSI

(375) 0x2501e6 MOV	%RSI,-0x68(%RBP)

(375) 0x2501ea JMP	2501fc

0x2501ec NOPL	(%RAX)

  (391) 0x2501f0 INC	%R15

  (391) 0x2501f3 CMP	%R14,%R8

  (391) 0x2501f6 JE	250790

  (391) 0x2501fc MOVQ	$0,(%RDX,%R8,8)

  (391) 0x250204 MOV	%RCX,%RSI

  (391) 0x250207 VXORPD	%XMM0,%XMM0,%XMM0

  (391) 0x25020b MOV	%R8,%R13

  (391) 0x25020e MOV	0x8(%R12,%R8,8),%RCX

  (391) 0x250213 CMP	%RCX,%RSI

  (391) 0x250216 JGE	250270

  (391) 0x250218 MOV	0x20(%RBP),%R8

  (391) 0x25021c MOV	(%R8),%R9

  (391) 0x25021f JMP	250252

0x250221 NOPW	%CS:(%RAX,%RAX,1)

    (395) 0x250230 VMOVSD	(%R9,%RSI,8),%XMM1

    (395) 0x250236 VANDPD	-0x40f08(%RIP){1to2},%XMM1,%XMM1

    (395) 0x250240 VADDSD	%XMM0,%XMM1,%XMM0

    (395) 0x250244 VMOVSD	%XMM0,(%RDX,%R13,8)

    (395) 0x25024a INC	%RSI

    (395) 0x25024d CMP	%RSI,%RCX

    (395) 0x250250 JE	250270

    (395) 0x250252 MOV	(%RDI,%RSI,8),%R8

    (395) 0x250256 CMP	%RAX,%R8

    (395) 0x250259 JL	250230

    (395) 0x25025b CMP	%R13,%R8

    (395) 0x25025e JE	250230

    (395) 0x250260 CMP	%R14,%R8

    (395) 0x250263 JL	25024a

    (395) 0x250265 JMP	250230

0x250267 NOPW	(%RAX,%RAX,1)

  (391) 0x250270 MOV	-0x38(%RBP),%RSI

  (391) 0x250274 LEA	0x1(%R13),%R8

  (391) 0x250278 MOV	(%RSI,%R13,8),%RBX

  (391) 0x25027c MOV	(%RSI,%R8,8),%R11

  (391) 0x250280 MOV	%R11,%RSI

  (391) 0x250283 SUB	%RBX,%RSI

  (391) 0x250286 JLE	2501f0

  (391) 0x25028c CMP	$0x4,%RSI

  (391) 0x250290 JB	250410

  (391) 0x250296 MOV	-0x58(%RBP),%R9

  (391) 0x25029a MOV	%R8,-0x48(%RBP)

  (391) 0x25029e MOV	%R15,-0x40(%RBP)

  (391) 0x2502a2 LEA	(%R9,%R15,8),%R8

  (391) 0x2502a6 LEA	(%R10,%RBX,8),%R15

  (391) 0x2502aa LEA	(%R10,%R11,8),%R9

  (391) 0x2502ae ADD	%RDX,%R8

  (391) 0x2502b1 CMP	%R9,%R8

  (391) 0x2502b4 MOV	%R15,%R9

  (391) 0x2502b7 MOV	-0x40(%RBP),%R15

  (391) 0x2502bb JAE	2502d6

  (391) 0x2502bd MOV	-0x30(%RBP),%R8

  (391) 0x2502c1 LEA	(%R8,%R15,8),%R8

  (391) 0x2502c5 ADD	%RDX,%R8

  (391) 0x2502c8 CMP	%R8,%R9

  (391) 0x2502cb JAE	2502d6

  (391) 0x2502cd MOV	-0x48(%RBP),%R8

  (391) 0x2502d1 JMP	250410

  (391) 0x2502d6 MOV	%R9,-0x50(%RBP)

  (391) 0x2502da CMP	$0x20,%RSI

  (391) 0x2502de JAE	2502e8

  (391) 0x2502e0 XOR	%R9D,%R9D

  (391) 0x2502e3 JMP	2503a9

  (391) 0x2502e8 MOV	-0x68(%RBP),%R8

  (391) 0x2502ec MOV	%RSI,%R9

  (391) 0x2502ef AND	$-0x20,%R9

  (391) 0x2502f3 VMOVQ	%XMM0,%XMM0

  (391) 0x2502f7 VXORPD	%XMM1,%XMM1,%XMM1

  (391) 0x2502fb VXORPD	%XMM2,%XMM2,%XMM2

  (391) 0x2502ff VXORPD	%XMM3,%XMM3,%XMM3

  (391) 0x250303 XOR	%R12D,%R12D

  (391) 0x250306 LEA	(%R8,%RBX,8),%R8

  (391) 0x25030a NOPW	(%RAX,%RAX,1)

    (393) 0x250310 VBROADCASTSD	-0x40fe2(%RIP),%ZMM4

    (393) 0x25031a VANDPD	-0xc0(%R8,%R12,8),%ZMM4,%ZMM5

    (393) 0x250322 VANDPD	-0x80(%R8,%R12,8),%ZMM4,%ZMM7

    (393) 0x25032a VANDPD	-0x40(%R8,%R12,8),%ZMM4,%ZMM6

    (393) 0x250332 VANDPD	(%R8,%R12,8),%ZMM4,%ZMM4

    (393) 0x250339 ADD	$0x20,%R12

    (393) 0x25033d VADDPD	%ZMM0,%ZMM5,%ZMM0

    (393) 0x250343 VADDPD	%ZMM1,%ZMM7,%ZMM1

    (393) 0x250349 VADDPD	%ZMM2,%ZMM6,%ZMM2

    (393) 0x25034f VADDPD	%ZMM3,%ZMM4,%ZMM3

    (393) 0x250355 CMP	%R12,%R9

    (393) 0x250358 JNE	250310

  (391) 0x25035a VADDPD	%ZMM0,%ZMM1,%ZMM0

  (391) 0x250360 MOV	-0x60(%RBP),%R12

  (391) 0x250364 MOV	-0x48(%RBP),%R8

  (391) 0x250368 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (391) 0x25036e VADDPD	%ZMM0,%ZMM3,%ZMM0

  (391) 0x250374 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (391) 0x25037b VADDPD	%ZMM1,%ZMM0,%ZMM0

  (391) 0x250381 VEXTRACTF128	$0x1,%YMM0,%XMM1

  (391) 0x250387 VADDPD	%XMM1,%XMM0,%XMM0

  (391) 0x25038b VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (391) 0x250390 VADDSD	%XMM1,%XMM0,%XMM0

  (391) 0x250394 VMOVSD	%XMM0,(%RDX,%R13,8)

  (391) 0x25039a CMP	%R9,%RSI

  (391) 0x25039d JE	2501f0

  (391) 0x2503a3 TEST	$0x1c,%SIL

  (391) 0x2503a7 JE	250408

  (391) 0x2503a9 MOV	-0x50(%RBP),%R15

  (391) 0x2503ad MOV	%RSI,%R8

  (391) 0x2503b0 AND	$-0x4,%R8

  (391) 0x2503b4 VMOVQ	%XMM0,%XMM0

  (391) 0x2503b8 ADD	%R8,%RBX

  (391) 0x2503bb NOPL	(%RAX,%RAX,1)

    (394) 0x2503c0 VMOVUPD	(%R15,%R9,8),%YMM1

    (394) 0x2503c6 ADD	$0x4,%R9

    (394) 0x2503ca VANDPD	-0x4109c(%RIP){1to4},%YMM1,%YMM1

    (394) 0x2503d4 VADDPD	%YMM0,%YMM1,%YMM0

    (394) 0x2503d8 CMP	%R9,%R8

    (394) 0x2503db JNE	2503c0

  (391) 0x2503dd VEXTRACTF128	$0x1,%YMM0,%XMM1

  (391) 0x2503e3 MOV	-0x40(%RBP),%R15

  (391) 0x2503e7 VADDPD	%XMM1,%XMM0,%XMM0

  (391) 0x2503eb VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (391) 0x2503f0 VADDSD	%XMM1,%XMM0,%XMM0

  (391) 0x2503f4 VMOVSD	%XMM0,(%RDX,%R13,8)

  (391) 0x2503fa CMP	%R8,%RSI

  (391) 0x2503fd MOV	-0x48(%RBP),%R8

  (391) 0x250401 JNE	250410

  (391) 0x250403 JMP	2501f0

  (391) 0x250408 ADD	%R9,%RBX

  (391) 0x25040b NOPL	(%RAX,%RAX,1)

    (392) 0x250410 VMOVSD	(%R10,%RBX,8),%XMM1

    (392) 0x250416 INC	%RBX

    (392) 0x250419 VANDPD	-0x410eb(%RIP){1to2},%XMM1,%XMM1

    (392) 0x250423 VADDSD	%XMM0,%XMM1,%XMM0

    (392) 0x250427 VMOVSD	%XMM0,(%RDX,%R13,8)

    (392) 0x25042d CMP	%RBX,%R11

    (392) 0x250430 JNE	250410

  (391) 0x250432 JMP	2501f0

(375) 0x250437 MOV	%RAX,%R8

(375) 0x25043a JMP	25044f

0x25043c NOPL	(%RAX)

  (419) 0x250440 INC	%R8

  (419) 0x250443 MOV	%R9,%RDI

  (419) 0x250446 CMP	%R14,%R8

  (419) 0x250449 JE	250790

  (419) 0x25044f MOVQ	$0,(%RDX,%R8,8)

  (419) 0x250457 MOV	0x8(%R12,%R8,8),%R9

  (419) 0x25045c CMP	%R9,%RDI

  (419) 0x25045f JGE	250440

  (419) 0x250461 MOV	0x20(%RBP),%R11

  (419) 0x250465 MOV	(%RCX,%R8,8),%R10

  (419) 0x250469 VXORPD	%XMM0,%XMM0,%XMM0

  (419) 0x25046d MOV	(%R11),%R11

  (419) 0x250470 JMP	250488

0x250472 NOPW	%CS:(%RAX,%RAX,1)

    (420) 0x250480 INC	%RDI

    (420) 0x250483 CMP	%RDI,%R9

    (420) 0x250486 JE	250440

    (420) 0x250488 MOV	(%RSI,%RDI,8),%RBX

    (420) 0x25048c CMP	%R10,(%RCX,%RBX,8)

    (420) 0x250490 JNE	250480

    (420) 0x250492 VMOVSD	(%R11,%RDI,8),%XMM1

    (420) 0x250498 VANDPD	-0x4116a(%RIP){1to2},%XMM1,%XMM1

    (420) 0x2504a2 VADDSD	%XMM0,%XMM1,%XMM0

    (420) 0x2504a6 VMOVSD	%XMM0,(%RDX,%R8,8)

    (420) 0x2504ac JMP	250480

(375) 0x2504ae MOV	%RAX,%RSI

(375) 0x2504b1 JMP	2504cf

0x2504b3 NOPW	%CS:(%RAX,%RAX,1)

  (396) 0x2504c0 INC	%RSI

  (396) 0x2504c3 MOV	%R8,%RCX

  (396) 0x2504c6 CMP	%R14,%RSI

  (396) 0x2504c9 JE	250790

  (396) 0x2504cf MOVQ	$0,(%RDX,%RSI,8)

  (396) 0x2504d7 MOV	0x8(%R12,%RSI,8),%R8

  (396) 0x2504dc CMP	%R8,%RCX

  (396) 0x2504df JGE	2504c0

  (396) 0x2504e1 MOV	0x20(%RBP),%R11

  (396) 0x2504e5 MOV	(%R9,%RSI,8),%R10

  (396) 0x2504e9 VXORPD	%XMM0,%XMM0,%XMM0

  (396) 0x2504ed MOV	(%R11),%R11

  (396) 0x2504f0 JMP	250508

0x2504f2 NOPW	%CS:(%RAX,%RAX,1)

    (397) 0x250500 INC	%RCX

    (397) 0x250503 CMP	%RCX,%R8

    (397) 0x250506 JE	2504c0

    (397) 0x250508 MOV	(%RDI,%RCX,8),%RBX

    (397) 0x25050c CMP	%RAX,%RBX

    (397) 0x25050f JL	25051b

    (397) 0x250511 CMP	%RSI,%RBX

    (397) 0x250514 JE	25051b

    (397) 0x250516 CMP	%R14,%RBX

    (397) 0x250519 JL	250500

    (397) 0x25051b CMP	%R10,(%R9,%RBX,8)

    (397) 0x25051f JNE	250500

    (397) 0x250521 VMOVSD	(%R11,%RCX,8),%XMM1

    (397) 0x250527 VANDPD	-0x411f9(%RIP){1to2},%XMM1,%XMM1

    (397) 0x250531 VADDSD	%XMM0,%XMM1,%XMM0

    (397) 0x250535 VMOVSD	%XMM0,(%RDX,%RSI,8)

    (397) 0x25053a JMP	250500

(375) 0x25053c LEA	0xc0(%R8),%RCX

(375) 0x250543 XOR	%R11D,%R11D

(375) 0x250546 MOV	%RAX,%RBX

(375) 0x250549 JMP	25055f

0x25054b NOPL	(%RAX,%RAX,1)

  (408) 0x250550 INC	%RBX

  (408) 0x250553 INC	%R11

  (408) 0x250556 CMP	%R14,%RBX

  (408) 0x250559 JE	250790

  (408) 0x25055f MOVQ	$0,(%RDX,%RBX,8)

  (408) 0x250567 MOV	%RDI,%R10

  (408) 0x25056a MOV	0x8(%R12,%RBX,8),%RDI

  (408) 0x25056f MOV	%RDI,%RSI

  (408) 0x250572 SUB	%R10,%RSI

  (408) 0x250575 JLE	250550

  (408) 0x250577 VXORPD	%XMM0,%XMM0,%XMM0

  (408) 0x25057b CMP	$0x4,%RSI

  (408) 0x25057f JB	2506f0

  (408) 0x250585 MOV	-0x60(%RBP),%R9

  (408) 0x250589 LEA	(%R8,%RDI,8),%R12

  (408) 0x25058d LEA	(%R9,%R11,8),%R15

  (408) 0x250591 LEA	(%R8,%R10,8),%R9

  (408) 0x250595 ADD	%RDX,%R15

  (408) 0x250598 CMP	%R12,%R15

  (408) 0x25059b JAE	2505b6

  (408) 0x25059d MOV	-0x58(%RBP),%R15

  (408) 0x2505a1 LEA	(%R15,%R11,8),%R15

  (408) 0x2505a5 ADD	%RDX,%R15

  (408) 0x2505a8 CMP	%R15,%R9

  (408) 0x2505ab JAE	2505b6

  (408) 0x2505ad MOV	-0x38(%RBP),%R12

  (408) 0x2505b1 JMP	2506f0

  (408) 0x2505b6 CMP	$0x20,%RSI

  (408) 0x2505ba JAE	2505c4

  (408) 0x2505bc XOR	%R15D,%R15D

  (408) 0x2505bf JMP	250684

  (408) 0x2505c4 LEA	(%RCX,%R10,8),%R12

  (408) 0x2505c8 MOV	%RSI,%R15

  (408) 0x2505cb AND	$-0x20,%R15

  (408) 0x2505cf VXORPD	%XMM0,%XMM0,%XMM0

  (408) 0x2505d3 VXORPD	%XMM1,%XMM1,%XMM1

  (408) 0x2505d7 VXORPD	%XMM2,%XMM2,%XMM2

  (408) 0x2505db VXORPD	%XMM3,%XMM3,%XMM3

  (408) 0x2505df XOR	%R13D,%R13D

  (408) 0x2505e2 NOPW	%CS:(%RAX,%RAX,1)

    (410) 0x2505f0 VBROADCASTSD	-0x412c2(%RIP),%ZMM4

    (410) 0x2505fa VANDPD	-0xc0(%R12,%R13,8),%ZMM4,%ZMM5

    (410) 0x250602 VANDPD	-0x80(%R12,%R13,8),%ZMM4,%ZMM7

    (410) 0x25060a VANDPD	-0x40(%R12,%R13,8),%ZMM4,%ZMM6

    (410) 0x250612 VANDPD	(%R12,%R13,8),%ZMM4,%ZMM4

    (410) 0x250619 ADD	$0x20,%R13

    (410) 0x25061d VADDPD	%ZMM0,%ZMM5,%ZMM0

    (410) 0x250623 VADDPD	%ZMM1,%ZMM7,%ZMM1

    (410) 0x250629 VADDPD	%ZMM2,%ZMM6,%ZMM2

    (410) 0x25062f VADDPD	%ZMM3,%ZMM4,%ZMM3

    (410) 0x250635 CMP	%R13,%R15

    (410) 0x250638 JNE	2505f0

  (408) 0x25063a VADDPD	%ZMM0,%ZMM1,%ZMM0

  (408) 0x250640 MOV	-0x38(%RBP),%R12

  (408) 0x250644 VADDPD	%ZMM0,%ZMM2,%ZMM0

  (408) 0x25064a VADDPD	%ZMM0,%ZMM3,%ZMM0

  (408) 0x250650 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

  (408) 0x250657 VADDPD	%ZMM1,%ZMM0,%ZMM0

  (408) 0x25065d VEXTRACTF128	$0x1,%YMM0,%XMM1

  (408) 0x250663 VADDPD	%XMM1,%XMM0,%XMM0

  (408) 0x250667 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (408) 0x25066c VADDSD	%XMM1,%XMM0,%XMM0

  (408) 0x250670 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (408) 0x250675 CMP	%R15,%RSI

  (408) 0x250678 JE	250550

  (408) 0x25067e TEST	$0x1c,%SIL

  (408) 0x250682 JE	2506e3

  (408) 0x250684 MOV	%RSI,%R12

  (408) 0x250687 AND	$-0x4,%R12

  (408) 0x25068b VMOVQ	%XMM0,%XMM0

  (408) 0x25068f ADD	%R12,%R10

  (408) 0x250692 NOPW	%CS:(%RAX,%RAX,1)

    (411) 0x2506a0 VMOVUPD	(%R9,%R15,8),%YMM1

    (411) 0x2506a6 ADD	$0x4,%R15

    (411) 0x2506aa VANDPD	-0x4137c(%RIP){1to4},%YMM1,%YMM1

    (411) 0x2506b4 VADDPD	%YMM0,%YMM1,%YMM0

    (411) 0x2506b8 CMP	%R15,%R12

    (411) 0x2506bb JNE	2506a0

  (408) 0x2506bd VEXTRACTF128	$0x1,%YMM0,%XMM1

  (408) 0x2506c3 VADDPD	%XMM1,%XMM0,%XMM0

  (408) 0x2506c7 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (408) 0x2506cc VADDSD	%XMM1,%XMM0,%XMM0

  (408) 0x2506d0 VMOVSD	%XMM0,(%RDX,%RBX,8)

  (408) 0x2506d5 CMP	%R12,%RSI

  (408) 0x2506d8 MOV	-0x38(%RBP),%R12

  (408) 0x2506dc JNE	2506f0

  (408) 0x2506de JMP	250550

  (408) 0x2506e3 ADD	%R15,%R10

  (408) 0x2506e6 NOPW	%CS:(%RAX,%RAX,1)

    (409) 0x2506f0 VMOVSD	(%R8,%R10,8),%XMM1

    (409) 0x2506f6 INC	%R10

    (409) 0x2506f9 VANDPD	-0x413cb(%RIP){1to2},%XMM1,%XMM1

    (409) 0x250703 VADDSD	%XMM0,%XMM1,%XMM0

    (409) 0x250707 VMOVSD	%XMM0,(%RDX,%RBX,8)

    (409) 0x25070c CMP	%R10,%RDI

    (409) 0x25070f JNE	2506f0

  (408) 0x250711 JMP	250550

(375) 0x250716 MOV	%RAX,%RSI

(375) 0x250719 JMP	25072b

0x25071b NOPL	(%RAX,%RAX,1)

  (389) 0x250720 INC	%RSI

  (389) 0x250723 MOV	%R8,%RCX

  (389) 0x250726 CMP	%R14,%RSI

  (389) 0x250729 JE	250790

  (389) 0x25072b MOVQ	$0,(%RDX,%RSI,8)

  (389) 0x250733 MOV	0x8(%R12,%RSI,8),%R8

  (389) 0x250738 CMP	%R8,%RCX

  (389) 0x25073b JGE	250720

  (389) 0x25073d MOV	0x20(%RBP),%R9

  (389) 0x250741 VXORPD	%XMM0,%XMM0,%XMM0

  (389) 0x250745 MOV	(%R9),%R9

  (389) 0x250748 JMP	250771

0x25074a NOPW	(%RAX,%RAX,1)

    (390) 0x250750 VMOVSD	(%R9,%RCX,8),%XMM1

    (390) 0x250756 VANDPD	-0x41428(%RIP){1to2},%XMM1,%XMM1

    (390) 0x250760 VADDSD	%XMM0,%XMM1,%XMM0

    (390) 0x250764 VMOVSD	%XMM0,(%RDX,%RSI,8)

    (390) 0x250769 INC	%RCX

    (390) 0x25076c CMP	%RCX,%R8

    (390) 0x25076f JE	250720

    (390) 0x250771 MOV	(%RDI,%RCX,8),%R10

    (390) 0x250775 CMP	%RAX,%R10

    (390) 0x250778 JL	250750

    (390) 0x25077a CMP	%RSI,%R10

    (390) 0x25077d JE	250750

    (390) 0x25077f CMP	%R14,%R10

    (390) 0x250782 JL	250769

    (390) 0x250784 JMP	250750

0x250786 NOPW	%CS:(%RAX,%RAX,1)

(375) 0x250790 CMP	%R14,%RAX

(375) 0x250793 JGE	24f0d0

(375) 0x250799 MOV	0x20(%RBP),%RCX

(375) 0x25079d MOV	0x18(%RBP),%RDX

(375) 0x2507a1 MOV	-0x70(%RBP),%RSI

(375) 0x2507a5 MOV	-0xa8(%RBP),%R15

(375) 0x2507ac MOV	-0xa0(%RBP),%R12

(375) 0x2507b3 MOV	%RAX,%RDI

(375) 0x2507b6 MOV	(%RCX),%RCX

(375) 0x2507b9 MOV	(%RDX),%RDX

(375) 0x2507bc MOV	(%RSI),%RSI

(375) 0x2507bf JMP	2507d8

0x2507c1 NOPW	%CS:(%RAX,%RAX,1)

  (377) 0x2507d0 INC	%RDI

  (377) 0x2507d3 CMP	%RDI,%R14

  (377) 0x2507d6 JE	250800

  (377) 0x2507d8 MOV	(%RDX,%RDI,8),%R8

  (377) 0x2507dc VUCOMISD	(%RCX,%R8,8),%XMM10

  (377) 0x2507e2 JBE	2507d0

  (377) 0x2507e4 VMOVSD	(%RSI,%RDI,8),%XMM0

  (377) 0x2507e9 VXORPD	-0x4146b(%RIP){1to2},%XMM0,%XMM0

  (377) 0x2507f3 VMOVLPD	%XMM0,(%RSI,%RDI,8)

  (377) 0x2507f8 JMP	2507d0

0x2507fa NOPW	(%RAX,%RAX,1)

(375) 0x250800 MOV	-0x70(%RBP),%RCX

(375) 0x250804 VMOVSD	%XMM8,-0x40(%RBP)

(375) 0x250809 MOV	(%RCX),%RCX

(375) 0x25080c NOPL	(%RAX)

  (376) 0x250810 VUCOMISD	(%RCX,%RAX,8),%XMM10

  (376) 0x250815 JE	250840

  (376) 0x250817 INC	%RAX

  (376) 0x25081a CMP	%RAX,%R14

  (376) 0x25081d JNE	250810

(375) 0x25081f MOV	-0x98(%RBP),%RBX

(375) 0x250826 VMOVSD	-0x40(%RBP),%XMM8

(375) 0x25082b CMP	%RBX,%R12

(375) 0x25082e JL	24f0ee

0x250834 JMP	250885

0x250836 NOPW	%CS:(%RAX,%RAX,1)

(375) 0x250840 MOV	$0xdd4,%ESI

(375) 0x250845 MOV	$0xc,%EDX

(375) 0x25084a LEA	-0x354cc(%RIP),%RDI

(375) 0x250851 XOR	%ECX,%ECX

(375) 0x250853 VZEROUPPER

(375) 0x250856 CALL	303e80 <hypre_error_handler>

(375) 0x25085b VMOVSD	-0x4154b(%RIP),%XMM12

(375) 0x250863 VMOVSD	-0x414eb(%RIP),%XMM11

(375) 0x25086b MOV	-0x88(%RBP),%RBX

(375) 0x250872 VXORPD	%XMM10,%XMM10,%XMM10

(375) 0x250877 VMOVSD	-0x40(%RBP),%XMM8

(375) 0x25087c CMP	%RBX,%R12

(375) 0x25087f JL	24f0ee

0x250885 MOV	-0x8c(%RBP),%ESI

0x25088b LEA	0xb6d4e(%RIP),%RDI

0x250892 VZEROUPPER

0x250895 CALL	305fb0 <@plt_start@+0xa0>

0x25089a ADD	$0xa8,%RSP

0x2508a1 POP	%RBX

0x2508a2 POP	%R12

0x2508a4 POP	%R13

0x2508a6 POP	%R14

0x2508a8 POP	%R15

0x2508aa POP	%RBP

0x2508ab RET

0x2508ac NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.97+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.03+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParCSRComputeL1NormsThre[...]	ams.c:3363	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1409	exec
○	hypre_PCGSetup	pcg.c:234	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.63 to 1.25 cycles (6.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 7.63 to 0.56 cycles (13.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3365

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	94
nb uops	61
loop length	545
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.63 cycles
front end	7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Dispatch	4.75
Overall L1	7.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.63 cycles. At this rate:

2% of peak load performance is reached (6.30 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.63 to 4.75 cycles (1.61x speedup).

ASM code

In the binary file, the address of the function is: 24efe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 25089a <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xd0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xb8571(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x90(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x8c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xb0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RBX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 250885 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x3fd32(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x3fda2(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 24f0ee <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x10e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 250885 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x8c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0xb6d4e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_2

Source file and lines	ams.c:3363-3540
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363-3409,3416-3451,3458-3540.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.63 to 1.25 cycles (6.10x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3363

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3365

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 48 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	94
nb uops	61
loop length	545
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.63 cycles
front end	7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.00	4.00	4.00	4.00	4.00	4.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.00	4.00	4.00	4.00	4.00	4.00	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.63
Dispatch	4.75
Overall L1	7.63

Vectorization ratios

INT

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	11%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.63 cycles. At this rate:

2% of peak load performance is reached (6.30 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.44 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 24efe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RCX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 25089a <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18ba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOVQ $0,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0xd0(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xb8571(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x90(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0xb0(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x88(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x8c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 305fa0 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x88(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xb0(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV %RBX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RBX,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 250885 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x3fd32(%RIP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD -0x3fda2(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 24f0ee <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x10e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 250885 <hypre_ParCSRComputeL1NormsThreads.omp_outlined+0x18a5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x8c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0xb6d4e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 305fb0 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRComputeL1NormsThreads.omp_outlined–	0.32	0.17
▼Loop 375 - ams.c:3365-3540 - exec–	0.00	0.00
○Loop 377 - ams.c:3532-3534 - exec	0.07	0.03
▼Loop 412 - ams.c:3382-3394 - exec–	0.02	0.01
○Loop 418 - ams.c:3389-3389 - exec	0.20	0.10
○Loop 416 - ams.c:3388-3389 - exec	0.03	0.02
○Loop 417 - ams.c:3389-3389 - exec	0.00	0.00
○Loop 415 - ams.c:3394-3394 - exec	0.00	0.00
○Loop 413 - ams.c:3393-3394 - exec	0.00	0.00
○Loop 414 - ams.c:3394-3394 - exec	0.00	0.00
○Loop 376 - ams.c:3536-3538 - exec	0.01	0.01
▼Loop 378 - ams.c:3458-3462 - exec–	0.00	0.00
○Loop 381 - ams.c:3462-3462 - exec	0.00	0.00
○Loop 379 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 380 - ams.c:3462-3462 - exec	0.00	0.00
▼Loop 421 - ams.c:3382-3409 - exec–	0.00	0.00
○Loop 423 - ams.c:3401-3403 - exec	0.00	0.00
○Loop 422 - ams.c:3407-3409 - exec	0.00	0.00
▼Loop 396 - ams.c:3403-3444 - exec–	0.00	0.00
○Loop 397 - ams.c:3439-3444 - exec	0.00	0.00
▼Loop 389 - ams.c:3388-3426 - exec–	0.00	0.00
○Loop 390 - ams.c:3422-3426 - exec	0.00	0.00
▼Loop 401 - ams.c:3470-3527 - exec–	0.00	0.00
○Loop 402 - ams.c:3493-3494 - exec	0.00	0.00
○Loop 405 - ams.c:3476-3487 - exec	0.00	0.00
○Loop 407 - ams.c:3501-3513 - exec	0.00	0.00
○Loop 403 - ams.c:3494-3494 - exec	0.00	0.00
○Loop 404 - ams.c:3493-3494 - exec	0.00	0.00
○Loop 406 - ams.c:3519-3521 - exec	0.00	0.00
▼Loop 408 - ams.c:3382-3389 - exec–	0.00	0.00
○Loop 410 - ams.c:3389-3389 - exec	0.00	0.00
○Loop 409 - ams.c:3388-3389 - exec	0.00	0.00
○Loop 411 - ams.c:3389-3389 - exec	0.00	0.00
▼Loop 382 - ams.c:3458-3465 - exec–	0.00	0.00
○Loop 386 - ams.c:3461-3462 - exec	0.00	0.00
○Loop 385 - ams.c:3465-3465 - exec	0.00	0.00
○Loop 387 - ams.c:3462-3462 - exec	0.00	0.00
○Loop 383 - ams.c:3464-3465 - exec	0.00	0.00
○Loop 388 - ams.c:3462-3462 - exec	0.00	0.00
○Loop 384 - ams.c:3465-3465 - exec	0.00	0.00
▼Loop 398 - ams.c:3416-3451 - exec–	0.00	0.00
○Loop 400 - ams.c:3439-3444 - exec	0.00	0.00
○Loop 399 - ams.c:3449-3451 - exec	0.00	0.00
▼Loop 419 - ams.c:3382-3431 - exec–	0.00	0.00
○Loop 420 - ams.c:3401-3403 - exec	0.00	0.00
▼Loop 391 - ams.c:3416-3432 - exec–	0.00	0.00
○Loop 395 - ams.c:3422-3426 - exec	0.00	0.00
○Loop 394 - ams.c:3432-3432 - exec	0.00	0.00
○Loop 393 - ams.c:3432-3432 - exec	0.00	0.00
○Loop 392 - ams.c:3431-3432 - exec	0.00	0.00

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Cycles summary

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code