OV - exec - Loop 968

	Loop Id: 968	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.04%

0x26b560 MOV	-0x70(%RBP),%RDX

0x26b564 INC	%RDX

0x26b567 CMP	%RDX,-0xe0(%RBP)

0x26b56e JLE	26b7ea

0x26b574 MOV	%RDX,-0x70(%RBP)

0x26b578 MOV	-0xd8(%RBP),%RSI

0x26b57f MOV	-0x98(%RBP),%R8

0x26b586 MOV	(%RSI,%RDX,8),%RDI

0x26b58a MOV	(%R8,%RDI,8),%RDX

0x26b58e MOV	%RDI,%R13

0x26b591 NOT	%R13

0x26b594 MOV	%RDI,-0x30(%RBP)

0x26b598 CMP	%RDX,0x8(%R8,%RDI,8)

0x26b59d JLE	26b6f0

0x26b5a3 MOV	-0xc8(%RBP),%RSI

0x26b5aa MOV	(%RSI),%RSI

0x26b5ad MOV	%RSI,-0x88(%RBP)

0x26b5b4 MOV	-0xf0(%RBP),%RSI

0x26b5bb MOV	(%RSI),%RSI

0x26b5be MOV	%RSI,-0x48(%RBP)

0x26b5c2 MOV	-0x90(%RBP),%RSI

0x26b5c9 MOV	-0xd0(%RBP),%R8

0x26b5d0 MOV	(%RSI),%RDI

0x26b5d3 MOV	(%R8),%RSI

0x26b5d6 MOV	%RSI,-0xe8(%RBP)

0x26b5dd MOV	-0xf8(%RBP),%RSI

0x26b5e4 MOV	(%RSI),%RSI

0x26b5e7 MOV	%RSI,-0x40(%RBP)

0x26b5eb MOV	-0x80(%RBP),%RSI

0x26b5ef MOV	(%RSI),%R10

0x26b5f2 JMP	26b619

  (971) 0x26b600 MOV	-0x98(%RBP),%RSI

  (971) 0x26b607 MOV	-0x30(%RBP),%R8

  (971) 0x26b60b INC	%RDX

  (971) 0x26b60e CMP	%RDX,0x8(%RSI,%R8,8)

  (971) 0x26b613 JLE	26b6f0

  (971) 0x26b619 MOV	-0x110(%RBP),%RSI

  (971) 0x26b620 MOV	(%RBX),%R9

  (971) 0x26b623 MOV	-0x108(%RBP),%R8

  (971) 0x26b62a MOV	(%RSI,%RDX,8),%R11

  (971) 0x26b62e DEC	%R9

  (971) 0x26b631 CMP	%R9,(%R8,%R11,8)

  (971) 0x26b635 JNE	26b600

  (971) 0x26b637 MOV	-0x48(%RBP),%RSI

  (971) 0x26b63b MOV	0x8(%RSI,%R11,8),%R9

  (971) 0x26b640 TEST	%R9,%R9

  (971) 0x26b643 JLE	26b690

  (971) 0x26b645 MOV	-0x88(%RBP),%RSI

  (971) 0x26b64c MOV	(%RSI,%R11,8),%R8

  (971) 0x26b650 ADD	%R8,%R9

  (971) 0x26b653 JMP	26b668

    (973) 0x26b660 INC	%R8

    (973) 0x26b663 CMP	%R9,%R8

    (973) 0x26b666 JGE	26b690

    (973) 0x26b668 MOV	(%RBX),%R12

    (973) 0x26b66b MOV	-0x8(%RDI,%R12,8),%RSI

    (973) 0x26b670 MOV	(%RSI,%R8,8),%RSI

    (973) 0x26b674 CMP	%R13,(%R14,%RSI,8)

    (973) 0x26b678 JE	26b660

    (973) 0x26b67a MOV	(%RDI,%R12,8),%R12

    (973) 0x26b67e MOV	%RSI,(%R12,%RAX,8)

    (973) 0x26b682 INC	%RAX

    (973) 0x26b685 MOV	%R13,(%R14,%RSI,8)

    (973) 0x26b689 JMP	26b660

  (971) 0x26b690 MOV	-0x40(%RBP),%RSI

  (971) 0x26b694 MOV	0x8(%RSI,%R11,8),%R9

  (971) 0x26b699 TEST	%R9,%R9

  (971) 0x26b69c JLE	26b600

  (971) 0x26b6a2 MOV	-0xe8(%RBP),%RSI

  (971) 0x26b6a9 MOV	(%RSI,%R11,8),%R8

  (971) 0x26b6ad ADD	%R8,%R9

  (971) 0x26b6b0 JMP	26b6cc

    (972) 0x26b6c0 INC	%R8

    (972) 0x26b6c3 CMP	%R9,%R8

    (972) 0x26b6c6 JGE	26b600

    (972) 0x26b6cc MOV	(%RBX),%R11

    (972) 0x26b6cf MOV	-0x8(%R10,%R11,8),%RSI

    (972) 0x26b6d4 MOV	(%RSI,%R8,8),%RSI

    (972) 0x26b6d8 CMP	%R13,(%R15,%RSI,8)

    (972) 0x26b6dc JE	26b6c0

    (972) 0x26b6de MOV	(%R10,%R11,8),%R11

    (972) 0x26b6e2 MOV	%RSI,(%R11,%RCX,8)

    (972) 0x26b6e6 INC	%RCX

    (972) 0x26b6e9 MOV	%R13,(%R15,%RSI,8)

    (972) 0x26b6ed JMP	26b6c0

0x26b6f0 MOV	-0x78(%RBP),%RSI

0x26b6f4 MOV	-0x30(%RBP),%RDI

0x26b6f8 MOV	(%RSI,%RDI,8),%RDX

0x26b6fc MOV	0x8(%RSI,%RDI,8),%RDI

0x26b701 CMP	%RDI,%RDX

0x26b704 JGE	26b560

0x26b70a MOV	-0x150(%RBP),%RSI

0x26b711 MOV	(%RSI),%RSI

0x26b714 MOV	%RSI,-0x40(%RBP)

0x26b718 MOV	-0x158(%RBP),%RSI

0x26b71f MOV	(%RSI),%RSI

0x26b722 MOV	%RSI,-0x48(%RBP)

0x26b726 MOV	-0x160(%RBP),%RSI

0x26b72d MOV	(%RSI),%R9

0x26b730 JMP	26b759

  (969) 0x26b740 MOV	-0x78(%RBP),%RSI

  (969) 0x26b744 MOV	-0x30(%RBP),%RDI

  (969) 0x26b748 MOV	0x8(%RSI,%RDI,8),%RDI

  (969) 0x26b74d INC	%RDX

  (969) 0x26b750 CMP	%RDI,%RDX

  (969) 0x26b753 JGE	26b560

  (969) 0x26b759 MOV	-0x100(%RBP),%RSI

  (969) 0x26b760 MOV	(%RBX),%R8

  (969) 0x26b763 MOV	-0x50(%RBP),%R10

  (969) 0x26b767 MOV	(%RSI,%RDX,8),%RSI

  (969) 0x26b76b DEC	%R8

  (969) 0x26b76e CMP	%R8,(%R10,%RSI,8)

  (969) 0x26b772 JNE	26b74d

  (969) 0x26b774 MOV	-0x48(%RBP),%R8

  (969) 0x26b778 MOV	0x8(%R8,%RSI,8),%R10

  (969) 0x26b77d TEST	%R10,%R10

  (969) 0x26b780 JLE	26b74d

  (969) 0x26b782 MOV	-0x40(%RBP),%RDI

  (969) 0x26b786 MOV	-0x80(%RBP),%R11

  (969) 0x26b78a MOV	-0x90(%RBP),%R8

  (969) 0x26b791 MOV	(%RDI,%RSI,8),%RDI

  (969) 0x26b795 MOV	(%R11),%R11

  (969) 0x26b798 MOV	(%R8),%R8

  (969) 0x26b79b ADD	%RDI,%R10

  (969) 0x26b79e JMP	26b7a8

    (970) 0x26b7a0 INC	%RDI

    (970) 0x26b7a3 CMP	%R10,%RDI

    (970) 0x26b7a6 JGE	26b740

    (970) 0x26b7a8 MOV	(%RBX),%R12

    (970) 0x26b7ab MOV	(%R9,%R12,8),%RSI

    (970) 0x26b7af MOV	(%RSI,%RDI,8),%RSI

    (970) 0x26b7b3 TEST	%RSI,%RSI

    (970) 0x26b7b6 JS	26b7d0

    (970) 0x26b7b8 CMP	%R13,(%R15,%RSI,8)

    (970) 0x26b7bc JE	26b7a0

    (970) 0x26b7be MOV	(%R11,%R12,8),%R12

    (970) 0x26b7c2 MOV	%RSI,(%R12,%RCX,8)

    (970) 0x26b7c6 INC	%RCX

    (970) 0x26b7c9 MOV	%R13,(%R15,%RSI,8)

    (970) 0x26b7cd JMP	26b7a0

    (970) 0x26b7d0 NOT	%RSI

    (970) 0x26b7d3 CMP	%R13,(%R14,%RSI,8)

    (970) 0x26b7d7 JE	26b7a0

    (970) 0x26b7d9 MOV	(%R8,%R12,8),%R12

    (970) 0x26b7dd MOV	%RSI,(%R12,%RAX,8)

    (970) 0x26b7e1 INC	%RAX

    (970) 0x26b7e4 MOV	%R13,(%R14,%RSI,8)

    (970) 0x26b7e8 JMP	26b7a0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►95.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.27+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.61
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	9.25
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.16
Front-end cycles	5.75
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	9.25
P7 cycles	9.25
P8 cycles	9.25
P9 cycles	9.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	29.00
Nb stores	8.00
Nb stack references	19.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.61
Bottlenecks	P6, P7, P8, P9,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	9.25
CQA cycles if FP arith vectorized	9.25
CQA cycles if fully vectorized	1.16
Front-end cycles	5.75
P0 cycles	1.67
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	1.67
P5 cycles	1.67
P6 cycles	9.25
P7 cycles	9.25
P8 cycles	9.25
P9 cycles	9.25
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	46.00
Nb uops	46.00
Nb loads	29.00
Nb stores	8.00
Nb stack references	19.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1099,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 77 paths individually, rerun with max-paths=77
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 77 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 1.16 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 9.25 to 5.75 cycles (1.61x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	46
nb uops	46
loop length	214
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	9.25
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

9% of peak load performance is reached (25.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 26b574

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RDX,-0xe0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 26b7ea <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0xaba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x98(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RDI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RDX,0x8(%R8,%RDI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 26b6f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x9c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x90(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 26b619 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x8e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI,%RDI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RSI,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 26b560 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x830>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x158(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x160(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 26b759 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 77 paths individually, rerun with max-paths=77
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 1.16 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 9.25 to 5.75 cycles (1.61x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	46
nb uops	46
loop length	214
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.75 cycles
front end	5.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	1.67	1.67	1.67	1.67	1.67	1.67	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.67	1.67	1.67	1.67	1.67	1.67	9.25	9.25	9.25	9.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.75
Dispatch	9.25
Overall L1	9.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

9% of peak load performance is reached (25.08 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.92 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 26b574

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x70(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %RDX,-0xe0(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 26b7ea <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0xaba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x98(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI,%RDX,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8,%RDI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOT %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RDX,0x8(%R8,%RDI,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 26b6f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x9c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf0(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x90(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xd0(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0xe8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0xf8(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 26b619 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x8e9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x30(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI,%RDI,8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RSI,%RDI,8),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
JGE 26b560 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x830>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x150(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x158(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x160(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
JMP 26b759 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code