OV - exec - Loop 2596

	Loop Id: 2596	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.03%

0x2b5f00 MOV	%R14,%R15

0x2b5f03 MOV	%R13,%R12

0x2b5f06 CMP	%R9,-0x98(%RBP)

0x2b5f0d JLE	2b630d

0x2b5f13 MOV	-0x100(%RBP),%RAX

0x2b5f1a MOV	%R9,%RDX

0x2b5f1d CMPQ	$0,(%RAX)

0x2b5f21 JE	2b5f4f

0x2b5f23 MOV	-0xf8(%RBP),%RAX

0x2b5f2a MOV	%R12,(%RDI,%RDX,8)

0x2b5f2e MOV	-0xe8(%RBP),%RCX

0x2b5f35 LEA	0x1(%R12),%R13

0x2b5f3a VMOVSD	(%RAX),%XMM0

0x2b5f3e MOV	-0xf0(%RBP),%RAX

0x2b5f45 VMOVSD	%XMM0,(%RAX,%R12,8)

0x2b5f4b MOV	%RDX,(%RCX,%R12,8)

0x2b5f4f MOV	-0x108(%RBP),%RAX

0x2b5f56 CMPQ	$0,(%RAX)

0x2b5f5a JE	2b6120

0x2b5f60 MOV	-0xb0(%RBP),%RCX

0x2b5f67 LEA	0x1(%RDX),%R9

0x2b5f6b MOV	(%RCX,%RDX,8),%RAX

0x2b5f6f CMP	%RAX,0x8(%RCX,%RDX,8)

0x2b5f74 JLE	2b6124

0x2b5f7a MOV	%R9,-0x50(%RBP)

0x2b5f7e MOV	%R15,%R14

0x2b5f81 MOV	-0xb8(%RBP),%RCX

0x2b5f88 MOV	(%RCX),%RCX

0x2b5f8b MOV	%RCX,-0x40(%RBP)

0x2b5f8f MOV	-0xc0(%RBP),%RCX

0x2b5f96 MOV	(%RCX),%RCX

0x2b5f99 MOV	%RCX,-0x48(%RBP)

0x2b5f9d MOV	%RDX,-0x38(%RBP)

0x2b5fa1 JMP	2b5fc9

  (2600) 0x2b5fb0 MOV	-0xb0(%RBP),%RCX

  (2600) 0x2b5fb7 MOV	-0x38(%RBP),%RDX

  (2600) 0x2b5fbb INC	%RAX

  (2600) 0x2b5fbe CMP	%RAX,0x8(%RCX,%RDX,8)

  (2600) 0x2b5fc3 JLE	2b6140

  (2600) 0x2b5fc9 MOV	-0x138(%RBP),%RCX

  (2600) 0x2b5fd0 MOV	-0x130(%RBP),%RSI

  (2600) 0x2b5fd7 MOV	-0x68(%RBP),%RDX

  (2600) 0x2b5fdb MOV	(%RCX,%RAX,8),%R9

  (2600) 0x2b5fdf VMOVSD	(%RSI,%RAX,8),%XMM0

  (2600) 0x2b5fe4 MOV	(%RDX,%R9,8),%R10

  (2600) 0x2b5fe8 MOV	0x8(%RDX,%R9,8),%RCX

  (2600) 0x2b5fed CMP	%RCX,%R10

  (2600) 0x2b5ff0 JGE	2b607d

  (2600) 0x2b5ff6 MOV	-0xa0(%RBP),%R11

  (2600) 0x2b5ffd MOV	-0x110(%RBP),%RDX

  (2600) 0x2b6004 MOV	-0xa8(%RBP),%R8

  (2600) 0x2b600b MOV	(%RDX),%RSI

  (2600) 0x2b600e MOV	(%R11),%R11

  (2600) 0x2b6011 MOV	(%R8),%RDX

  (2600) 0x2b6014 MOV	%RDX,-0x30(%RBP)

  (2600) 0x2b6018 JMP	2b603a

    (2602) 0x2b6020 VMOVSD	(%RSI,%R10,8),%XMM1

    (2602) 0x2b6026 VFMADD213SD	(%R11,%R8,8),%XMM0,%XMM1

    (2602) 0x2b602c VMOVSD	%XMM1,(%R11,%R8,8)

    (2602) 0x2b6032 INC	%R10

    (2602) 0x2b6035 CMP	%RCX,%R10

    (2602) 0x2b6038 JGE	2b607d

    (2602) 0x2b603a MOV	-0x40(%RBP),%RDX

    (2602) 0x2b603e MOV	(%RDX,%R10,8),%RDX

    (2602) 0x2b6042 ADD	(%RBX),%RDX

    (2602) 0x2b6045 MOV	(%RDI,%RDX,8),%R8

    (2602) 0x2b6049 CMP	%R15,%R8

    (2602) 0x2b604c JGE	2b6020

    (2602) 0x2b604e MOV	%R14,(%RDI,%RDX,8)

    (2602) 0x2b6052 MOV	-0x30(%RBP),%RCX

    (2602) 0x2b6056 VMULSD	(%RSI,%R10,8),%XMM0,%XMM1

    (2602) 0x2b605c VMOVSD	%XMM1,(%R11,%R14,8)

    (2602) 0x2b6062 SUB	(%RBX),%RDX

    (2602) 0x2b6065 MOV	%RDX,(%RCX,%R14,8)

    (2602) 0x2b6069 MOV	-0x68(%RBP),%RDX

    (2602) 0x2b606d INC	%R14

    (2602) 0x2b6070 MOV	0x8(%RDX,%R9,8),%RCX

    (2602) 0x2b6075 INC	%R10

    (2602) 0x2b6078 CMP	%RCX,%R10

    (2602) 0x2b607b JL	2b603a

  (2600) 0x2b607d MOV	-0x60(%RBP),%RCX

  (2600) 0x2b6081 MOV	(%RCX,%R9,8),%RSI

  (2600) 0x2b6085 MOV	0x8(%RCX,%R9,8),%R11

  (2600) 0x2b608a CMP	%R11,%RSI

  (2600) 0x2b608d JGE	2b5fb0

  (2600) 0x2b6093 MOV	-0x80(%RBP),%R10

  (2600) 0x2b6097 MOV	-0x118(%RBP),%RCX

  (2600) 0x2b609e MOV	-0x88(%RBP),%RDX

  (2600) 0x2b60a5 MOV	(%RCX),%R8

  (2600) 0x2b60a8 MOV	(%R10),%R10

  (2600) 0x2b60ab MOV	(%RDX),%RCX

  (2600) 0x2b60ae MOV	%RCX,-0x30(%RBP)

  (2600) 0x2b60b2 JMP	2b60de

    (2601) 0x2b60c0 VMOVSD	(%R8,%RSI,8),%XMM1

    (2601) 0x2b60c6 VFMADD213SD	(%R10,%RCX,8),%XMM0,%XMM1

    (2601) 0x2b60cc VMOVSD	%XMM1,(%R10,%RCX,8)

    (2601) 0x2b60d2 INC	%RSI

    (2601) 0x2b60d5 CMP	%R11,%RSI

    (2601) 0x2b60d8 JGE	2b5fb0

    (2601) 0x2b60de MOV	-0x48(%RBP),%RCX

    (2601) 0x2b60e2 MOV	(%RCX,%RSI,8),%RDX

    (2601) 0x2b60e6 MOV	(%RDI,%RDX,8),%RCX

    (2601) 0x2b60ea CMP	%R12,%RCX

    (2601) 0x2b60ed JGE	2b60c0

    (2601) 0x2b60ef MOV	%R13,(%RDI,%RDX,8)

    (2601) 0x2b60f3 MOV	-0x30(%RBP),%RCX

    (2601) 0x2b60f7 VMULSD	(%R8,%RSI,8),%XMM0,%XMM1

    (2601) 0x2b60fd VMOVSD	%XMM1,(%R10,%R13,8)

    (2601) 0x2b6103 MOV	%RDX,(%RCX,%R13,8)

    (2601) 0x2b6107 MOV	-0x60(%RBP),%RDX

    (2601) 0x2b610b INC	%R13

    (2601) 0x2b610e MOV	0x8(%RDX,%R9,8),%R11

    (2601) 0x2b6113 INC	%RSI

    (2601) 0x2b6116 CMP	%R11,%RSI

    (2601) 0x2b6119 JL	2b60de

  (2600) 0x2b611b JMP	2b5fb0

0x2b6120 LEA	0x1(%RDX),%R9

0x2b6124 MOV	%R15,%R14

0x2b6127 MOV	-0x58(%RBP),%RAX

0x2b612b MOV	(%RAX,%RDX,8),%R8

0x2b612f CMP	(%RAX,%R9,8),%R8

0x2b6133 JGE	2b5f00

0x2b6139 JMP	2b6156

0x2b6140 MOV	-0x50(%RBP),%R9

0x2b6144 MOV	-0x58(%RBP),%RAX

0x2b6148 MOV	(%RAX,%RDX,8),%R8

0x2b614c CMP	%R8,(%RAX,%R9,8)

0x2b6150 JLE	2b5f00

0x2b6156 MOV	-0xc8(%RBP),%RAX

0x2b615d MOV	(%RAX),%RAX

0x2b6160 MOV	%RAX,-0x40(%RBP)

0x2b6164 MOV	-0xd0(%RBP),%RAX

0x2b616b MOV	(%RAX),%RAX

0x2b616e MOV	%RAX,-0x70(%RBP)

0x2b6172 MOV	-0xd8(%RBP),%RAX

0x2b6179 MOV	(%RAX),%RAX

0x2b617c MOV	%RAX,-0x48(%RBP)

0x2b6180 MOV	-0xe0(%RBP),%RAX

0x2b6187 MOV	(%RAX),%RAX

0x2b618a MOV	%RAX,-0x30(%RBP)

0x2b618e MOV	%R9,-0x50(%RBP)

0x2b6192 JMP	2b61b5

  (2597) 0x2b61a0 MOV	-0x50(%RBP),%R9

  (2597) 0x2b61a4 MOV	-0x58(%RBP),%RAX

  (2597) 0x2b61a8 INC	%R8

  (2597) 0x2b61ab CMP	%R8,(%RAX,%R9,8)

  (2597) 0x2b61af JLE	2b5f00

  (2597) 0x2b61b5 MOV	-0x90(%RBP),%RAX

  (2597) 0x2b61bc MOV	-0x140(%RBP),%RDX

  (2597) 0x2b61c3 MOV	-0x78(%RBP),%RCX

  (2597) 0x2b61c7 MOV	(%RAX,%R8,8),%R9

  (2597) 0x2b61cb VMOVSD	(%RDX,%R8,8),%XMM0

  (2597) 0x2b61d1 MOV	(%RCX,%R9,8),%RSI

  (2597) 0x2b61d5 MOV	0x8(%RCX,%R9,8),%RCX

  (2597) 0x2b61da CMP	%RCX,%RSI

  (2597) 0x2b61dd JGE	2b6255

  (2597) 0x2b61df MOV	-0x80(%RBP),%R10

  (2597) 0x2b61e3 MOV	-0x128(%RBP),%RAX

  (2597) 0x2b61ea MOV	-0x88(%RBP),%R11

  (2597) 0x2b61f1 MOV	(%RAX),%RDX

  (2597) 0x2b61f4 MOV	(%R10),%R10

  (2597) 0x2b61f7 MOV	(%R11),%RAX

  (2597) 0x2b61fa MOV	%RAX,-0x38(%RBP)

  (2597) 0x2b61fe JMP	2b6219

    (2599) 0x2b6200 VMOVSD	(%RDX,%RSI,8),%XMM1

    (2599) 0x2b6205 VFMADD213SD	(%R10,%R11,8),%XMM0,%XMM1

    (2599) 0x2b620b VMOVSD	%XMM1,(%R10,%R11,8)

    (2599) 0x2b6211 INC	%RSI

    (2599) 0x2b6214 CMP	%RCX,%RSI

    (2599) 0x2b6217 JGE	2b6255

    (2599) 0x2b6219 MOV	-0x40(%RBP),%RAX

    (2599) 0x2b621d MOV	(%RAX,%RSI,8),%RAX

    (2599) 0x2b6221 MOV	(%RDI,%RAX,8),%R11

    (2599) 0x2b6225 CMP	%R12,%R11

    (2599) 0x2b6228 JGE	2b6200

    (2599) 0x2b622a MOV	%R13,(%RDI,%RAX,8)

    (2599) 0x2b622e MOV	-0x38(%RBP),%RCX

    (2599) 0x2b6232 VMULSD	(%RDX,%RSI,8),%XMM0,%XMM1

    (2599) 0x2b6237 VMOVSD	%XMM1,(%R10,%R13,8)

    (2599) 0x2b623d MOV	%RAX,(%RCX,%R13,8)

    (2599) 0x2b6241 MOV	-0x78(%RBP),%RCX

    (2599) 0x2b6245 INC	%R13

    (2599) 0x2b6248 MOV	0x8(%RCX,%R9,8),%RCX

    (2599) 0x2b624d INC	%RSI

    (2599) 0x2b6250 CMP	%RCX,%RSI

    (2599) 0x2b6253 JL	2b6219

  (2597) 0x2b6255 MOV	-0x148(%RBP),%RAX

  (2597) 0x2b625c CMPQ	$0,(%RAX)

  (2597) 0x2b6260 JE	2b61a0

  (2597) 0x2b6266 MOV	-0x70(%RBP),%RAX

  (2597) 0x2b626a MOV	(%RAX,%R9,8),%R10

  (2597) 0x2b626e MOV	0x8(%RAX,%R9,8),%R11

  (2597) 0x2b6273 CMP	%R11,%R10

  (2597) 0x2b6276 JGE	2b61a0

  (2597) 0x2b627c MOV	-0xa0(%RBP),%RDX

  (2597) 0x2b6283 MOV	-0x120(%RBP),%RAX

  (2597) 0x2b628a MOV	-0xa8(%RBP),%RCX

  (2597) 0x2b6291 MOV	(%RAX),%RSI

  (2597) 0x2b6294 MOV	(%RDX),%RDX

  (2597) 0x2b6297 MOV	(%RCX),%RAX

  (2597) 0x2b629a MOV	%RAX,-0x38(%RBP)

  (2597) 0x2b629e JMP	2b62bd

    (2598) 0x2b62a0 VMOVSD	(%RSI,%R10,8),%XMM1

    (2598) 0x2b62a6 VFMADD213SD	(%RDX,%RAX,8),%XMM0,%XMM1

    (2598) 0x2b62ac VMOVSD	%XMM1,(%RDX,%RAX,8)

    (2598) 0x2b62b1 INC	%R10

    (2598) 0x2b62b4 CMP	%R11,%R10

    (2598) 0x2b62b7 JGE	2b61a0

    (2598) 0x2b62bd MOV	-0x30(%RBP),%RAX

    (2598) 0x2b62c1 MOV	-0x48(%RBP),%RCX

    (2598) 0x2b62c5 MOV	(%RAX,%R10,8),%RAX

    (2598) 0x2b62c9 MOV	(%RCX,%RAX,8),%RCX

    (2598) 0x2b62cd ADD	(%RBX),%RCX

    (2598) 0x2b62d0 MOV	(%RDI,%RCX,8),%RAX

    (2598) 0x2b62d4 CMP	%R15,%RAX

    (2598) 0x2b62d7 JGE	2b62a0

    (2598) 0x2b62d9 MOV	%R14,(%RDI,%RCX,8)

    (2598) 0x2b62dd MOV	-0x38(%RBP),%RAX

    (2598) 0x2b62e1 VMULSD	(%RSI,%R10,8),%XMM0,%XMM1

    (2598) 0x2b62e7 VMOVSD	%XMM1,(%RDX,%R14,8)

    (2598) 0x2b62ed SUB	(%RBX),%RCX

    (2598) 0x2b62f0 MOV	%RCX,(%RAX,%R14,8)

    (2598) 0x2b62f4 MOV	-0x70(%RBP),%RCX

    (2598) 0x2b62f8 INC	%R14

    (2598) 0x2b62fb MOV	0x8(%RCX,%R9,8),%R11

    (2598) 0x2b6300 INC	%R10

    (2598) 0x2b6303 CMP	%R11,%R10

    (2598) 0x2b6306 JL	2b62bd

  (2597) 0x2b6308 JMP	2b61a0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	5.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:917-917,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.75
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	10.75
CQA cycles if fully vectorized	1.34
Front-end cycles	7.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	10.75
P7 cycles	10.75
P8 cycles	10.75
P9 cycles	10.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	31.00
Nb stores	12.00
Nb stack references	20.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	5.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:917-917,par_csr_matop.c:937-937
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.75
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	10.75
CQA cycles if fully vectorized	1.34
Front-end cycles	7.50
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	10.75
P7 cycles	10.75
P8 cycles	10.75
P9 cycles	10.75
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	60.00
Nb loads	31.00
Nb stores	12.00
Nb stack references	20.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-888,917,937.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 286 paths individually, rerun with max-paths=286
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 286 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.75 to 2.00 cycles (5.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.75 to 1.34 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.75 to 7.50 cycles (1.43x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 248 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	60
nb uops	60
loop length	274
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	10.75	10.75	10.75	10.75	0.00	0.00	0.00	0.00	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	10.75	10.75	10.75	10.75	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	10.75
Overall L1	10.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.75 cycles. At this rate:

9% of peak load performance is reached (23.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2b5f13

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,-0x98(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JLE 2b630d <hypre_ParMatmul.omp_outlined.7+0x6dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2b5f4f <hypre_ParMatmul.omp_outlined.7+0x31f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R12,(%RDI,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xe8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%R12),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0xf0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSD %XMM0,(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x108(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2b6120 <hypre_ParMatmul.omp_outlined.7+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%RCX,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,0x8(%RCX,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JLE 2b6124 <hypre_ParMatmul.omp_outlined.7+0x4f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 2b5fc9 <hypre_ParMatmul.omp_outlined.7+0x399>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP (%RAX,%R9,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 2b5f00 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2b6156 <hypre_ParMatmul.omp_outlined.7+0x526>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R8,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JLE 2b5f00 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 2b61b5 <hypre_ParMatmul.omp_outlined.7+0x585>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 286 paths individually, rerun with max-paths=286
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.75 to 2.00 cycles (5.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 10.75 to 7.50 cycles (1.43x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 248 bytes. The binary loop is storing 96 bytes.

General properties

nb instructions	60
nb uops	60
loop length	274
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.50 cycles
front end	7.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	10.75	10.75	10.75	10.75	0.00	0.00	0.00	0.00	0.50	0.50
cycles	3.00	3.00	3.00	3.00	3.00	3.00	10.75	10.75	10.75	10.75	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.50
Dispatch	10.75
Overall L1	10.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.75 cycles. At this rate:

9% of peak load performance is reached (23.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.93 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2b5f13

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
MOV %R14,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R13,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,-0x98(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JLE 2b630d <hypre_ParMatmul.omp_outlined.7+0x6dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x100(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2b5f4f <hypre_ParMatmul.omp_outlined.7+0x31f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xf8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %R12,(%RDI,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xe8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%R12),%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
VMOVSD (%RAX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV -0xf0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVSD %XMM0,(%RAX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDX,(%RCX,%R12,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0x108(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JE 2b6120 <hypre_ParMatmul.omp_outlined.7+0x4f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xb0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV (%RCX,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %RAX,0x8(%RCX,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JLE 2b6124 <hypre_ParMatmul.omp_outlined.7+0x4f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0xb8(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xc0(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RCX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 2b5fc9 <hypre_ParMatmul.omp_outlined.7+0x399>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP (%RAX,%R9,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
JGE 2b5f00 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2b6156 <hypre_ParMatmul.omp_outlined.7+0x526>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX,%RDX,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
CMP %R8,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	1	0.25	N/A
JLE 2b5f00 <hypre_ParMatmul.omp_outlined.7+0x2d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xd0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xd8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
JMP 2b61b5 <hypre_ParMatmul.omp_outlined.7+0x585>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code