OV - exec - Loop 2570

	Loop Id: 2570	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.03%

0x2b3690 MOV	-0x98(%RBP),%RAX

0x2b3697 MOV	-0x48(%RBP),%RCX

0x2b369b MOV	-0x90(%RBP),%RDX

0x2b36a2 MOV	%RBX,(%RAX,%RCX,8)

0x2b36a6 MOV	%R14,(%RDX,%RCX,8)

0x2b36aa MOV	%R13,%R14

0x2b36ad MOV	%R12,%RBX

0x2b36b0 MOV	%R9,%RDX

0x2b36b3 CMP	%R9,-0x30(%RBP)

0x2b36b7 JE	2b38ef

0x2b36bd MOV	0x18(%RBP),%RAX

0x2b36c1 CMPQ	$0,(%RAX)

0x2b36c5 JE	2b36cf

0x2b36c7 LEA	0x1(%RBX),%R12

0x2b36cb MOV	%RBX,(%RDI,%RDX,8)

0x2b36cf MOV	0x20(%RBP),%RAX

0x2b36d3 MOV	-0xa0(%RBP),%R11

0x2b36da MOV	%RDX,-0x48(%RBP)

0x2b36de CMPQ	$0,(%RAX)

0x2b36e2 JE	2b37c0

0x2b36e8 MOV	(%R11,%RDX,8),%RAX

0x2b36ec LEA	0x1(%RDX),%R9

0x2b36f0 CMP	%RAX,0x8(%R11,%RDX,8)

0x2b36f5 JLE	2b37c4

0x2b36fb MOV	0x40(%RBP),%RCX

0x2b36ff MOV	0x50(%RBP),%RDX

0x2b3703 MOV	%R9,-0x38(%RBP)

0x2b3707 MOV	%R14,%R13

0x2b370a MOV	(%RCX),%RCX

0x2b370d MOV	(%RDX),%RSI

0x2b3710 JMP	2b3732

  (2574) 0x2b3720 MOV	-0x48(%RBP),%RDX

  (2574) 0x2b3724 INC	%RAX

  (2574) 0x2b3727 CMP	%RAX,0x8(%R11,%RDX,8)

  (2574) 0x2b372c JLE	2b37e0

  (2574) 0x2b3732 MOV	-0xa8(%RBP),%RDX

  (2574) 0x2b3739 MOV	-0x60(%RBP),%R10

  (2574) 0x2b373d MOV	(%RDX,%RAX,8),%R8

  (2574) 0x2b3741 MOV	(%R10,%R8,8),%R9

  (2574) 0x2b3745 MOV	0x8(%R10,%R8,8),%RDX

  (2574) 0x2b374a JMP	2b3753

    (2576) 0x2b3750 INC	%R9

    (2576) 0x2b3753 CMP	%RDX,%R9

    (2576) 0x2b3756 JGE	2b3780

    (2576) 0x2b3758 MOV	(%RCX,%R9,8),%R10

    (2576) 0x2b375c ADD	(%R15),%R10

    (2576) 0x2b375f CMP	%R14,(%RDI,%R10,8)

    (2576) 0x2b3763 JGE	2b3750

    (2576) 0x2b3765 MOV	-0x60(%RBP),%RDX

    (2576) 0x2b3769 MOV	%R13,(%RDI,%R10,8)

    (2576) 0x2b376d INC	%R13

    (2576) 0x2b3770 MOV	0x8(%RDX,%R8,8),%RDX

    (2576) 0x2b3775 JMP	2b3750

  (2574) 0x2b3780 MOV	-0x58(%RBP),%RDX

  (2574) 0x2b3784 MOV	(%RDX,%R8,8),%R9

  (2574) 0x2b3788 MOV	0x8(%RDX,%R8,8),%RDX

  (2574) 0x2b378d JMP	2b3793

    (2575) 0x2b3790 INC	%R9

    (2575) 0x2b3793 CMP	%RDX,%R9

    (2575) 0x2b3796 JGE	2b3720

    (2575) 0x2b3798 MOV	(%RSI,%R9,8),%R10

    (2575) 0x2b379c CMP	%RBX,(%RDI,%R10,8)

    (2575) 0x2b37a0 JGE	2b3790

    (2575) 0x2b37a2 MOV	-0x58(%RBP),%RDX

    (2575) 0x2b37a6 MOV	%R12,(%RDI,%R10,8)

    (2575) 0x2b37aa INC	%R12

    (2575) 0x2b37ad MOV	0x8(%RDX,%R8,8),%RDX

    (2575) 0x2b37b2 JMP	2b3790

0x2b37c0 LEA	0x1(%RDX),%R9

0x2b37c4 MOV	%R14,%R13

0x2b37c7 MOV	-0x50(%RBP),%RAX

0x2b37cb MOV	(%RAX,%RDX,8),%RCX

0x2b37cf CMP	(%RAX,%R9,8),%RCX

0x2b37d3 JGE	2b3690

0x2b37d9 JMP	2b37f6

0x2b37e0 MOV	-0x38(%RBP),%R9

0x2b37e4 MOV	-0x50(%RBP),%RAX

0x2b37e8 MOV	(%RAX,%RDX,8),%RCX

0x2b37ec CMP	%RCX,(%RAX,%R9,8)

0x2b37f0 JLE	2b3690

0x2b37f6 MOV	0x88(%RBP),%RDX

0x2b37fd MOV	0x70(%RBP),%RAX

0x2b3801 MOV	0x90(%RBP),%RSI

0x2b3808 MOV	%R9,-0x38(%RBP)

0x2b380c MOV	(%RAX),%R8

0x2b380f MOV	0x80(%RBP),%RAX

0x2b3816 MOV	(%RDX),%RDX

0x2b3819 MOV	(%RAX),%RAX

0x2b381c MOV	%RDX,-0xc0(%RBP)

0x2b3823 MOV	(%RSI),%RDX

0x2b3826 MOV	%RDX,-0xb8(%RBP)

0x2b382d JMP	2b3845

  (2571) 0x2b3830 MOV	-0x50(%RBP),%RDX

  (2571) 0x2b3834 MOV	-0x38(%RBP),%R9

  (2571) 0x2b3838 INC	%RCX

  (2571) 0x2b383b CMP	%RCX,(%RDX,%R9,8)

  (2571) 0x2b383f JLE	2b3690

  (2571) 0x2b3845 MOV	-0xb0(%RBP),%RDX

  (2571) 0x2b384c MOV	-0x68(%RBP),%RSI

  (2571) 0x2b3850 MOV	(%RDX,%RCX,8),%R10

  (2571) 0x2b3854 MOV	(%RSI,%R10,8),%R11

  (2571) 0x2b3858 MOV	0x8(%RSI,%R10,8),%RDX

  (2571) 0x2b385d JMP	2b3863

    (2573) 0x2b3860 INC	%R11

    (2573) 0x2b3863 CMP	%RDX,%R11

    (2573) 0x2b3866 JGE	2b3890

    (2573) 0x2b3868 MOV	(%R8,%R11,8),%R9

    (2573) 0x2b386c CMP	%RBX,(%RDI,%R9,8)

    (2573) 0x2b3870 JGE	2b3860

    (2573) 0x2b3872 MOV	-0x68(%RBP),%RDX

    (2573) 0x2b3876 MOV	%R12,(%RDI,%R9,8)

    (2573) 0x2b387a INC	%R12

    (2573) 0x2b387d MOV	0x8(%RDX,%R10,8),%RDX

    (2573) 0x2b3882 JMP	2b3860

  (2571) 0x2b3890 MOV	0x78(%RBP),%RDX

  (2571) 0x2b3894 CMPQ	$0,(%RDX)

  (2571) 0x2b3898 JE	2b3830

  (2571) 0x2b389a MOV	(%RAX,%R10,8),%R11

  (2571) 0x2b389e MOV	0x8(%RAX,%R10,8),%RDX

  (2571) 0x2b38a3 JMP	2b38b3

    (2572) 0x2b38b0 INC	%R11

    (2572) 0x2b38b3 CMP	%RDX,%R11

    (2572) 0x2b38b6 JGE	2b3830

    (2572) 0x2b38bc MOV	-0xb8(%RBP),%RSI

    (2572) 0x2b38c3 MOV	(%RSI,%R11,8),%R9

    (2572) 0x2b38c7 MOV	-0xc0(%RBP),%RSI

    (2572) 0x2b38ce MOV	(%RSI,%R9,8),%R9

    (2572) 0x2b38d2 ADD	(%R15),%R9

    (2572) 0x2b38d5 CMP	%R14,(%RDI,%R9,8)

    (2572) 0x2b38d9 JGE	2b38b0

    (2572) 0x2b38db MOV	%R13,(%RDI,%R9,8)

    (2572) 0x2b38df INC	%R13

    (2572) 0x2b38e2 MOV	0x8(%RAX,%R10,8),%RDX

    (2572) 0x2b38e7 JMP	2b38b0

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	1.19
Front-end cycles	6.88
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P6, P7, P8, P9,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	1.19
Front-end cycles	6.88
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	30.00
Nb stores	8.00
Nb stack references	17.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	240.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-146,170,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 50 paths individually, rerun with max-paths=50
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 50 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 1.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 6.88 cycles (1.38x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	55
nb uops	55
loop length	236
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

9% of peak load performance is reached (25.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2b36bd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,(%RAX,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,(%RDX,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,-0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b38ef <hypre_ParMatmul_RowSizes.omp_outlined+0x3cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b36cf <hypre_ParMatmul_RowSizes.omp_outlined+0x1af>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RBX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,(%RDI,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b37c0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R11,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %RAX,0x8(%R11,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 2b37c4 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 2b3732 <hypre_ParMatmul_RowSizes.omp_outlined+0x212>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP (%RAX,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 2b3690 <hypre_ParMatmul_RowSizes.omp_outlined+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 2b37f6 <hypre_ParMatmul_RowSizes.omp_outlined+0x2d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JLE 2b3690 <hypre_ParMatmul_RowSizes.omp_outlined+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x88(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x90(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2b3845 <hypre_ParMatmul_RowSizes.omp_outlined+0x325>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 50 paths individually, rerun with max-paths=50
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 1.19 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 9.50 to 6.88 cycles (1.38x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop
- use the 'restrict' C99 keyword

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 240 bytes. The binary loop is storing 64 bytes.

General properties

nb instructions	55
nb uops	55
loop length	236
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.88 cycles
front end	6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.00	3.00	3.00	3.00	3.00	3.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	3.00	3.00	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.88
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

9% of peak load performance is reached (25.26 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.74 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 2b36bd

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
MOV -0x98(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,(%RAX,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,(%RDX,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R13,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R9,-0x30(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b38ef <hypre_ParMatmul_RowSizes.omp_outlined+0x3cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b36cf <hypre_ParMatmul_RowSizes.omp_outlined+0x1af>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RBX),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RBX,(%RDI,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMPQ $0,(%RAX)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JE 2b37c0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R11,%RDX,8),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %RAX,0x8(%R11,%RDX,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JLE 2b37c4 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 2b3732 <hypre_ParMatmul_RowSizes.omp_outlined+0x212>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
LEA 0x1(%RDX),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R14,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP (%RAX,%R9,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (12.5%)
JGE 2b3690 <hypre_ParMatmul_RowSizes.omp_outlined+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
JMP 2b37f6 <hypre_ParMatmul_RowSizes.omp_outlined+0x2d6>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
MOV -0x38(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX,%RDX,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RCX,(%RAX,%R9,8)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
JLE 2b3690 <hypre_ParMatmul_RowSizes.omp_outlined+0x170>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x88(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x90(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R9,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2b3845 <hypre_ParMatmul_RowSizes.omp_outlined+0x325>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code