OV - exec - Loop 1028

	Loop Id: 1028	Module: exec	Source: par_multi_interp.c:1605-1660	Coverage: 0.10%

0x26dc80 MOV	-0xa0(%RBP),%R11

0x26dc87 INC	%R11

0x26dc8a CMP	%R11,-0xd8(%RBP)

0x26dc91 JLE	26e207

0x26dc97 MOV	-0x160(%RBP),%RCX

0x26dc9e MOV	(%RCX,%R11,8),%R8

0x26dca2 MOV	-0x98(%RBP),%RCX

0x26dca9 MOV	%R11,-0xa0(%RBP)

0x26dcb0 MOV	(%RCX,%R8,8),%RCX

0x26dcb4 MOV	0x8(%RDX,%R8,8),%RSI

0x26dcb9 MOV	(%RDX,%R8,8),%R9

0x26dcbd LEA	(%RSI,%RCX,1),%R10

0x26dcc1 SUB	%R9,%R10

0x26dcc4 CMP	%R10,%RCX

0x26dcc7 JGE	26dd08

0x26dcc9 SUB	%R9,%RSI

0x26dccc MOV	-0x118(%RBP),%R9

0x26dcd3 SAL	$0x3,%RCX

0x26dcd7 MOV	-0x110(%RBP),%R11

0x26dcde ADD	0x8(%R9),%RCX

0x26dce2 XOR	%R9D,%R9D

0x26dce5 NOPW	%CS:(%RAX,%RAX,1)

  (1039) 0x26dcf0 MOV	(%RCX,%R9,8),%R10

  (1039) 0x26dcf4 INC	%R9

  (1039) 0x26dcf7 MOV	(%R11,%R10,8),%R10

  (1039) 0x26dcfb MOV	%R8,(%RBX,%R10,8)

  (1039) 0x26dcff CMP	%R9,%RSI

  (1039) 0x26dd02 JNE	26dcf0

0x26dd04 MOV	(%RDX,%R8,8),%R9

0x26dd08 MOV	-0x50(%RBP),%RDX

0x26dd0c VXORPD	%XMM4,%XMM4,%XMM4

0x26dd10 MOV	(%RDX,%R8,8),%RCX

0x26dd14 MOV	0x8(%RDX,%R8,8),%R11

0x26dd19 INC	%RCX

0x26dd1c CMP	%R11,%RCX

0x26dd1f JGE	26dde0

0x26dd25 MOV	-0xd0(%RBP),%RDX

0x26dd2c MOV	-0x128(%RBP),%R15

0x26dd33 MOV	-0xb8(%RBP),%R10

0x26dd3a MOV	-0xc0(%RBP),%RAX

0x26dd41 VXORPD	%XMM3,%XMM3,%XMM3

0x26dd45 MOV	(%RDX),%RSI

0x26dd48 MOV	(%R15),%RDX

0x26dd4b MOV	(%R10),%R10

0x26dd4e MOV	(%RAX),%RAX

0x26dd51 MOV	%RDX,-0x30(%RBP)

0x26dd55 MOV	-0x120(%RBP),%RDX

0x26dd5c MOV	(%RDX),%R13

0x26dd5f MOV	-0x48(%RBP),%RDX

0x26dd63 JMP	26dd78

  (1038) 0x26dd70 INC	%RCX

  (1038) 0x26dd73 CMP	%R11,%RCX

  (1038) 0x26dd76 JGE	26dde4

  (1038) 0x26dd78 MOV	-0xb0(%RBP),%R15

  (1038) 0x26dd7f MOV	-0xa8(%RBP),%R12

  (1038) 0x26dd86 MOV	(%R15,%RCX,8),%R15

  (1038) 0x26dd8a CMPQ	$-0x3,(%R12,%R15,8)

  (1038) 0x26dd8f JE	26dda7

  (1038) 0x26dd91 CMPQ	$0x1,(%RDX)

  (1038) 0x26dd95 JE	26dda1

  (1038) 0x26dd97 MOV	(%RSI,%R8,8),%R12

  (1038) 0x26dd9b CMP	%R12,(%RSI,%R15,8)

  (1038) 0x26dd9f JNE	26dda7

  (1038) 0x26dda1 VADDSD	(%R10,%RCX,8),%XMM3,%XMM3

  (1038) 0x26dda7 CMP	$-0x1,%R15

  (1038) 0x26ddab JE	26dd70

  (1038) 0x26ddad CMP	%R8,(%RBX,%R15,8)

  (1038) 0x26ddb1 JNE	26dd70

  (1038) 0x26ddb3 VMOVSD	(%R10,%RCX,8),%XMM5

  (1038) 0x26ddb9 MOV	-0x30(%RBP),%R11

  (1038) 0x26ddbd VMOVSD	%XMM5,(%RAX,%R9,8)

  (1038) 0x26ddc3 MOV	(%R11,%R15,8),%R11

  (1038) 0x26ddc7 MOV	%R11,(%R13,%R9,8)

  (1038) 0x26ddcc MOV	-0x50(%RBP),%R11

  (1038) 0x26ddd0 INC	%R9

  (1038) 0x26ddd3 VADDSD	(%R10,%RCX,8),%XMM4,%XMM4

  (1038) 0x26ddd9 MOV	0x8(%R11,%R8,8),%R11

  (1038) 0x26ddde JMP	26dd70

0x26dde0 VXORPD	%XMM3,%XMM3,%XMM3

0x26dde4 MOV	-0x88(%RBP),%RCX

0x26ddeb MOV	-0x38(%RBP),%RDX

0x26ddef MOV	(%RCX,%R8,8),%RCX

0x26ddf3 MOV	0x8(%RDX,%R8,8),%RSI

0x26ddf8 MOV	(%RDX,%R8,8),%R11

0x26ddfc LEA	(%RSI,%RCX,1),%R10

0x26de00 SUB	%R11,%R10

0x26de03 CMP	%R10,%RCX

0x26de06 JGE	26de4c

0x26de08 MOV	-0x108(%RBP),%RDX

0x26de0f SAL	$0x3,%RCX

0x26de13 SUB	%R11,%RSI

0x26de16 XOR	%R10D,%R10D

0x26de19 ADD	0x8(%RDX),%RCX

0x26de1d MOV	-0x100(%RBP),%RDX

0x26de24 NOPW	%CS:(%RAX,%RAX,1)

  (1037) 0x26de30 MOV	(%RCX,%R10,8),%R11

  (1037) 0x26de34 INC	%R10

  (1037) 0x26de37 MOV	(%RDX,%R11,8),%R11

  (1037) 0x26de3b MOV	%R8,(%R14,%R11,8)

  (1037) 0x26de3f CMP	%R10,%RSI

  (1037) 0x26de42 JNE	26de30

0x26de44 MOV	-0x38(%RBP),%RCX

0x26de48 MOV	(%RCX,%R8,8),%R11

0x26de4c MOV	-0x40(%RBP),%RCX

0x26de50 MOV	(%RCX,%R8,8),%R15

0x26de54 MOV	0x8(%RCX,%R8,8),%R10

0x26de59 CMP	%R10,%R15

0x26de5c JGE	26dff0

0x26de62 MOV	-0xd0(%RBP),%RDX

0x26de69 MOV	-0x130(%RBP),%RCX

0x26de70 MOV	(%RDX),%RAX

0x26de73 MOV	(%RCX),%RCX

0x26de76 MOV	%RAX,-0x60(%RBP)

0x26de7a MOV	-0x138(%RBP),%RDX

0x26de81 MOV	(%RDX),%RAX

0x26de84 MOV	%RAX,-0x58(%RBP)

0x26de88 MOV	-0xc8(%RBP),%RAX

0x26de8f MOV	-0x140(%RBP),%RDX

0x26de96 MOV	(%RAX),%RAX

0x26de99 MOV	(%RDX),%RSI

0x26de9c MOV	%RAX,-0x30(%RBP)

0x26dea0 MOV	-0x150(%RBP),%RDX

0x26dea7 MOV	(%RDX),%RAX

0x26deaa MOV	%RAX,-0x70(%RBP)

0x26deae MOV	-0x148(%RBP),%RDX

0x26deb5 MOV	(%RDX),%RAX

0x26deb8 MOV	%RAX,-0x68(%RBP)

0x26debc CMPQ	$0,-0xf8(%RBP)

0x26dec4 JE	26df69

0x26deca MOV	-0xf0(%RBP),%RDX

0x26ded1 MOV	(%RDX),%R13

0x26ded4 MOV	-0x48(%RBP),%RDX

0x26ded8 JMP	26deec

  (1036) 0x26dee0 INC	%R15

  (1036) 0x26dee3 CMP	%R10,%R15

  (1036) 0x26dee6 JGE	26dff0

  (1036) 0x26deec MOV	(%RCX,%R15,8),%R12

  (1036) 0x26def0 MOV	-0x78(%RBP),%RAX

  (1036) 0x26def4 MOV	(%R13,%R12,8),%R12

  (1036) 0x26def9 CMPQ	$-0x3,(%RAX,%R12,8)

  (1036) 0x26defe JE	26df22

  (1036) 0x26df00 CMPQ	$0x1,(%RDX)

  (1036) 0x26df04 JE	26df1c

  (1036) 0x26df06 MOV	-0x60(%RBP),%RAX

  (1036) 0x26df0a MOV	(%RAX,%R8,8),%RDX

  (1036) 0x26df0e MOV	-0x58(%RBP),%RAX

  (1036) 0x26df12 CMP	(%RAX,%R12,8),%RDX

  (1036) 0x26df16 MOV	-0x48(%RBP),%RDX

  (1036) 0x26df1a JNE	26df22

  (1036) 0x26df1c VADDSD	(%RSI,%R15,8),%XMM3,%XMM3

  (1036) 0x26df22 CMP	$-0x1,%R12

  (1036) 0x26df26 JE	26dee0

  (1036) 0x26df28 CMP	%R8,(%R14,%R12,8)

  (1036) 0x26df2c JNE	26dee0

  (1036) 0x26df2e VMOVSD	(%RSI,%R15,8),%XMM5

  (1036) 0x26df34 MOV	-0x30(%RBP),%RAX

  (1036) 0x26df38 MOV	-0x70(%RBP),%RDX

  (1036) 0x26df3c MOV	-0x68(%RBP),%R10

  (1036) 0x26df40 VMOVSD	%XMM5,(%RAX,%R11,8)

  (1036) 0x26df46 MOV	(%RDX,%R12,8),%RDX

  (1036) 0x26df4a MOV	%RDX,(%R10,%R11,8)

  (1036) 0x26df4e MOV	-0x40(%RBP),%R10

  (1036) 0x26df52 MOV	-0x48(%RBP),%RDX

  (1036) 0x26df56 INC	%R11

  (1036) 0x26df59 VADDSD	(%RSI,%R15,8),%XMM4,%XMM4

  (1036) 0x26df5f MOV	0x8(%R10,%R8,8),%R10

  (1036) 0x26df64 JMP	26dee0

0x26df69 MOV	-0x48(%RBP),%RDX

0x26df6d JMP	26df78

  (1035) 0x26df70 INC	%R15

  (1035) 0x26df73 CMP	%R10,%R15

  (1035) 0x26df76 JGE	26dff0

  (1035) 0x26df78 MOV	(%RCX,%R15,8),%R13

  (1035) 0x26df7c MOV	-0x78(%RBP),%R12

  (1035) 0x26df80 CMPQ	$-0x3,(%R12,%R13,8)

  (1035) 0x26df85 JE	26dfa5

  (1035) 0x26df87 CMPQ	$0x1,(%RDX)

  (1035) 0x26df8b JE	26df9f

  (1035) 0x26df8d MOV	-0x60(%RBP),%RAX

  (1035) 0x26df91 MOV	(%RAX,%R8,8),%R12

  (1035) 0x26df95 MOV	-0x58(%RBP),%RAX

  (1035) 0x26df99 CMP	%R12,(%RAX,%R13,8)

  (1035) 0x26df9d JNE	26dfa5

  (1035) 0x26df9f VADDSD	(%RSI,%R15,8),%XMM3,%XMM3

  (1035) 0x26dfa5 CMP	$-0x1,%R13

  (1035) 0x26dfa9 JE	26df70

  (1035) 0x26dfab CMP	%R8,(%R14,%R13,8)

  (1035) 0x26dfaf JNE	26df70

  (1035) 0x26dfb1 VMOVSD	(%RSI,%R15,8),%XMM5

  (1035) 0x26dfb7 MOV	-0x30(%RBP),%RAX

  (1035) 0x26dfbb MOV	-0x70(%RBP),%R10

  (1035) 0x26dfbf MOV	-0x68(%RBP),%R12

  (1035) 0x26dfc3 VMOVSD	%XMM5,(%RAX,%R11,8)

  (1035) 0x26dfc9 MOV	(%R10,%R13,8),%R10

  (1035) 0x26dfcd MOV	%R10,(%R12,%R11,8)

  (1035) 0x26dfd1 MOV	-0x40(%RBP),%R10

  (1035) 0x26dfd5 INC	%R11

  (1035) 0x26dfd8 VADDSD	(%RSI,%R15,8),%XMM4,%XMM4

  (1035) 0x26dfde MOV	0x8(%R10,%R8,8),%R10

  (1035) 0x26dfe3 JMP	26df70

0x26dff0 MOV	-0x50(%RBP),%RCX

0x26dff4 MOV	-0x80(%RBP),%RAX

0x26dff8 MOV	(%RCX,%R8,8),%RCX

0x26dffc VMULSD	(%RAX,%RCX,8),%XMM4,%XMM4

0x26e001 VUCOMISD	%XMM0,%XMM4

0x26e005 JNE	26e009

0x26e007 JNP	26e011

0x26e009 VXORPD	%XMM1,%XMM3,%XMM2

0x26e00d VDIVSD	%XMM4,%XMM2,%XMM2

0x26e011 MOV	-0x90(%RBP),%RDX

0x26e018 MOV	-0x158(%RBP),%RAX

0x26e01f MOV	%R9,%RSI

0x26e022 MOV	(%RDX,%R8,8),%RCX

0x26e026 SUB	%RCX,%RSI

0x26e029 JLE	26e102

0x26e02f CMP	$0x4,%RSI

0x26e033 JB	26e0f0

0x26e039 CMP	$0x20,%RSI

0x26e03d JAE	26e044

0x26e03f XOR	%R10D,%R10D

0x26e042 JMP	26e0b2

0x26e044 MOV	-0xe8(%RBP),%R15

0x26e04b VBROADCASTSD	%XMM2,%ZMM3

0x26e051 MOV	%RSI,%R10

0x26e054 AND	$-0x20,%R10

0x26e058 XOR	%R12D,%R12D

0x26e05b LEA	(%R15,%RCX,8),%R15

0x26e05f NOP

  (1033) 0x26e060 VMULPD	-0xc0(%R15,%R12,8),%ZMM3,%ZMM4

  (1033) 0x26e068 VMULPD	-0x80(%R15,%R12,8),%ZMM3,%ZMM5

  (1033) 0x26e070 VMULPD	-0x40(%R15,%R12,8),%ZMM3,%ZMM6

  (1033) 0x26e078 VMULPD	(%R15,%R12,8),%ZMM3,%ZMM7

  (1033) 0x26e07f VMOVUPD	%ZMM4,-0xc0(%R15,%R12,8)

  (1033) 0x26e087 VMOVUPD	%ZMM5,-0x80(%R15,%R12,8)

  (1033) 0x26e08f VMOVUPD	%ZMM6,-0x40(%R15,%R12,8)

  (1033) 0x26e097 VMOVUPD	%ZMM7,(%R15,%R12,8)

  (1033) 0x26e09e ADD	$0x20,%R12

  (1033) 0x26e0a2 CMP	%R12,%R10

  (1033) 0x26e0a5 JNE	26e060

0x26e0a7 CMP	%R10,%RSI

0x26e0aa JE	26e102

0x26e0ac TEST	$0x1c,%SIL

0x26e0b0 JE	26e0ec

0x26e0b2 MOV	%RSI,%R15

0x26e0b5 AND	$-0x4,%R15

0x26e0b9 LEA	(%RAX,%RCX,8),%R12

0x26e0bd VBROADCASTSD	%XMM2,%YMM3

0x26e0c2 ADD	%R15,%RCX

0x26e0c5 NOPW	%CS:(%RAX,%RAX,1)

  (1034) 0x26e0d0 VMULPD	(%R12,%R10,8),%YMM3,%YMM4

  (1034) 0x26e0d6 VMOVUPD	%YMM4,(%R12,%R10,8)

  (1034) 0x26e0dc ADD	$0x4,%R10

  (1034) 0x26e0e0 CMP	%R10,%R15

  (1034) 0x26e0e3 JNE	26e0d0

0x26e0e5 CMP	%R15,%RSI

0x26e0e8 JNE	26e0f0

0x26e0ea JMP	26e102

0x26e0ec ADD	%R10,%RCX

0x26e0ef NOP

  (1032) 0x26e0f0 VMULSD	(%RAX,%RCX,8),%XMM2,%XMM3

  (1032) 0x26e0f5 VMOVSD	%XMM3,(%RAX,%RCX,8)

  (1032) 0x26e0fa INC	%RCX

  (1032) 0x26e0fd CMP	%RCX,%R9

  (1032) 0x26e100 JNE	26e0f0

0x26e102 MOV	-0x38(%RBP),%RCX

0x26e106 MOV	%R11,%RSI

0x26e109 MOV	(%RCX,%R8,8),%RCX

0x26e10d SUB	%RCX,%RSI

0x26e110 JLE	26dc80

0x26e116 CMP	$0x4,%RSI

0x26e11a JB	26e1f0

0x26e120 CMP	$0x20,%RSI

0x26e124 JAE	26e12b

0x26e126 XOR	%R8D,%R8D

0x26e129 JMP	26e1a6

0x26e12b MOV	-0xe0(%RBP),%RAX

0x26e132 VBROADCASTSD	%XMM2,%ZMM3

0x26e138 MOV	%RSI,%R8

0x26e13b AND	$-0x20,%R8

0x26e13f XOR	%R10D,%R10D

0x26e142 LEA	(%RAX,%RCX,8),%R9

0x26e146 NOPW	%CS:(%RAX,%RAX,1)

  (1030) 0x26e150 VMULPD	-0xc0(%R9,%R10,8),%ZMM3,%ZMM4

  (1030) 0x26e158 VMULPD	-0x80(%R9,%R10,8),%ZMM3,%ZMM5

  (1030) 0x26e160 VMULPD	-0x40(%R9,%R10,8),%ZMM3,%ZMM6

  (1030) 0x26e168 VMULPD	(%R9,%R10,8),%ZMM3,%ZMM7

  (1030) 0x26e16f VMOVUPD	%ZMM4,-0xc0(%R9,%R10,8)

  (1030) 0x26e177 VMOVUPD	%ZMM5,-0x80(%R9,%R10,8)

  (1030) 0x26e17f VMOVUPD	%ZMM6,-0x40(%R9,%R10,8)

  (1030) 0x26e187 VMOVUPD	%ZMM7,(%R9,%R10,8)

  (1030) 0x26e18e ADD	$0x20,%R10

  (1030) 0x26e192 CMP	%R10,%R8

  (1030) 0x26e195 JNE	26e150

0x26e197 CMP	%R8,%RSI

0x26e19a JE	26dc80

0x26e1a0 TEST	$0x1c,%SIL

0x26e1a4 JE	26e1df

0x26e1a6 MOV	%RSI,%R9

0x26e1a9 AND	$-0x4,%R9

0x26e1ad LEA	(%RDI,%RCX,8),%R10

0x26e1b1 VBROADCASTSD	%XMM2,%YMM3

0x26e1b6 ADD	%R9,%RCX

0x26e1b9 NOPL	(%RAX)

  (1031) 0x26e1c0 VMULPD	(%R10,%R8,8),%YMM3,%YMM4

  (1031) 0x26e1c6 VMOVUPD	%YMM4,(%R10,%R8,8)

  (1031) 0x26e1cc ADD	$0x4,%R8

  (1031) 0x26e1d0 CMP	%R8,%R9

  (1031) 0x26e1d3 JNE	26e1c0

0x26e1d5 CMP	%R9,%RSI

0x26e1d8 JNE	26e1f0

0x26e1da JMP	26dc80

0x26e1df ADD	%R8,%RCX

0x26e1e2 NOPW	%CS:(%RAX,%RAX,1)

  (1029) 0x26e1f0 VMULSD	(%RDI,%RCX,8),%XMM2,%XMM3

  (1029) 0x26e1f5 VMOVSD	%XMM3,(%RDI,%RCX,8)

  (1029) 0x26e1fa INC	%RCX

  (1029) 0x26e1fd CMP	%RCX,%R11

  (1029) 0x26e200 JNE	26e1f0

0x26e202 JMP	26dc80

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1605 - 1660

--------------------------------------------------------------------------------

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►97.05+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.91+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1575	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.80
CQA speedup if FP arith vectorized	3.70
CQA speedup if fully vectorized	13.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.18
Source	par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1612,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1633,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.63
CQA cycles if no scalar integer	7.38
CQA cycles if FP arith vectorized	5.57
CQA cycles if fully vectorized	1.51
Front-end cycles	20.63
P0 cycles	11.67
P1 cycles	11.67
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	19.00
P7 cycles	19.00
P8 cycles	19.00
P9 cycles	19.00
P10 cycles	1.25
P11 cycles	3.00
P12 cycles	2.50
P13 cycles	1.25
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	172.00
Nb uops	165.00
Nb loads	69.00
Nb stores	7.00
Nb stack references	36.00
FLOP/cycle	0.10
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.48
Bytes prefetched	0.00
Bytes loaded	552.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.43
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.32

Metric	Value
CQA speedup if no scalar integer	2.80
CQA speedup if FP arith vectorized	3.70
CQA speedup if fully vectorized	13.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.18
Source	par_multi_interp.c:1605-1607,par_multi_interp.c:1610-1612,par_multi_interp.c:1617-1618,par_multi_interp.c:1631-1633,par_multi_interp.c:1638-1639,par_multi_interp.c:1655-1659
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.63
CQA cycles if no scalar integer	7.38
CQA cycles if FP arith vectorized	5.57
CQA cycles if fully vectorized	1.51
Front-end cycles	20.63
P0 cycles	11.67
P1 cycles	11.67
P2 cycles	11.67
P3 cycles	11.67
P4 cycles	11.67
P5 cycles	11.67
P6 cycles	19.00
P7 cycles	19.00
P8 cycles	19.00
P9 cycles	19.00
P10 cycles	1.25
P11 cycles	3.00
P12 cycles	2.50
P13 cycles	1.25
P14 cycles	0.50
P15 cycles	0.50
DIV/SQRT cycles	4.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	172.00
Nb uops	165.00
Nb loads	69.00
Nb stores	7.00
Nb stack references	36.00
FLOP/cycle	0.10
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.48
Bytes prefetched	0.00
Bytes loaded	552.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.43
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	14.32

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.18
Source file and lines	par_multi_interp.c:1605-1660
Module	exec

The loop is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1605-1660.

Analyzed code is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1605-1607,1610-1612,1617-1618,1631-1633,1638-1639,1655-1659.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.63 to 7.38 cycles (2.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 20.63 to 1.51 cycles (13.62x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1656

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 552 bytes (69 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	165
loop length	760
used x86 registers	13
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	1
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.63 cycles
front end	20.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	19.00	19.00	19.00	19.00	1.25	3.00	2.50	1.25	0.50	0.50
cycles	11.67	11.67	11.67	11.67	11.67	11.67	19.00	19.00	19.00	19.00	1.25	3.00	2.50	1.25	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	20.63
Dispatch	19.00
DIV/SQRT	4.00
Overall L1	20.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	36%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.63 cycles. At this rate:

10% of peak load performance is reached (26.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.63 to 19.00 cycles (1.09x speedup).

ASM code

In the binary file, the address of the loop is: 26dc97

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,-0xd8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 26e207 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8f7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x160(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R11,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dd08 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x3f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x118(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x110(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x8(%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RDX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dde0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x128(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xb8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xc0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x120(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26dd78 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x468>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26de4c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x53c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x108(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R11,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x8(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x100(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%R8,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R10,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dff0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x130(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x138(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x150(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x148(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMPQ $0,-0xf8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 26df69 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x659>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26deec <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x5dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26df78 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x668>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD (%RAX,%RCX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 26e009 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6f9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JNP 26e011 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x701>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VDIVSD %XMM4,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x158(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 26e0f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 26e044 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x734>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 26e0b2 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xe8(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
LEA (%R15,%RCX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26e0ec <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 26e0f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 26e1f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 26e12b <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x81b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 26e1a6 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RAX,%RCX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26e1df <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 26e1f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.18
Source file and lines	par_multi_interp.c:1605-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.63 to 7.38 cycles (2.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1656

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 552 bytes (69 double precision FP elements). The binary loop is storing 56 bytes (7 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	165
loop length	760
used x86 registers	13
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	1
nb stack references	36

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.63 cycles
front end	20.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	11.67	11.67	11.67	11.67	11.67	11.67	19.00	19.00	19.00	19.00	1.25	3.00	2.50	1.25	0.50	0.50
cycles	11.67	11.67	11.67	11.67	11.67	11.67	19.00	19.00	19.00	19.00	1.25	3.00	2.50	1.25	0.50	0.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

4.00

Cycles summary

Front-end	20.63
Dispatch	19.00
DIV/SQRT	4.00
Overall L1	20.63

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	36%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	44%

INT+FP

all	11%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	18%

INT+FP

all	13%
load	12%
store	12%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.63 cycles. At this rate:

10% of peak load performance is reached (26.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 26dc97

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV -0xa0(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,-0xd8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 26e207 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8f7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x160(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R11,8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R9,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dd08 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x3f8>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x118(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV -0x110(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD 0x8(%R9),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV (%RDX,%R8,8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RDX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R11,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dde0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x4d0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x128(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xb8(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0xc0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x120(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26dd78 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x468>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV -0x88(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDX,%R8,8),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA (%RSI,%RCX,1),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R11,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26de4c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x53c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x108(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %R11,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
ADD 0x8(%RDX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV -0x100(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RCX,%R8,8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R10,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 26dff0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xd0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x130(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x138(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0xc8(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x140(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x150(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x148(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMPQ $0,-0xf8(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JE 26df69 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x659>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0xf0(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26deec <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x5dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x48(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JMP 26df78 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x668>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULSD (%RAX,%RCX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VUCOMISD %XMM0,%XMM4	2	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	6	0.50	scal (12.5%)
JNE 26e009 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6f9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JNP 26e011 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x701>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VXORPD %XMM1,%XMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VDIVSD %XMM4,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	scal (12.5%)
MOV -0x90(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x158(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 26e0f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 26e044 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x734>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 26e0b2 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xe8(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
LEA (%R15,%RCX,8),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R10,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26e0ec <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RCX,8),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 26e0f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 26e102 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x7f2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R10,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RCX,%R8,8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RCX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JLE 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 26e1f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMP $0x20,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 26e12b <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x81b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 26e1a6 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x896>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0xe0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
LEA (%RAX,%RCX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R8,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST $0x1c,%SIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 26e1df <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8cf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%RDI,%RCX,8),%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VBROADCASTSD %XMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
ADD %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
CMP %R9,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 26e1f0 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x8e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %R8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 26dc80 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x370>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code