OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace.omp

	Function: hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9	Module: exec	Source: csr_matvec.c:178-204 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 204

--------------------------------------------------------------------------------

178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE

179: #endif

180:

181:          for (i = 0; i < num_rownnz; i++)

182:          {

183:             m = A_rownnz[i];

[...]

194:                for (jj = A_i[m]; jj < A_i[m+1]; jj++)

195:                   tempx +=  A_data[jj] * x_data[A_j[jj]];

196:                y_data[m] += tempx;

197:             }

198:             else

199:                for ( j=0; j<num_vectors; ++j )

200:                {

201:                   tempx = 0;

202:                   for (jj = A_i[m]; jj < A_i[m+1]; jj++)

203:                      tempx +=  A_data[jj] * x_data[ j*vecstride_x + A_j[jj]*idxstride_x ];

204:                   y_data[ j*vecstride_y + m*idxstride_y] += tempx;

0x2d5be0 PUSH	%RBP

0x2d5be1 MOV	%RSP,%RBP

0x2d5be4 PUSH	%R15

0x2d5be6 PUSH	%R14

0x2d5be8 PUSH	%R13

0x2d5bea PUSH	%R12

0x2d5bec PUSH	%RBX

0x2d5bed SUB	$0x88,%RSP

0x2d5bf4 MOV	(%RDX),%RBX

0x2d5bf7 TEST	%RBX,%RBX

0x2d5bfa JLE	2d5c8a

0x2d5c00 MOV	(%RDI),%ESI

0x2d5c02 DEC	%RBX

0x2d5c05 MOV	%R9,%R14

0x2d5c08 MOV	%R8,%R15

0x2d5c0b MOV	%RCX,%R12

0x2d5c0e MOVQ	$0,-0x60(%RBP)

0x2d5c16 MOVQ	$0x1,-0xa8(%RBP)

0x2d5c21 MOVL	$0,-0x40(%RBP)

0x2d5c28 MOV	%RBX,-0x38(%RBP)

0x2d5c2c SUB	$0x8,%RSP

0x2d5c30 LEA	-0xa8(%RBP),%RAX

0x2d5c37 LEA	0x12822(%RIP),%RDI

0x2d5c3e LEA	-0x40(%RBP),%RCX

0x2d5c42 LEA	-0x60(%RBP),%R8

0x2d5c46 LEA	-0x38(%RBP),%R9

0x2d5c4a MOV	%ESI,-0x3c(%RBP)

0x2d5c4d MOV	$0x22,%EDX

0x2d5c52 PUSH	$0x1

0x2d5c54 PUSH	$0x1

0x2d5c56 PUSH	%RAX

0x2d5c57 CALL	2e2d50 <@plt_start@+0x90>

0x2d5c5c ADD	$0x20,%RSP

0x2d5c60 MOV	-0x38(%RBP),%RAX

0x2d5c64 CMP	%RBX,%RAX

0x2d5c67 CMOVL	%RAX,%RBX

0x2d5c6b MOV	-0x60(%RBP),%RAX

0x2d5c6f MOV	%RBX,-0x38(%RBP)

0x2d5c73 CMP	%RBX,%RAX

0x2d5c76 JLE	2d5c9c

0x2d5c78 MOV	-0x3c(%RBP),%ESI

0x2d5c7b LEA	0x127f6(%RIP),%RDI

0x2d5c82 VZEROUPPER

0x2d5c85 CALL	2e2d60 <@plt_start@+0xa0>

0x2d5c8a ADD	$0x88,%RSP

0x2d5c91 POP	%RBX

0x2d5c92 POP	%R12

0x2d5c94 POP	%R13

0x2d5c96 POP	%R14

0x2d5c98 POP	%R15

0x2d5c9a POP	%RBP

0x2d5c9b RET

0x2d5c9c MOV	0x28(%RBP),%RCX

0x2d5ca0 MOV	0x20(%RBP),%RDI

0x2d5ca4 MOV	0x18(%RBP),%RDX

0x2d5ca8 MOV	0x10(%RBP),%R8

0x2d5cac MOV	(%R12),%R12

0x2d5cb0 MOV	(%R15),%R10

0x2d5cb3 MOV	(%R14),%R14

0x2d5cb6 MOV	(%RCX),%RSI

0x2d5cb9 CMP	$0x1,%R10

0x2d5cbd JNE	2d5d1a

0x2d5cbf MOV	(%R8),%RCX

0x2d5cc2 MOV	(%RDX),%RDX

0x2d5cc5 MOV	(%RDI),%RDI

0x2d5cc8 JMP	2d5ce8

0x2d5cca NOPW	(%RAX,%RAX,1)

(3273) 0x2d5cd0 VADDSD	(%RSI,%R8,8),%XMM0,%XMM0

(3273) 0x2d5cd6 CMP	%RBX,%RAX

(3273) 0x2d5cd9 VMOVSD	%XMM0,(%RSI,%R8,8)

(3273) 0x2d5cdf LEA	0x1(%RAX),%R8

(3273) 0x2d5ce3 MOV	%R8,%RAX

(3273) 0x2d5ce6 JGE	2d5c78

(3273) 0x2d5ce8 MOV	(%R12,%RAX,8),%R8

(3273) 0x2d5cec VXORPD	%XMM0,%XMM0,%XMM0

(3273) 0x2d5cf0 MOV	(%R14,%R8,8),%R9

(3273) 0x2d5cf4 MOV	0x8(%R14,%R8,8),%R10

(3273) 0x2d5cf9 CMP	%R10,%R9

(3273) 0x2d5cfc JGE	2d5cd0

(3273) 0x2d5cfe XCHG	%AX,%AX

  (3274) 0x2d5d00 MOV	(%RDI,%R9,8),%R11

  (3274) 0x2d5d04 VMOVSD	(%RCX,%R9,8),%XMM1

  (3274) 0x2d5d0a INC	%R9

  (3274) 0x2d5d0d VFMADD231SD	(%RDX,%R11,8),%XMM1,%XMM0

  (3274) 0x2d5d13 CMP	%R9,%R10

  (3274) 0x2d5d16 JNE	2d5d00

(3273) 0x2d5d18 JMP	2d5cd0

0x2d5d1a JL	2d5c78

0x2d5d20 MOV	0x40(%RBP),%RDX

0x2d5d24 MOV	0x48(%RBP),%RCX

0x2d5d28 CMP	$0x4,%R10

0x2d5d2c MOV	%R10,%R9

0x2d5d2f VXORPD	%XMM0,%XMM0,%XMM0

0x2d5d33 VXORPD	%XMM1,%XMM1,%XMM1

0x2d5d37 VXORPD	%XMM2,%XMM2,%XMM2

0x2d5d3b MOV	%RBX,-0x90(%RBP)

0x2d5d42 MOV	%R12,-0x88(%RBP)

0x2d5d49 MOV	%R14,-0x80(%RBP)

0x2d5d4d MOV	(%RDX),%RDX

0x2d5d50 MOV	(%RCX),%RDI

0x2d5d53 SETAE	%CL

0x2d5d56 CMP	$0x1,%RDX

0x2d5d5a MOV	%RDX,-0x58(%RBP)

0x2d5d5e LEA	(,%RDX,8),%RDX

0x2d5d66 MOV	%RDI,-0x78(%RBP)

0x2d5d6a SETE	%R8B

0x2d5d6e AND	$-0x4,%R9

0x2d5d72 AND	%CL,%R8B

0x2d5d75 MOV	%R9,-0x70(%RBP)

0x2d5d79 MOV	%RDX,-0x98(%RBP)

0x2d5d80 MOV	%R8B,-0x29(%RBP)

0x2d5d84 MOV	%R10,%R8

0x2d5d87 AND	$-0x20,%R8

0x2d5d8b MOV	%R8,-0x48(%RBP)

0x2d5d8f LEA	(,%RDI,8),%R8

0x2d5d97 LEA	0xc0(%RSI),%RDI

0x2d5d9e MOV	%RDI,-0x68(%RBP)

0x2d5da2 MOV	%R8,-0x50(%RBP)

0x2d5da6 JMP	2d5dcf

0x2d5da8 NOPL	(%RAX,%RAX,1)

(3268) 0x2d5db0 MOV	-0x88(%RBP),%R12

(3268) 0x2d5db7 MOV	-0x80(%RBP),%R14

(3268) 0x2d5dbb LEA	0x1(%RAX),%RCX

(3268) 0x2d5dbf CMP	-0x90(%RBP),%RAX

(3268) 0x2d5dc6 MOV	%RCX,%RAX

(3268) 0x2d5dc9 JGE	2d5c78

(3268) 0x2d5dcf MOV	(%R12,%RAX,8),%R8

(3268) 0x2d5dd3 MOV	%R8,%RBX

(3268) 0x2d5dd6 IMUL	-0x78(%RBP),%RBX

(3268) 0x2d5ddb MOV	(%R14,%R8,8),%R15

(3268) 0x2d5ddf MOV	0x8(%R14,%R8,8),%R12

(3268) 0x2d5de4 CMP	%R12,%R15

(3268) 0x2d5de7 JGE	2d5e90

(3268) 0x2d5ded MOV	0x10(%RBP),%RCX

(3268) 0x2d5df1 MOV	0x30(%RBP),%RDX

(3268) 0x2d5df5 MOV	0x20(%RBP),%R9

(3268) 0x2d5df9 MOV	0x38(%RBP),%RDI

(3268) 0x2d5dfd XOR	%R13D,%R13D

(3268) 0x2d5e00 MOV	(%RCX),%R8

(3268) 0x2d5e03 MOV	0x18(%RBP),%RCX

(3268) 0x2d5e07 MOV	(%RDX),%RDX

(3268) 0x2d5e0a MOV	(%R9),%R9

(3268) 0x2d5e0d MOV	(%RDI),%R14

(3268) 0x2d5e10 MOV	(%RCX),%RCX

(3268) 0x2d5e13 MOV	%RDX,-0xa0(%RBP)

(3268) 0x2d5e1a NOPW	(%RAX,%RAX,1)

  (3272) 0x2d5e20 MOV	%R13,%RDI

  (3272) 0x2d5e23 IMUL	-0xa0(%RBP),%RDI

  (3272) 0x2d5e2b VXORPD	%XMM3,%XMM3,%XMM3

  (3272) 0x2d5e2f MOV	%R15,%R11

  (3272) 0x2d5e32 NOPW	%CS:(%RAX,%RAX,1)

    (3271) 0x2d5e40 MOV	(%R9,%R11,8),%RDX

    (3271) 0x2d5e44 VMOVSD	(%R8,%R11,8),%XMM4

    (3271) 0x2d5e4a INC	%R11

    (3271) 0x2d5e4d IMUL	%R14,%RDX

    (3271) 0x2d5e51 ADD	%RDI,%RDX

    (3271) 0x2d5e54 VFMADD231SD	(%RCX,%RDX,8),%XMM4,%XMM3

    (3271) 0x2d5e5a CMP	%R11,%R12

    (3271) 0x2d5e5d JNE	2d5e40

  (3272) 0x2d5e5f MOV	%R13,%RDX

  (3272) 0x2d5e62 IMUL	-0x58(%RBP),%RDX

  (3272) 0x2d5e67 INC	%R13

  (3272) 0x2d5e6a ADD	%RBX,%RDX

  (3272) 0x2d5e6d VADDSD	(%RSI,%RDX,8),%XMM3,%XMM3

  (3272) 0x2d5e72 VMOVSD	%XMM3,(%RSI,%RDX,8)

  (3272) 0x2d5e77 CMP	%R10,%R13

  (3272) 0x2d5e7a JNE	2d5e20

(3268) 0x2d5e7c JMP	2d5db0

0x2d5e81 NOPW	%CS:(%RAX,%RAX,1)

(3268) 0x2d5e90 CMPB	$0,-0x29(%RBP)

(3268) 0x2d5e94 JE	2d5ea0

(3268) 0x2d5e96 CMP	$0x20,%R10

(3268) 0x2d5e9a JAE	2d5ea7

(3268) 0x2d5e9c XOR	%ECX,%ECX

(3268) 0x2d5e9e JMP	2d5f1d

(3268) 0x2d5ea0 XOR	%EDX,%EDX

(3268) 0x2d5ea2 JMP	2d5f51

(3268) 0x2d5ea7 MOV	-0x50(%RBP),%RCX

(3268) 0x2d5eab MOV	-0x48(%RBP),%RDI

(3268) 0x2d5eaf XOR	%EDX,%EDX

(3268) 0x2d5eb1 IMUL	%R8,%RCX

(3268) 0x2d5eb5 ADD	-0x68(%RBP),%RCX

(3268) 0x2d5eb9 NOPL	(%RAX)

  (3269) 0x2d5ec0 VADDPD	-0xc0(%RCX,%RDX,8),%ZMM1,%ZMM3

  (3269) 0x2d5ec8 VADDPD	-0x80(%RCX,%RDX,8),%ZMM1,%ZMM4

  (3269) 0x2d5ed0 VADDPD	-0x40(%RCX,%RDX,8),%ZMM1,%ZMM5

  (3269) 0x2d5ed8 VADDPD	(%RCX,%RDX,8),%ZMM1,%ZMM6

  (3269) 0x2d5edf VMOVUPD	%ZMM3,-0xc0(%RCX,%RDX,8)

  (3269) 0x2d5ee7 VMOVUPD	%ZMM4,-0x80(%RCX,%RDX,8)

  (3269) 0x2d5eef VMOVUPD	%ZMM5,-0x40(%RCX,%RDX,8)

  (3269) 0x2d5ef7 VMOVUPD	%ZMM6,(%RCX,%RDX,8)

  (3269) 0x2d5efe ADD	$0x20,%RDX

  (3269) 0x2d5f02 CMP	%RDX,%RDI

  (3269) 0x2d5f05 JNE	2d5ec0

(3268) 0x2d5f07 CMP	%RDI,%R10

(3268) 0x2d5f0a JE	2d5db0

(3268) 0x2d5f10 MOV	-0x48(%RBP),%RDX

(3268) 0x2d5f14 MOV	%RDX,%RCX

(3268) 0x2d5f17 TEST	$0x1c,%R10B

(3268) 0x2d5f1b JE	2d5f51

(3268) 0x2d5f1d IMUL	-0x50(%RBP),%R8

(3268) 0x2d5f22 MOV	-0x70(%RBP),%RDI

(3268) 0x2d5f26 ADD	%RSI,%R8

(3268) 0x2d5f29 NOPL	(%RAX)

  (3270) 0x2d5f30 VADDPD	(%R8,%RCX,8),%YMM0,%YMM3

  (3270) 0x2d5f36 VMOVUPD	%YMM3,(%R8,%RCX,8)

  (3270) 0x2d5f3c ADD	$0x4,%RCX

  (3270) 0x2d5f40 CMP	%RCX,%RDI

  (3270) 0x2d5f43 JNE	2d5f30

(3268) 0x2d5f45 MOV	%RDI,%RDX

(3268) 0x2d5f48 CMP	%RDI,%R10

(3268) 0x2d5f4b JE	2d5db0

(3268) 0x2d5f51 MOV	%R10,%RCX

(3268) 0x2d5f54 SUB	%RDX,%RCX

(3268) 0x2d5f57 IMUL	-0x58(%RBP),%RDX

(3268) 0x2d5f5c ADD	%RBX,%RDX

(3268) 0x2d5f5f LEA	(%RSI,%RDX,8),%RDX

(3268) 0x2d5f63 NOPW	%CS:(%RAX,%RAX,1)

  (3267) 0x2d5f70 VADDSD	(%RDX),%XMM2,%XMM3

  (3267) 0x2d5f74 VMOVSD	%XMM3,(%RDX)

  (3267) 0x2d5f78 ADD	-0x98(%RBP),%RDX

  (3267) 0x2d5f7f DEC	%RCX

  (3267) 0x2d5f82 JNE	2d5f70

(3268) 0x2d5f84 JMP	2d5db0

0x2d5f89 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,194-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 1.75 cycles (7.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.63 to 1.01 cycles (12.55x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 121 bytes.

General properties

nb instructions	102
nb uops	101
loop length	412
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.63
Dispatch	9.75
Overall L1	12.63

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	12%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

4% of peak load performance is reached (12.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.63 to 9.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the function is: 2d5be0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2d5c8a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x12822(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2e2d50 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2d5c9c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x127f6(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2e2d60 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 2d5d1a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x13a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 2d5ce8 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x108>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JL 2d5c78 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x98>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SETAE %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SETE %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
AND %CL,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8B,-0x29(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc0(%RSI),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d5dcf <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x1ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	csr_matvec.c:178-204
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178-183,194-204.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 1.75 cycles (7.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:178

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:181

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 121 bytes.

General properties

nb instructions	102
nb uops	101
loop length	412
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.17	6.17	6.17	6.17	6.17	6.17	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.17	6.17	6.17	6.17	6.17	6.17	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.63
Dispatch	9.75
Overall L1	12.63

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	12%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

4% of peak load performance is reached (12.04 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2d5be0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
TEST %RBX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2d5c8a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xaa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xa8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x12822(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x60(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2e2d50 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x60(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 2d5c9c <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0xbc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
LEA 0x127f6(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2e2d60 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x88,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV 0x28(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x1,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JNE 2d5d1a <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x13a>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 2d5ce8 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x108>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JL 2d5c78 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x98>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x40(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP $0x4,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VXORPD %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RBX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R12,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R14,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SETAE %CL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP $0x1,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDX,8),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SETE %R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
AND $-0x4,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
AND %CL,%R8B	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R9,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RDX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8B,-0x29(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %R8,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
LEA (,%RDI,8),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0xc0(%RSI),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %RDI,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 2d5dcf <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9+0x1ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.9–	0.05	0.03
▼Loop 3273 - csr_matvec.c:181-196 - exec–	0.01	0.01
○Loop 3274 - csr_matvec.c:194-195 - exec	0.05	0.02
▼Loop 3268 - csr_matvec.c:178-204 - exec–	0.00	0.00
○Loop 3267 - csr_matvec.c:199-204 - exec	0.00	0.00
○Loop 3270 - csr_matvec.c:199-204 - exec	0.00	0.00
○Loop 3269 - csr_matvec.c:199-204 - exec	0.00	0.00
▼Loop 3272 - csr_matvec.c:199-204 - exec–	0.00	0.00
○Loop 3271 - csr_matvec.c:199-203 - exec	0.00	0.00

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