OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 1.07% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

3412:                                  hypre_printf("Error in row %d ! Too many elements!\n",

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x2ccf50 PUSH	%RBP

0x2ccf51 MOV	%RSP,%RBP

0x2ccf54 PUSH	%R15

0x2ccf56 PUSH	%R14

0x2ccf58 PUSH	%R13

0x2ccf5a PUSH	%R12

0x2ccf5c PUSH	%RBX

0x2ccf5d SUB	$0x68,%RSP

0x2ccf61 MOV	%R9,%R12

0x2ccf64 MOV	%R8,-0x80(%RBP)

0x2ccf68 MOV	%RCX,%RBX

0x2ccf6b MOV	%RDX,%R13

0x2ccf6e MOV	%RDI,-0x30(%RBP)

0x2ccf72 CALL	2e0200 <hypre_NumActiveThreads>

0x2ccf77 MOV	%RAX,%R15

0x2ccf7a CALL	2e0210 <hypre_GetThreadNum>

0x2ccf7f MOV	%RAX,%R14

0x2ccf82 MOV	(%R13),%RAX

0x2ccf86 LEA	0x1(%R14),%RCX

0x2ccf8a CQTO

0x2ccf8c IDIV	%R15

0x2ccf8f CMP	%RDX,%R14

0x2ccf92 JGE	2ccfa5

0x2ccf94 LEA	0x1(%RAX),%R15

0x2ccf98 MOV	%R15,%RSI

0x2ccf9b IMUL	%R14,%RSI

0x2ccf9f IMUL	%RCX,%R15

0x2ccfa3 JMP	2ccfb9

0x2ccfa5 MOV	%RAX,%RSI

0x2ccfa8 IMUL	%R14,%RSI

0x2ccfac IMUL	%RAX,%RCX

0x2ccfb0 ADD	%RDX,%RCX

0x2ccfb3 ADD	%RDX,%RSI

0x2ccfb6 MOV	%RCX,%R15

0x2ccfb9 MOV	(%RBX),%R8

0x2ccfbc MOV	%RBX,-0x48(%RBP)

0x2ccfc0 MOV	%RSI,%RBX

0x2ccfc3 MOVQ	$0,(%R8,%R14,8)

0x2ccfcb CMP	%R15,%RSI

0x2ccfce JGE	2cd02f

0x2ccfd0 MOV	-0x80(%RBP),%RSI

0x2ccfd4 IMUL	%R14,%RAX

0x2ccfd8 CMP	%RDX,%R14

0x2ccfdb LEA	(%R8,%R14,8),%RCX

0x2ccfdf MOV	%R15,%RDI

0x2ccfe2 CMOVL	%R14,%RDX

0x2ccfe6 SUB	%RAX,%RDI

0x2ccfe9 SUB	%RDX,%RDI

0x2ccfec MOV	(%RSI),%RSI

0x2ccfef CMP	$0x4,%RDI

0x2ccff3 JB	2cd014

0x2ccff5 LEA	(%RSI,%R15,8),%R9

0x2ccff9 CMP	%R9,%RCX

0x2ccffc JAE	2cd86f

0x2cd002 LEA	0x8(%R8,%R14,8),%R8

0x2cd007 LEA	(%RSI,%RBX,8),%R9

0x2cd00b CMP	%R8,%R9

0x2cd00e JAE	2cd86f

0x2cd014 XOR	%R10D,%R10D

0x2cd017 MOV	%RBX,%R9

0x2cd01a NOPW	(%RAX,%RAX,1)

(3087) 0x2cd020 ADD	(%RSI,%R9,8),%R10

(3087) 0x2cd024 INC	%R9

(3087) 0x2cd027 MOV	%R10,(%RCX)

(3087) 0x2cd02a CMP	%R15,%R9

(3087) 0x2cd02d JL	2cd020

0x2cd02f MOV	-0x30(%RBP),%RAX

0x2cd033 LEA	0x1af5e(%RIP),%RDI

0x2cd03a MOV	(%RAX),%R13D

0x2cd03d MOV	%R13D,%ESI

0x2cd040 VZEROUPPER

0x2cd043 CALL	2e2d40 <@plt_start@+0x80>

0x2cd048 TEST	%R14,%R14

0x2cd04b JNE	2cd077

0x2cd04d CMPQ	$0,(%R12)

0x2cd052 JLE	2cd077

0x2cd054 MOV	-0x48(%RBP),%RAX

0x2cd058 XOR	%EDX,%EDX

0x2cd05a MOV	(%RAX),%RAX

0x2cd05d MOV	(%RAX),%RCX

(3086) 0x2cd060 ADD	0x8(%RAX,%RDX,8),%RCX

(3086) 0x2cd065 LEA	0x1(%RDX),%RSI

(3086) 0x2cd069 MOV	%RCX,0x8(%RAX,%RDX,8)

(3086) 0x2cd06e MOV	%RSI,%RDX

(3086) 0x2cd071 CMP	%RSI,(%R12)

(3086) 0x2cd075 JG	2cd060

0x2cd077 LEA	0x1af32(%RIP),%RDI

0x2cd07e MOV	%R13D,%ESI

0x2cd081 CALL	2e2d40 <@plt_start@+0x80>

0x2cd086 TEST	%R14,%R14

0x2cd089 JE	2cd0a4

0x2cd08b MOV	-0x48(%RBP),%RAX

0x2cd08f MOV	(%RAX),%RAX

0x2cd092 MOV	-0x8(%RAX,%R14,8),%R12

0x2cd097 MOV	%RBX,%RDX

0x2cd09a CMP	%R15,%RBX

0x2cd09d JL	2cd0b3

0x2cd09f JMP	2cd860

0x2cd0a4 XOR	%R12D,%R12D

0x2cd0a7 MOV	%RBX,%RDX

0x2cd0aa CMP	%R15,%RBX

0x2cd0ad JGE	2cd860

0x2cd0b3 MOV	0x60(%RBP),%RSI

0x2cd0b7 XOR	%EAX,%EAX

0x2cd0b9 MOV	%RAX,-0x40(%RBP)

0x2cd0bd MOV	%R15,-0x38(%RBP)

0x2cd0c1 JMP	2cd100

(3073) 0x2cd0c3 MOV	%RCX,-0x30(%RBP)

(3073) 0x2cd0c7 MOV	%RAX,%RDI

(3073) 0x2cd0ca MOV	0x60(%RBP),%RSI

(3073) 0x2cd0ce MOV	-0x68(%RBP),%RDX

(3073) 0x2cd0d2 MOV	-0x30(%RBP),%R8

(3073) 0x2cd0d6 MOV	(%RSI),%RAX

(3073) 0x2cd0d9 MOV	0x38(%RAX),%RCX

(3073) 0x2cd0dd MOV	%R8,(%RCX,%RDX,8)

(3073) 0x2cd0e1 MOV	0x40(%RAX),%RAX

(3073) 0x2cd0e5 MOV	%RDI,(%RAX,%RDX,8)

(3073) 0x2cd0e9 MOV	-0x60(%RBP),%RDX

(3073) 0x2cd0ed NOPL	(%RAX)

(3073) 0x2cd0f0 MOV	-0x38(%RBP),%R15

(3073) 0x2cd0f4 INC	%RDX

(3073) 0x2cd0f7 CMP	%R15,%RDX

(3073) 0x2cd0fa JGE	2cd860

(3073) 0x2cd100 MOV	0x10(%RBP),%RAX

(3073) 0x2cd104 MOV	-0x80(%RBP),%RDI

(3073) 0x2cd108 MOV	0x18(%RBP),%RCX

(3073) 0x2cd10c MOV	(%RAX),%RAX

(3073) 0x2cd10f MOV	(%RAX,%RDX,8),%RBX

(3073) 0x2cd113 MOV	(%RDI),%RAX

(3073) 0x2cd116 MOV	(%RAX,%RDX,8),%R15

(3073) 0x2cd11a MOV	(%RCX),%RAX

(3073) 0x2cd11d MOV	0x20(%RBP),%RCX

(3073) 0x2cd121 MOV	%RBX,%R8

(3073) 0x2cd124 MOV	(%RCX),%RCX

(3073) 0x2cd127 SUB	(%RAX,%RCX,8),%R8

(3073) 0x2cd12b JL	2cd1f0

(3073) 0x2cd131 CMP	%RBX,0x8(%RAX,%RCX,8)

(3073) 0x2cd136 JLE	2cd1f0

(3073) 0x2cd13c MOV	0x28(%RBP),%RAX

(3073) 0x2cd140 MOV	%RDX,-0x60(%RBP)

(3073) 0x2cd144 CMPQ	$0,(%RAX)

(3073) 0x2cd148 JE	2cd2d1

(3073) 0x2cd14e MOV	0x30(%RBP),%RAX

(3073) 0x2cd152 MOV	0x38(%RBP),%RDX

(3073) 0x2cd156 MOV	0x40(%RBP),%RCX

(3073) 0x2cd15a MOV	(%RAX),%RAX

(3073) 0x2cd15d MOV	(%RAX,%R8,8),%RBX

(3073) 0x2cd161 MOV	(%RDX),%RAX

(3073) 0x2cd164 MOV	0x48(%RBP),%RDX

(3073) 0x2cd168 MOV	(%RAX,%R8,8),%RAX

(3073) 0x2cd16c MOV	%RAX,-0x30(%RBP)

(3073) 0x2cd170 MOV	(%RCX),%RAX

(3073) 0x2cd173 MOV	(%RAX,%R8,8),%RCX

(3073) 0x2cd177 MOV	(%RDX),%RAX

(3073) 0x2cd17a MOV	(%RAX,%R8,8),%R13

(3073) 0x2cd17e MOV	%RCX,%RAX

(3073) 0x2cd181 MOV	%RCX,-0x48(%RBP)

(3073) 0x2cd185 MOV	%R15,%RCX

(3073) 0x2cd188 SUB	%R13,%RAX

(3073) 0x2cd18b SUB	%RAX,%RCX

(3073) 0x2cd18e JLE	2cd478

(3073) 0x2cd194 MOV	$0x8,%ESI

(3073) 0x2cd199 MOV	%RCX,%RDI

(3073) 0x2cd19c MOV	%RCX,-0x50(%RBP)

(3073) 0x2cd1a0 MOV	%R8,-0x68(%RBP)

(3073) 0x2cd1a4 CALL	2de630 <hypre_CAlloc>

(3073) 0x2cd1a9 MOV	-0x50(%RBP),%RDI

(3073) 0x2cd1ad MOV	$0x8,%ESI

(3073) 0x2cd1b2 MOV	%RAX,-0x58(%RBP)

(3073) 0x2cd1b6 CALL	2de630 <hypre_CAlloc>

(3073) 0x2cd1bb MOV	-0x58(%RBP),%RDI

(3073) 0x2cd1bf MOV	-0x68(%RBP),%R8

(3073) 0x2cd1c3 MOV	%RAX,%RDX

(3073) 0x2cd1c6 MOV	%RDX,-0x40(%RBP)

(3073) 0x2cd1ca TEST	%R15,%R15

(3073) 0x2cd1cd JG	2cd48b

(3073) 0x2cd1d3 MOV	0x48(%RBP),%RAX

(3073) 0x2cd1d7 MOV	(%RAX),%RAX

(3073) 0x2cd1da MOV	%R13,(%RAX,%R8,8)

(3073) 0x2cd1de MOV	-0x38(%RBP),%R15

(3073) 0x2cd1e2 TEST	%RDI,%RDI

(3073) 0x2cd1e5 JNE	2cd83c

(3073) 0x2cd1eb JMP	2cd853

(3073) 0x2cd1f0 ADD	%R15,%R12

(3073) 0x2cd1f3 CMPQ	$0,(%RSI)

(3073) 0x2cd1f7 JE	2cd0f0

(3073) 0x2cd1fd MOV	0xb8(%RBP),%RAX

(3073) 0x2cd204 MOV	(%RAX),%RDI

(3073) 0x2cd207 TEST	%RDI,%RDI

(3073) 0x2cd20a JLE	2cd0f0

(3073) 0x2cd210 TEST	%R15,%R15

(3073) 0x2cd213 JLE	2cd0f0

(3073) 0x2cd219 MOV	0xc0(%RBP),%RAX

(3073) 0x2cd220 MOV	%RDX,-0x60(%RBP)

(3073) 0x2cd224 XOR	%ECX,%ECX

(3073) 0x2cd226 XOR	%EDX,%EDX

(3073) 0x2cd228 MOV	(%RAX),%RAX

(3073) 0x2cd22b JMP	2cd246

0x2cd22d NOPL	(%RAX)

  (3074) 0x2cd230 MOV	0xb8(%RBP),%RDI

  (3074) 0x2cd237 MOV	(%RDI),%RDI

  (3074) 0x2cd23a ADD	%RSI,%RCX

  (3074) 0x2cd23d ADD	$0x2,%RDX

  (3074) 0x2cd241 CMP	%RDI,%RDX

  (3074) 0x2cd244 JGE	2cd2c0

  (3074) 0x2cd246 LEA	(,%RDX,8),%RSI

  (3074) 0x2cd24e OR	$0x8,%RSI

  (3074) 0x2cd252 MOV	(%RAX,%RSI,1),%RSI

  (3074) 0x2cd256 CMP	%RBX,(%RAX,%RDX,8)

  (3074) 0x2cd25a JNE	2cd23a

  (3074) 0x2cd25c TEST	%RSI,%RSI

  (3074) 0x2cd25f JLE	2cd23a

  (3074) 0x2cd261 MOV	0xc8(%RBP),%RDI

  (3074) 0x2cd268 MOV	0x50(%RBP),%R10

  (3074) 0x2cd26c XOR	%R9D,%R9D

  (3074) 0x2cd26f MOV	(%RDI),%R8

  (3074) 0x2cd272 MOV	(%R10),%RDI

  (3074) 0x2cd275 LEA	(%R8,%RCX,8),%R8

  (3074) 0x2cd279 JMP	2cd288

0x2cd27b NOPL	(%RAX,%RAX,1)

    (3075) 0x2cd280 INC	%R9

    (3075) 0x2cd283 CMP	%R15,%R9

    (3075) 0x2cd286 JE	2cd230

    (3075) 0x2cd288 MOV	0xd0(%RBP),%R10

    (3075) 0x2cd28f XOR	%R11D,%R11D

    (3075) 0x2cd292 MOV	(%R10),%R10

    (3075) 0x2cd295 JMP	2cd2a8

0x2cd297 NOPW	(%RAX,%RAX,1)

      (3076) 0x2cd2a0 INC	%R11

      (3076) 0x2cd2a3 CMP	%R11,%RSI

      (3076) 0x2cd2a6 JE	2cd280

      (3076) 0x2cd2a8 MOV	(%R8,%R11,8),%R13

      (3076) 0x2cd2ac CMP	%R13,(%RDI,%R9,8)

      (3076) 0x2cd2b0 JNE	2cd2a0

      (3076) 0x2cd2b2 MOVQ	$-0x1,(%R8,%R11,8)

      (3076) 0x2cd2ba INCQ	(%R10,%R14,8)

      (3076) 0x2cd2be JMP	2cd2a0

(3073) 0x2cd2c0 MOV	-0x60(%RBP),%RDX

(3073) 0x2cd2c4 MOV	-0x38(%RBP),%R15

(3073) 0x2cd2c8 MOV	0x60(%RBP),%RSI

(3073) 0x2cd2cc JMP	2cd0f4

(3073) 0x2cd2d1 MOV	(%RSI),%RAX

(3073) 0x2cd2d4 MOV	%R8,-0x68(%RBP)

(3073) 0x2cd2d8 MOV	0x38(%RAX),%RCX

(3073) 0x2cd2dc MOV	0x40(%RAX),%RAX

(3073) 0x2cd2e0 MOV	(%RAX,%R8,8),%RAX

(3073) 0x2cd2e4 MOV	(%RCX,%R8,8),%RCX

(3073) 0x2cd2e8 TEST	%R15,%R15

(3073) 0x2cd2eb JLE	2cd0c3

(3073) 0x2cd2f1 MOV	0x68(%RBP),%RDX

(3073) 0x2cd2f5 MOV	0x70(%RBP),%RDI

(3073) 0x2cd2f9 MOV	%RCX,-0x30(%RBP)

(3073) 0x2cd2fd XOR	%ESI,%ESI

(3073) 0x2cd2ff MOV	(%RDX),%RDX

(3073) 0x2cd302 MOV	%RDX,-0x58(%RBP)

(3073) 0x2cd306 MOV	0x8(%RDX,%R8,8),%RDX

(3073) 0x2cd30b MOV	%RDX,-0x90(%RBP)

(3073) 0x2cd312 MOV	(%RDI),%RDX

(3073) 0x2cd315 MOV	0xa8(%RBP),%RDI

(3073) 0x2cd31c MOV	%RDX,-0x50(%RBP)

(3073) 0x2cd320 MOV	0x8(%RDX,%R8,8),%RDX

(3073) 0x2cd325 MOV	0x50(%RBP),%R8

(3073) 0x2cd329 MOV	(%RDI),%R10

(3073) 0x2cd32c MOV	0xb0(%RBP),%RDI

(3073) 0x2cd333 MOV	%RDX,-0x88(%RBP)

(3073) 0x2cd33a MOV	(%R8),%RDX

(3073) 0x2cd33d MOV	0x58(%RBP),%R8

(3073) 0x2cd341 MOV	%RDX,-0x48(%RBP)

(3073) 0x2cd345 MOV	(%RDI),%RDX

(3073) 0x2cd348 MOV	(%R8),%R11

(3073) 0x2cd34b MOV	0x88(%RBP),%R8

(3073) 0x2cd352 MOV	0x90(%RBP),%RDI

(3073) 0x2cd359 MOV	%RDX,-0x78(%RBP)

(3073) 0x2cd35d MOV	(%RDI),%RDX

(3073) 0x2cd360 MOV	(%R8),%R8

(3073) 0x2cd363 MOV	%RAX,%RDI

(3073) 0x2cd366 MOV	%RDX,-0x70(%RBP)

(3073) 0x2cd36a JMP	2cd38d

  (3077) 0x2cd36c VMOVQ	(%R11,%R12,8),%XMM0

  (3077) 0x2cd372 MOV	-0x78(%RBP),%RDX

  (3077) 0x2cd376 VMOVQ	%XMM0,(%RDX,%RDI,8)

  (3077) 0x2cd37b MOV	%R13,%RDI

  (3077) 0x2cd37e INC	%R12

  (3077) 0x2cd381 INC	%RSI

  (3077) 0x2cd384 CMP	%R15,%RSI

  (3077) 0x2cd387 JE	2cd0ca

  (3077) 0x2cd38d MOV	-0x48(%RBP),%RDX

  (3077) 0x2cd391 MOV	%RDI,%R13

  (3077) 0x2cd394 MOV	0x78(%RBP),%RDI

  (3077) 0x2cd398 MOV	(%RDX,%R12,8),%RDX

  (3077) 0x2cd39c CMP	%RDX,(%RDI)

  (3077) 0x2cd39f JG	2cd400

  (3077) 0x2cd3a1 MOV	0x80(%RBP),%RDI

  (3077) 0x2cd3a8 CMP	%RDX,(%RDI)

  (3077) 0x2cd3ab JL	2cd400

  (3077) 0x2cd3ad MOV	-0x68(%RBP),%RDI

  (3077) 0x2cd3b1 MOV	-0x58(%RBP),%R9

  (3077) 0x2cd3b5 MOV	(%R9,%RDI,8),%RDI

  (3077) 0x2cd3b9 CMP	%RCX,%RDI

  (3077) 0x2cd3bc JGE	2cd3ce

  (3077) 0x2cd3be XCHG	%AX,%AX

    (3079) 0x2cd3c0 CMP	%RDX,(%R10,%RDI,8)

    (3079) 0x2cd3c4 JE	2cd36c

    (3079) 0x2cd3c6 INC	%RDI

    (3079) 0x2cd3c9 CMP	%RDI,%RCX

    (3079) 0x2cd3cc JNE	2cd3c0

  (3077) 0x2cd3ce MOV	-0x30(%RBP),%RDI

  (3077) 0x2cd3d2 CMP	%RDI,-0x90(%RBP)

  (3077) 0x2cd3d9 JLE	2cd6a1

  (3077) 0x2cd3df MOV	%RDX,(%R10,%RDI,8)

  (3077) 0x2cd3e3 MOV	-0x78(%RBP),%RDX

  (3077) 0x2cd3e7 VMOVQ	(%R11,%R12,8),%XMM0

  (3077) 0x2cd3ed VMOVQ	%XMM0,(%RDX,%RDI,8)

  (3077) 0x2cd3f2 INC	%RDI

  (3077) 0x2cd3f5 MOV	%RDI,-0x30(%RBP)

  (3077) 0x2cd3f9 JMP	2cd37b

0x2cd3fe XCHG	%AX,%AX

  (3077) 0x2cd400 MOV	-0x68(%RBP),%RDI

  (3077) 0x2cd404 MOV	-0x50(%RBP),%R9

  (3077) 0x2cd408 MOV	(%R9,%RDI,8),%RDI

  (3077) 0x2cd40c CMP	%RAX,%RDI

  (3077) 0x2cd40f JGE	2cd42e

  (3077) 0x2cd411 NOPW	%CS:(%RAX,%RAX,1)

    (3078) 0x2cd420 CMP	%RDX,(%R8,%RDI,8)

    (3078) 0x2cd424 JE	2cd469

    (3078) 0x2cd426 INC	%RDI

    (3078) 0x2cd429 CMP	%RDI,%RAX

    (3078) 0x2cd42c JNE	2cd420

  (3077) 0x2cd42e CMP	%R13,-0x88(%RBP)

  (3077) 0x2cd435 JLE	2cd6da

  (3077) 0x2cd43b MOV	%RDX,(%R8,%R13,8)

  (3077) 0x2cd43f MOV	-0x70(%RBP),%RDX

  (3077) 0x2cd443 MOV	%R13,%RDI

  (3077) 0x2cd446 INC	%RDI

  (3077) 0x2cd449 VMOVQ	(%R11,%R12,8),%XMM0

  (3077) 0x2cd44f VMOVQ	%XMM0,(%RDX,%R13,8)

  (3077) 0x2cd455 INC	%R12

  (3077) 0x2cd458 INC	%RSI

  (3077) 0x2cd45b CMP	%R15,%RSI

  (3077) 0x2cd45e JNE	2cd38d

(3073) 0x2cd464 JMP	2cd0ca

  (3077) 0x2cd469 VMOVQ	(%R11,%R12,8),%XMM0

  (3077) 0x2cd46f MOV	-0x70(%RBP),%RDX

  (3077) 0x2cd473 JMP	2cd376

(3073) 0x2cd478 MOV	-0x40(%RBP),%RDX

(3073) 0x2cd47c XOR	%EDI,%EDI

(3073) 0x2cd47e MOV	%RDX,-0x40(%RBP)

(3073) 0x2cd482 TEST	%R15,%R15

(3073) 0x2cd485 JLE	2cd1d3

(3073) 0x2cd48b MOV	0x50(%RBP),%RAX

(3073) 0x2cd48f MOV	0x58(%RBP),%RCX

(3073) 0x2cd493 MOV	(%RAX),%RAX

(3073) 0x2cd496 MOV	(%RCX),%RCX

(3073) 0x2cd499 TEST	%R13,%R13

(3073) 0x2cd49c JLE	2cd529

(3073) 0x2cd4a2 MOV	%R13,%R11

(3073) 0x2cd4a5 XOR	%R10D,%R10D

(3073) 0x2cd4a8 XOR	%EDX,%EDX

(3073) 0x2cd4aa JMP	2cd4cf

0x2cd4ac NOPL	(%RAX)

  (3084) 0x2cd4b0 VMOVQ	(%RCX,%R12,8),%XMM0

  (3084) 0x2cd4b6 MOV	-0x30(%RBP),%RSI

  (3084) 0x2cd4ba VMOVQ	%XMM0,(%RSI,%R9,8)

  (3084) 0x2cd4c0 INC	%R12

  (3084) 0x2cd4c3 INC	%RDX

  (3084) 0x2cd4c6 CMP	%R15,%RDX

  (3084) 0x2cd4c9 JE	2cd588

  (3084) 0x2cd4cf MOV	(%RAX,%R12,8),%RSI

  (3084) 0x2cd4d3 XOR	%R9D,%R9D

  (3084) 0x2cd4d6 NOPW	%CS:(%RAX,%RAX,1)

    (3085) 0x2cd4e0 CMP	%RSI,(%RBX,%R9,8)

    (3085) 0x2cd4e4 JE	2cd4b0

    (3085) 0x2cd4e6 INC	%R9

    (3085) 0x2cd4e9 CMP	%R9,%R13

    (3085) 0x2cd4ec JNE	2cd4e0

  (3084) 0x2cd4ee CMP	%R11,-0x48(%RBP)

  (3084) 0x2cd4f2 JLE	2cd510

  (3084) 0x2cd4f4 MOV	%RSI,(%RBX,%R11,8)

  (3084) 0x2cd4f8 MOV	-0x30(%RBP),%RSI

  (3084) 0x2cd4fc VMOVQ	(%RCX,%R12,8),%XMM0

  (3084) 0x2cd502 VMOVQ	%XMM0,(%RSI,%R11,8)

  (3084) 0x2cd508 INC	%R11

  (3084) 0x2cd50b JMP	2cd4c0

0x2cd50d NOPL	(%RAX)

  (3084) 0x2cd510 MOV	%RSI,(%RDI,%R10,8)

  (3084) 0x2cd514 MOV	-0x40(%RBP),%RSI

  (3084) 0x2cd518 VMOVQ	(%RCX,%R12,8),%XMM0

  (3084) 0x2cd51e VMOVQ	%XMM0,(%RSI,%R10,8)

  (3084) 0x2cd524 INC	%R10

  (3084) 0x2cd527 JMP	2cd4c0

(3073) 0x2cd529 MOV	%R13,%R11

(3073) 0x2cd52c XOR	%R10D,%R10D

(3073) 0x2cd52f JMP	2cd55f

0x2cd531 NOPW	%CS:(%RAX,%RAX,1)

  (3083) 0x2cd540 MOV	%RDX,(%RDI,%R10,8)

  (3083) 0x2cd544 MOV	-0x40(%RBP),%RDX

  (3083) 0x2cd548 VMOVQ	(%RCX,%R12,8),%XMM0

  (3083) 0x2cd54e VMOVQ	%XMM0,(%RDX,%R10,8)

  (3083) 0x2cd554 INC	%R10

  (3083) 0x2cd557 INC	%R12

  (3083) 0x2cd55a DEC	%R15

  (3083) 0x2cd55d JE	2cd588

  (3083) 0x2cd55f MOV	(%RAX,%R12,8),%RDX

  (3083) 0x2cd563 CMP	%R11,-0x48(%RBP)

  (3083) 0x2cd567 JLE	2cd540

  (3083) 0x2cd569 MOV	%RDX,(%RBX,%R11,8)

  (3083) 0x2cd56d MOV	-0x30(%RBP),%RDX

  (3083) 0x2cd571 VMOVQ	(%RCX,%R12,8),%XMM0

  (3083) 0x2cd577 VMOVQ	%XMM0,(%RDX,%R11,8)

  (3083) 0x2cd57d INC	%R11

  (3083) 0x2cd580 INC	%R12

  (3083) 0x2cd583 DEC	%R15

  (3083) 0x2cd586 JNE	2cd55f

(3073) 0x2cd588 MOV	0x48(%RBP),%RAX

(3073) 0x2cd58c LEA	(%R11,%R10,1),%RBX

(3073) 0x2cd590 MOV	(%RAX),%RAX

(3073) 0x2cd593 MOV	%RBX,(%RAX,%R8,8)

(3073) 0x2cd597 TEST	%R10,%R10

(3073) 0x2cd59a JE	2cd62b

(3073) 0x2cd5a0 MOV	0x30(%RBP),%R15

(3073) 0x2cd5a4 MOV	%RDI,-0x58(%RBP)

(3073) 0x2cd5a8 LEA	(,%RBX,8),%RSI

(3073) 0x2cd5b0 MOV	%R11,-0x50(%RBP)

(3073) 0x2cd5b4 MOV	%R8,%R13

(3073) 0x2cd5b7 MOV	%R10,-0x48(%RBP)

(3073) 0x2cd5bb MOV	%RSI,-0x30(%RBP)

(3073) 0x2cd5bf MOV	(%R15),%RAX

(3073) 0x2cd5c2 MOV	(%RAX,%R8,8),%RDI

(3073) 0x2cd5c6 CALL	2de6a0 <hypre_ReAlloc>

(3073) 0x2cd5cb MOV	(%R15),%RCX

(3073) 0x2cd5ce MOV	0x38(%RBP),%R15

(3073) 0x2cd5d2 MOV	-0x30(%RBP),%RSI

(3073) 0x2cd5d6 MOV	%RAX,(%RCX,%R13,8)

(3073) 0x2cd5da MOV	(%R15),%RAX

(3073) 0x2cd5dd MOV	(%RAX,%R13,8),%RDI

(3073) 0x2cd5e1 CALL	2de6a0 <hypre_ReAlloc>

(3073) 0x2cd5e6 MOV	(%R15),%RCX

(3073) 0x2cd5e9 MOV	-0x48(%RBP),%R11

(3073) 0x2cd5ed MOV	%RAX,(%RCX,%R13,8)

(3073) 0x2cd5f1 MOV	0x40(%RBP),%RCX

(3073) 0x2cd5f5 MOV	(%RCX),%RAX

(3073) 0x2cd5f8 MOV	%RBX,(%RAX,%R13,8)

(3073) 0x2cd5fc TEST	%R11,%R11

(3073) 0x2cd5ff JLE	2cd63d

(3073) 0x2cd601 MOV	0x30(%RBP),%RAX

(3073) 0x2cd605 MOV	(%R15),%RCX

(3073) 0x2cd608 MOV	%R15,%RDX

(3073) 0x2cd60b MOV	(%RAX),%RAX

(3073) 0x2cd60e MOV	(%RCX,%R13,8),%RCX

(3073) 0x2cd612 MOV	(%RAX,%R13,8),%RAX

(3073) 0x2cd616 CMP	$0x4,%R11

(3073) 0x2cd61a JAE	2cd653

(3073) 0x2cd61c MOV	-0x38(%RBP),%R15

(3073) 0x2cd620 MOV	-0x58(%RBP),%RDI

(3073) 0x2cd624 XOR	%EDX,%EDX

(3073) 0x2cd626 JMP	2cd7fc

(3073) 0x2cd62b MOV	-0x38(%RBP),%R15

(3073) 0x2cd62f TEST	%RDI,%RDI

(3073) 0x2cd632 JNE	2cd83c

(3073) 0x2cd638 JMP	2cd853

(3073) 0x2cd63d MOV	-0x38(%RBP),%R15

(3073) 0x2cd641 MOV	-0x58(%RBP),%RDI

(3073) 0x2cd645 TEST	%RDI,%RDI

(3073) 0x2cd648 JNE	2cd83c

(3073) 0x2cd64e JMP	2cd853

(3073) 0x2cd653 MOV	-0x50(%RBP),%RSI

(3073) 0x2cd657 MOV	-0x58(%RBP),%RDI

(3073) 0x2cd65b MOV	-0x38(%RBP),%R15

(3073) 0x2cd65f LEA	(%RAX,%RSI,8),%RDX

(3073) 0x2cd663 SUB	%RDI,%RDX

(3073) 0x2cd666 CMP	$0x80,%RDX

(3073) 0x2cd66d JB	2cd723

(3073) 0x2cd673 LEA	(%RCX,%RSI,8),%RDX

(3073) 0x2cd677 SUB	-0x40(%RBP),%RDX

(3073) 0x2cd67b CMP	$0x80,%RDX

(3073) 0x2cd682 JB	2cd723

(3073) 0x2cd688 LEA	(,%RSI,8),%RSI

(3073) 0x2cd690 CMP	$0x10,%R11

(3073) 0x2cd694 JAE	2cd732

(3073) 0x2cd69a XOR	%EDX,%EDX

(3073) 0x2cd69c JMP	2cd7a8

(3073) 0x2cd6a1 MOV	$0xd70,%ESI

(3073) 0x2cd6a6 MOV	$0x1,%EDX

(3073) 0x2cd6ab LEA	-0xb553b(%RIP),%RDI

(3073) 0x2cd6b2 XOR	%ECX,%ECX

(3073) 0x2cd6b4 CALL	2e0c30 <hypre_error_handler>

(3073) 0x2cd6b9 MOV	0x98(%RBP),%RAX

(3073) 0x2cd6c0 MOV	0xa0(%RBP),%RCX

(3073) 0x2cd6c7 LOCK INCQ	(%RAX)

(3073) 0x2cd6cb CMPQ	$0,(%RCX)

(3073) 0x2cd6cf JE	2cd72a

(3073) 0x2cd6d1 LEA	-0xb7ce5(%RIP),%RDI

(3073) 0x2cd6d8 JMP	2cd711

(3073) 0x2cd6da MOV	$0xd4e,%ESI

(3073) 0x2cd6df MOV	$0x1,%EDX

(3073) 0x2cd6e4 LEA	-0xb5574(%RIP),%RDI

(3073) 0x2cd6eb XOR	%ECX,%ECX

(3073) 0x2cd6ed CALL	2e0c30 <hypre_error_handler>

(3073) 0x2cd6f2 MOV	0x98(%RBP),%RAX

(3073) 0x2cd6f9 MOV	0xa0(%RBP),%RCX

(3073) 0x2cd700 LOCK INCQ	(%RAX)

(3073) 0x2cd704 CMPQ	$0,(%RCX)

(3073) 0x2cd708 JE	2cd72a

(3073) 0x2cd70a LEA	-0xb919c(%RIP),%RDI

(3073) 0x2cd711 MOV	%RBX,%RSI

(3073) 0x2cd714 XOR	%EAX,%EAX

(3073) 0x2cd716 CALL	2de830 <hypre_printf>

(3073) 0x2cd71b MOV	%R13,%RDI

(3073) 0x2cd71e JMP	2cd0ca

(3073) 0x2cd723 XOR	%EDX,%EDX

(3073) 0x2cd725 JMP	2cd7fc

(3073) 0x2cd72a MOV	%R13,%RDI

(3073) 0x2cd72d JMP	2cd0ca

(3073) 0x2cd732 MOV	-0x40(%RBP),%R10

(3073) 0x2cd736 MOV	%R11,%RDX

(3073) 0x2cd739 LEA	0x40(%RAX,%RSI,1),%R11

(3073) 0x2cd73e LEA	0x40(%RCX,%RSI,1),%R8

(3073) 0x2cd743 AND	$-0x10,%RDX

(3073) 0x2cd747 XOR	%R9D,%R9D

(3073) 0x2cd74a NOPW	(%RAX,%RAX,1)

  (3081) 0x2cd750 VMOVUPS	(%RDI,%R9,8),%ZMM0

  (3081) 0x2cd757 VMOVUPS	0x40(%RDI,%R9,8),%ZMM1

  (3081) 0x2cd75f VMOVUPS	%ZMM0,-0x40(%R11,%R9,8)

  (3081) 0x2cd767 VMOVUPS	%ZMM1,(%R11,%R9,8)

  (3081) 0x2cd76e VMOVDQU64	(%R10,%R9,8),%ZMM0

  (3081) 0x2cd775 VMOVDQU64	0x40(%R10,%R9,8),%ZMM1

  (3081) 0x2cd77d VMOVDQU64	%ZMM0,-0x40(%R8,%R9,8)

  (3081) 0x2cd785 VMOVDQU64	%ZMM1,(%R8,%R9,8)

  (3081) 0x2cd78c ADD	$0x10,%R9

  (3081) 0x2cd790 CMP	%R9,%RDX

  (3081) 0x2cd793 JNE	2cd750

(3073) 0x2cd795 MOV	-0x48(%RBP),%R11

(3073) 0x2cd799 CMP	%RDX,%R11

(3073) 0x2cd79c JE	2cd83c

(3073) 0x2cd7a2 TEST	$0xc,%R11B

(3073) 0x2cd7a6 JE	2cd7f8

(3073) 0x2cd7a8 MOV	%RDX,%R10

(3073) 0x2cd7ab MOV	%R11,%RDX

(3073) 0x2cd7ae AND	$-0x4,%RDX

(3073) 0x2cd7b2 MOV	-0x40(%RBP),%R9

(3073) 0x2cd7b6 LEA	(%RAX,%RSI,1),%R8

(3073) 0x2cd7ba ADD	%RCX,%RSI

(3073) 0x2cd7bd ADD	%RDX,-0x50(%RBP)

(3073) 0x2cd7c1 NOPW	%CS:(%RAX,%RAX,1)

  (3082) 0x2cd7d0 VMOVUPS	(%RDI,%R10,8),%YMM0

  (3082) 0x2cd7d6 VMOVUPS	%YMM0,(%R8,%R10,8)

  (3082) 0x2cd7dc VMOVDQU	(%R9,%R10,8),%YMM0

  (3082) 0x2cd7e2 VMOVDQU	%YMM0,(%RSI,%R10,8)

  (3082) 0x2cd7e8 ADD	$0x4,%R10

  (3082) 0x2cd7ec CMP	%R10,%RDX

  (3082) 0x2cd7ef JNE	2cd7d0

(3073) 0x2cd7f1 CMP	%RDX,%R11

(3073) 0x2cd7f4 JNE	2cd7fc

(3073) 0x2cd7f6 JMP	2cd83c

(3073) 0x2cd7f8 ADD	%RDX,-0x50(%RBP)

(3073) 0x2cd7fc MOV	-0x50(%RBP),%RSI

(3073) 0x2cd800 MOV	-0x40(%RBP),%R8

(3073) 0x2cd804 SUB	%RDX,%R11

(3073) 0x2cd807 XOR	%R9D,%R9D

(3073) 0x2cd80a LEA	(%RCX,%RSI,8),%RCX

(3073) 0x2cd80e LEA	(%RAX,%RSI,8),%RAX

(3073) 0x2cd812 LEA	(%R8,%RDX,8),%RSI

(3073) 0x2cd816 LEA	(%RDI,%RDX,8),%RDX

(3073) 0x2cd81a NOPW	(%RAX,%RAX,1)

  (3080) 0x2cd820 MOV	(%RDX,%R9,8),%R8

  (3080) 0x2cd824 MOV	%R8,(%RAX,%R9,8)

  (3080) 0x2cd828 VMOVQ	(%RSI,%R9,8),%XMM0

  (3080) 0x2cd82e VMOVQ	%XMM0,(%RCX,%R9,8)

  (3080) 0x2cd834 INC	%R9

  (3080) 0x2cd837 CMP	%R9,%R11

  (3080) 0x2cd83a JNE	2cd820

(3073) 0x2cd83c VZEROUPPER

(3073) 0x2cd83f CALL	2de720 <hypre_Free>

(3073) 0x2cd844 MOV	-0x40(%RBP),%RDI

(3073) 0x2cd848 CALL	2de720 <hypre_Free>

(3073) 0x2cd84d XOR	%EAX,%EAX

(3073) 0x2cd84f MOV	%RAX,-0x40(%RBP)

(3073) 0x2cd853 MOV	-0x60(%RBP),%RDX

(3073) 0x2cd857 MOV	0x60(%RBP),%RSI

(3073) 0x2cd85b JMP	2cd0f4

0x2cd860 ADD	$0x68,%RSP

0x2cd864 POP	%RBX

0x2cd865 POP	%R12

0x2cd867 POP	%R13

0x2cd869 POP	%R14

0x2cd86b POP	%R15

0x2cd86d POP	%RBP

0x2cd86e RET

0x2cd86f CMP	$0x20,%RDI

0x2cd873 JAE	2cd880

0x2cd875 XOR	%R10D,%R10D

0x2cd878 XOR	%R8D,%R8D

0x2cd87b JMP	2cd922

0x2cd880 LEA	0xc0(%RSI,%RBX,8),%R9

0x2cd888 MOV	%RDI,%R8

0x2cd88b AND	$-0x20,%R8

0x2cd88f VPXOR	%XMM0,%XMM0,%XMM0

0x2cd893 VPXOR	%XMM1,%XMM1,%XMM1

0x2cd897 VPXOR	%XMM2,%XMM2,%XMM2

0x2cd89b VPXOR	%XMM3,%XMM3,%XMM3

0x2cd89f XOR	%R10D,%R10D

0x2cd8a2 NOPW	%CS:(%RAX,%RAX,1)

(3088) 0x2cd8b0 VPADDQ	-0xc0(%R9,%R10,8),%ZMM0,%ZMM0

(3088) 0x2cd8b8 VPADDQ	-0x80(%R9,%R10,8),%ZMM1,%ZMM1

(3088) 0x2cd8c0 VPADDQ	-0x40(%R9,%R10,8),%ZMM2,%ZMM2

(3088) 0x2cd8c8 VPADDQ	(%R9,%R10,8),%ZMM3,%ZMM3

(3088) 0x2cd8cf ADD	$0x20,%R10

(3088) 0x2cd8d3 CMP	%R10,%R8

(3088) 0x2cd8d6 JNE	2cd8b0

0x2cd8d8 VPADDQ	%ZMM0,%ZMM1,%ZMM0

0x2cd8de VPADDQ	%ZMM2,%ZMM3,%ZMM2

0x2cd8e4 VPADDQ	%ZMM0,%ZMM2,%ZMM0

0x2cd8ea VEXTRACTI64X4	$0x1,%ZMM0,%YMM1

0x2cd8f1 VPADDQ	%ZMM1,%ZMM0,%ZMM0

0x2cd8f7 VEXTRACTI128	$0x1,%YMM0,%XMM1

0x2cd8fd VPADDQ	%XMM1,%XMM0,%XMM0

0x2cd901 VPSHUFD	$0x4e,%XMM0,%XMM1

0x2cd906 VPADDQ	%XMM1,%XMM0,%XMM0

0x2cd90a VMOVQ	%XMM0,(%RCX)

0x2cd90e CMP	%R8,%RDI

0x2cd911 JE	2cd02f

0x2cd917 VMOVQ	%XMM0,%R10

0x2cd91c TEST	$0x1c,%DIL

0x2cd920 JE	2cd979

0x2cd922 SAL	$0x3,%RDX

0x2cd926 MOV	%RDI,%R11

0x2cd929 AND	$-0x4,%R11

0x2cd92d VMOVQ	%R10,%XMM0

0x2cd932 LEA	(%RDX,%RAX,8),%RAX

0x2cd936 LEA	(%RBX,%R11,1),%R9

0x2cd93a ADD	%RSI,%RAX

0x2cd93d NOPL	(%RAX)

(3089) 0x2cd940 VPADDQ	(%RAX,%R8,8),%YMM0,%YMM0

(3089) 0x2cd946 ADD	$0x4,%R8

(3089) 0x2cd94a CMP	%R8,%R11

(3089) 0x2cd94d JNE	2cd940

0x2cd94f VEXTRACTI128	$0x1,%YMM0,%XMM1

0x2cd955 VPADDQ	%XMM1,%XMM0,%XMM0

0x2cd959 VPSHUFD	$0x4e,%XMM0,%XMM1

0x2cd95e VPADDQ	%XMM1,%XMM0,%XMM0

0x2cd962 VMOVQ	%XMM0,(%RCX)

0x2cd966 CMP	%R11,%RDI

0x2cd969 JE	2cd02f

0x2cd96f VMOVQ	%XMM0,%R10

0x2cd974 JMP	2cd020

0x2cd979 ADD	%RBX,%R8

0x2cd97c MOV	%R8,%R9

0x2cd97f JMP	2cd020

0x2cd984 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3352,3359-3368,3376-3377,3383-3392,3399-3412,3422-3426,3433-3446,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 5.75 cycles (3.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.63 to 15.75 cycles (1.25x speedup).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	161
nb uops	157
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00
cycles	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	12.00
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

all	32%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	29%

Vector efficiency ratios

all	22%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

2% of peak load performance is reached (5.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2ccf50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 2e0200 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e0210 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																				scal (12.5%)
IDIV %R15	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ccfa5 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RAX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
JMP 2ccfb9 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x69>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%R8,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R8,%R14,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVL %R14,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2cd014 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xc4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd86f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%R14,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
LEA (%RSI,%RBX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd86f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1af5e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2e2d40 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 2cd077 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 2cd077 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1af32(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e2d40 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd0a4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x154>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 2cd0b3 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2cd860 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2cd860 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2cd100 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP $0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd880 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x930>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2cd922 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA 0xc0(%RSI,%RBX,8),%R9	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VPADDQ %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST $0x1c,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 2cd979 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 2cd020 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2cd020 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.63 to 5.75 cycles (3.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
29% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3257
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3256
unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3278
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3286

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259
LEA: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3274

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3259

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	161
nb uops	157
loop length	623
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.63 cycles
front end	19.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00
cycles	12.00	12.00	12.00	12.00	12.00	12.00	7.00	7.00	7.00	7.00	3.25	3.25	3.25	3.25	2.00	2.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

7.00-12.00

Cycles summary

Front-end	19.63
Dispatch	12.00
DIV/SQRT	7.00-12.00
Overall L1	19.63

Vectorization ratios

all	32%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	29%

Vector efficiency ratios

all	22%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	12%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.63 cycles. At this rate:

2% of peak load performance is reached (5.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.26 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 2ccf50

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CALL 2e0200 <hypre_NumActiveThreads>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e0210 <hypre_GetThreadNum>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R14),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CQTO																				scal (12.5%)
IDIV %R15	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2ccfa5 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x55>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x1(%RAX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RCX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
JMP 2ccfb9 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x69>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R14,%RSI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
IMUL %RAX,%RCX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RDX,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,(%R8,%R14,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R15,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x80(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14,%RAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
CMP %RDX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%R8,%R14,8),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
CMOVL %R14,%RDX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
SUB %RAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SUB %RDX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV (%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2cd014 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xc4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA (%RSI,%R15,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R9,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd86f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x8(%R8,%R14,8),%R8	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
LEA (%RSI,%RBX,8),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP %R8,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd86f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x91f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %RBX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1af5e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 2e2d40 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JNE 2cd077 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
CMPQ $0,(%R12)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	scal (12.5%)
JLE 2cd077 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x127>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1af32(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e2d40 <@plt_start@+0x80>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
TEST %R14,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd0a4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x154>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV -0x8(%RAX,%R14,8),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JL 2cd0b3 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x163>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
JMP 2cd860 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XOR %R12D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %R15,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JGE 2cd860 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x910>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x60(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JMP 2cd100 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP $0x20,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 2cd880 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x930>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2cd922 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9d2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
LEA 0xc0(%RSI,%RBX,8),%R9	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	2	0.50	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VPADDQ %ZMM0,%ZMM1,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM2,%ZMM3,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDQ %ZMM1,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (100.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R8,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
TEST $0x1c,%DIL	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 2cd979 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xa29>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SAL $0x3,%RDX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RDI,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x4,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVQ %R10,%XMM0	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RDX,%RAX,8),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%R11,1),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD %RSI,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSHUFD $0x4e,%XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDQ %XMM1,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVQ %XMM0,(%RCX)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CMP %R11,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 2cd02f <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xdf>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVQ %XMM0,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
JMP 2cd020 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
ADD %RBX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 2cd020 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0xd0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15–	1.07	0.56
▼Loop 3073 - IJMatrix_parcsr.c:3291-3484 - exec–	0.24	0.12
▼Loop 3077 - IJMatrix_parcsr.c:3383-3454 - exec–	0.82	0.41
○Loop 3078 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 3079 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
▼Loop 3084 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
○Loop 3085 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
○Loop 3081 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3074 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3075 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3076 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3080 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3082 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3083 - IJMatrix_parcsr.c:3316-3341 - exec	0.00	0.00
○Loop 3088 - IJMatrix_parcsr.c:3275-3275 - exec	0.01	0.00
○Loop 3089 - IJMatrix_parcsr.c:3275-3275 - exec	0.00	0.00
○Loop 3087 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
○Loop 3086 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00

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