OV - exec - Function hypre_BoomerAMGCreateS.omp

	Function: hypre_BoomerAMGCreateS.omp_outlined.2	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 1.12% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x2a30b0 PUSH	%RBP

0x2a30b1 MOV	%RSP,%RBP

0x2a30b4 PUSH	%R15

0x2a30b6 PUSH	%R14

0x2a30b8 PUSH	%R13

0x2a30ba PUSH	%R12

0x2a30bc PUSH	%RBX

0x2a30bd SUB	$0x98,%RSP

0x2a30c4 MOV	%RDX,-0xa0(%RBP)

0x2a30cb MOV	(%RDX),%RDX

0x2a30ce MOV	0x68(%RBP),%R14

0x2a30d2 MOV	0x38(%RBP),%R12

0x2a30d6 MOV	0x18(%RBP),%R13

0x2a30da LEA	-0x88(%RBP),%RDI

0x2a30e1 LEA	-0x58(%RBP),%RSI

0x2a30e5 MOV	%R9,%RBX

0x2a30e8 MOV	%R8,-0xc0(%RBP)

0x2a30ef MOV	%RCX,%R15

0x2a30f2 CALL	2e0220 <hypre_GetSimpleThreadPartition>

0x2a30f7 MOVQ	$0,-0x70(%RBP)

0x2a30ff MOVQ	$0,-0x68(%RBP)

0x2a3107 MOV	-0x88(%RBP),%R9

0x2a310e MOV	(%R15),%RDI

0x2a3111 CMP	%R9,-0x58(%RBP)

0x2a3115 JLE	2a38cc

0x2a311b MOV	0x50(%RBP),%R8

0x2a311f MOV	(%RBX),%RSI

0x2a3122 MOV	%RBX,-0x98(%RBP)

0x2a3129 MOV	0x40(%RBP),%R11

0x2a312d MOV	0x48(%RBP),%R10

0x2a3131 MOV	0x28(%RBP),%RAX

0x2a3135 MOV	0x30(%RBP),%RDX

0x2a3139 MOV	0x10(%RBP),%RCX

0x2a313d VMOVSD	-0x93dfd(%RIP),%XMM3

0x2a3145 VMOVDDUP	-0x93df5(%RIP),%XMM4

0x2a314d MOV	%R15,-0x90(%RBP)

0x2a3154 MOV	(%R13),%R15

0x2a3158 MOV	(%R14),%R13

0x2a315b VXORPD	%XMM2,%XMM2,%XMM2

0x2a315f XOR	%R14D,%R14D

0x2a3162 MOV	%RDI,-0xb8(%RBP)

0x2a3169 MOV	(%R8),%RBX

0x2a316c MOV	0x60(%RBP),%R8

0x2a3170 MOV	%RSI,-0xb0(%RBP)

0x2a3177 MOV	(%RCX),%RSI

0x2a317a MOV	(%R12),%RCX

0x2a317e MOV	(%RDX),%R12

0x2a3181 MOV	(%RAX),%RAX

0x2a3184 MOV	(%R10),%R10

0x2a3187 XOR	%EDX,%EDX

0x2a3189 MOV	%R13,-0x30(%RBP)

0x2a318d VMOVSD	(%R8),%XMM0

0x2a3192 MOV	0x70(%RBP),%R8

0x2a3196 MOV	%RAX,-0x60(%RBP)

0x2a319a MOV	%R12,-0xa8(%RBP)

0x2a31a1 MOV	%R10,-0x78(%RBP)

0x2a31a5 MOV	%RBX,-0x38(%RBP)

0x2a31a9 VMOVSD	(%R8),%XMM1

0x2a31ae MOV	(%R11),%R8

0x2a31b1 MOV	%R8,-0x80(%RBP)

0x2a31b5 MOV	0x58(%RBP),%R8

0x2a31b9 MOV	(%R8),%R11

0x2a31bc JMP	2a31d4

0x2a31be XCHG	%AX,%AX

(2239) 0x2a31c0 MOV	%RAX,%RDX

(2239) 0x2a31c3 MOV	-0xb8(%RBP),%RDI

(2239) 0x2a31ca CMP	%R9,-0x58(%RBP)

(2239) 0x2a31ce JLE	2a38d3

(2239) 0x2a31d4 MOV	-0xc0(%RBP),%RAX

(2239) 0x2a31db MOV	%R14,(%RDI,%R9,8)

(2239) 0x2a31df MOV	%R9,%R10

(2239) 0x2a31e2 CMPQ	$0,(%RAX)

(2239) 0x2a31e6 JE	2a31f3

(2239) 0x2a31e8 MOV	-0xb0(%RBP),%RAX

(2239) 0x2a31ef MOV	%RDX,(%RAX,%R10,8)

(2239) 0x2a31f3 MOV	(%R15,%R10,8),%RDI

(2239) 0x2a31f7 MOV	%RDX,-0x48(%RBP)

(2239) 0x2a31fb MOV	0x20(%RBP),%RDX

(2239) 0x2a31ff MOV	0x8(%R15,%R10,8),%R8

(2239) 0x2a3204 LEA	0x1(%R10),%R9

(2239) 0x2a3208 VMOVSD	(%RSI,%RDI,8),%XMM6

(2239) 0x2a320d CMPQ	$0x2,(%RDX)

(2239) 0x2a3211 LEA	0x1(%RDI),%RAX

(2239) 0x2a3215 JL	2a3280

(2239) 0x2a3217 MOV	%RDI,-0x50(%RBP)

(2239) 0x2a321b MOV	-0x60(%RBP),%RDI

(2239) 0x2a321f MOV	-0xa8(%RBP),%R12

(2239) 0x2a3226 VUCOMISD	%XMM6,%XMM2

(2239) 0x2a322a VXORPD	%XMM5,%XMM5,%XMM5

(2239) 0x2a322e VMOVAPD	%XMM6,%XMM7

(2239) 0x2a3232 JBE	2a32f0

(2239) 0x2a3238 CMP	%R8,%RAX

(2239) 0x2a323b JGE	2a3340

(2239) 0x2a3241 MOV	(%RDI,%R10,8),%R13

(2239) 0x2a3245 VMOVAPD	%XMM6,%XMM7

(2239) 0x2a3249 JMP	2a325c

0x2a324b NOPL	(%RAX,%RAX,1)

  (2257) 0x2a3250 INC	%RAX

  (2257) 0x2a3253 CMP	%RAX,%R8

  (2257) 0x2a3256 JE	2a3340

  (2257) 0x2a325c MOV	(%R12,%RAX,8),%RDX

  (2257) 0x2a3260 CMP	%R13,(%RDI,%RDX,8)

  (2257) 0x2a3264 JNE	2a3250

  (2257) 0x2a3266 VMOVSD	(%RSI,%RAX,8),%XMM8

  (2257) 0x2a326b VADDSD	%XMM7,%XMM8,%XMM7

  (2257) 0x2a326f VMAXSD	%XMM5,%XMM8,%XMM5

  (2257) 0x2a3273 JMP	2a3250

0x2a3275 NOPW	%CS:(%RAX,%RAX,1)

(2239) 0x2a3280 VUCOMISD	%XMM6,%XMM2

(2239) 0x2a3284 VXORPD	%XMM5,%XMM5,%XMM5

(2239) 0x2a3288 VMOVAPD	%XMM6,%XMM7

(2239) 0x2a328c JBE	2a33b0

(2239) 0x2a3292 CMP	%R8,%RAX

(2239) 0x2a3295 JGE	2a32b5

(2239) 0x2a3297 VMOVAPD	%XMM6,%XMM7

(2239) 0x2a329b NOPL	(%RAX,%RAX,1)

  (2253) 0x2a32a0 VMOVSD	(%RSI,%RAX,8),%XMM8

  (2253) 0x2a32a5 INC	%RAX

  (2253) 0x2a32a8 VADDSD	%XMM7,%XMM8,%XMM7

  (2253) 0x2a32ac VMAXSD	%XMM5,%XMM8,%XMM5

  (2253) 0x2a32b0 CMP	%RAX,%R8

  (2253) 0x2a32b3 JNE	2a32a0

(2239) 0x2a32b5 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a32b9 MOV	(%RCX,%R9,8),%RAX

(2239) 0x2a32bd CMP	%RAX,%R12

(2239) 0x2a32c0 JGE	2a347c

(2239) 0x2a32c6 MOV	%R12,%RDX

(2239) 0x2a32c9 NOPL	(%RAX)

  (2252) 0x2a32d0 VMOVSD	(%RBX,%RDX,8),%XMM8

  (2252) 0x2a32d5 INC	%RDX

  (2252) 0x2a32d8 VADDSD	%XMM7,%XMM8,%XMM7

  (2252) 0x2a32dc VMAXSD	%XMM5,%XMM8,%XMM5

  (2252) 0x2a32e0 CMP	%RDX,%RAX

  (2252) 0x2a32e3 JNE	2a32d0

(2239) 0x2a32e5 JMP	2a347c

0x2a32ea NOPW	(%RAX,%RAX,1)

(2239) 0x2a32f0 CMP	%R8,%RAX

(2239) 0x2a32f3 JGE	2a3410

(2239) 0x2a32f9 MOV	(%RDI,%R10,8),%R13

(2239) 0x2a32fd VMOVAPD	%XMM6,%XMM7

(2239) 0x2a3301 JMP	2a331c

0x2a3303 NOPW	%CS:(%RAX,%RAX,1)

  (2255) 0x2a3310 INC	%RAX

  (2255) 0x2a3313 CMP	%RAX,%R8

  (2255) 0x2a3316 JE	2a3410

  (2255) 0x2a331c MOV	(%R12,%RAX,8),%RDX

  (2255) 0x2a3320 CMP	%R13,(%RDI,%RDX,8)

  (2255) 0x2a3324 JNE	2a3310

  (2255) 0x2a3326 VMOVSD	(%RSI,%RAX,8),%XMM8

  (2255) 0x2a332b VADDSD	%XMM7,%XMM8,%XMM7

  (2255) 0x2a332f VMINSD	%XMM8,%XMM5,%XMM5

  (2255) 0x2a3334 JMP	2a3310

0x2a3336 NOPW	%CS:(%RAX,%RAX,1)

(2239) 0x2a3340 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a3344 MOV	(%RCX,%R9,8),%RAX

(2239) 0x2a3348 CMP	%RAX,%R12

(2239) 0x2a334b JGE	2a3470

(2239) 0x2a3351 MOV	-0x60(%RBP),%RDX

(2239) 0x2a3355 MOV	0x50(%RBP),%RBX

(2239) 0x2a3359 MOV	%R12,%R13

(2239) 0x2a335c MOV	(%RDX,%R10,8),%RDI

(2239) 0x2a3360 MOV	(%RBX),%RDX

(2239) 0x2a3363 MOV	%RDX,-0x40(%RBP)

(2239) 0x2a3367 JMP	2a337c

0x2a3369 NOPL	(%RAX)

  (2256) 0x2a3370 INC	%R13

  (2256) 0x2a3373 CMP	%R13,%RAX

  (2256) 0x2a3376 JE	2a3470

  (2256) 0x2a337c MOV	-0x78(%RBP),%RDX

  (2256) 0x2a3380 MOV	-0x80(%RBP),%RBX

  (2256) 0x2a3384 MOV	(%RDX,%R13,8),%RDX

  (2256) 0x2a3388 CMP	%RDI,(%RBX,%RDX,8)

  (2256) 0x2a338c JNE	2a3370

  (2256) 0x2a338e MOV	-0x40(%RBP),%RDX

  (2256) 0x2a3392 VMOVSD	(%RDX,%R13,8),%XMM8

  (2256) 0x2a3398 VADDSD	%XMM7,%XMM8,%XMM7

  (2256) 0x2a339c VMAXSD	%XMM5,%XMM8,%XMM5

  (2256) 0x2a33a0 JMP	2a3370

0x2a33a2 NOPW	%CS:(%RAX,%RAX,1)

(2239) 0x2a33b0 CMP	%R8,%RAX

(2239) 0x2a33b3 JGE	2a33d6

(2239) 0x2a33b5 VMOVAPD	%XMM6,%XMM7

(2239) 0x2a33b9 NOPL	(%RAX)

  (2251) 0x2a33c0 VMOVSD	(%RSI,%RAX,8),%XMM8

  (2251) 0x2a33c5 INC	%RAX

  (2251) 0x2a33c8 VADDSD	%XMM7,%XMM8,%XMM7

  (2251) 0x2a33cc VMINSD	%XMM8,%XMM5,%XMM5

  (2251) 0x2a33d1 CMP	%RAX,%R8

  (2251) 0x2a33d4 JNE	2a33c0

(2239) 0x2a33d6 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a33da MOV	(%RCX,%R9,8),%RAX

(2239) 0x2a33de CMP	%RAX,%R12

(2239) 0x2a33e1 JGE	2a347c

(2239) 0x2a33e7 MOV	%R12,%RDX

(2239) 0x2a33ea NOPW	(%RAX,%RAX,1)

  (2250) 0x2a33f0 VMOVSD	(%RBX,%RDX,8),%XMM8

  (2250) 0x2a33f5 INC	%RDX

  (2250) 0x2a33f8 VADDSD	%XMM7,%XMM8,%XMM7

  (2250) 0x2a33fc VMINSD	%XMM8,%XMM5,%XMM5

  (2250) 0x2a3401 CMP	%RDX,%RAX

  (2250) 0x2a3404 JNE	2a33f0

(2239) 0x2a3406 JMP	2a347c

0x2a3408 NOPL	(%RAX,%RAX,1)

(2239) 0x2a3410 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a3414 MOV	(%RCX,%R9,8),%RAX

(2239) 0x2a3418 CMP	%RAX,%R12

(2239) 0x2a341b JGE	2a3470

(2239) 0x2a341d MOV	-0x60(%RBP),%RDX

(2239) 0x2a3421 MOV	0x50(%RBP),%RBX

(2239) 0x2a3425 MOV	(%RDX,%R10,8),%RDI

(2239) 0x2a3429 MOV	(%RBX),%RDX

(2239) 0x2a342c MOV	%RDX,-0x40(%RBP)

(2239) 0x2a3430 MOV	%R12,%RDX

(2239) 0x2a3433 JMP	2a3448

0x2a3435 NOPW	%CS:(%RAX,%RAX,1)

  (2254) 0x2a3440 INC	%RDX

  (2254) 0x2a3443 CMP	%RDX,%RAX

  (2254) 0x2a3446 JE	2a3470

  (2254) 0x2a3448 MOV	-0x78(%RBP),%RBX

  (2254) 0x2a344c MOV	(%RBX,%RDX,8),%R13

  (2254) 0x2a3450 MOV	-0x80(%RBP),%RBX

  (2254) 0x2a3454 CMP	%RDI,(%RBX,%R13,8)

  (2254) 0x2a3458 JNE	2a3440

  (2254) 0x2a345a MOV	-0x40(%RBP),%RBX

  (2254) 0x2a345e VMOVSD	(%RBX,%RDX,8),%XMM8

  (2254) 0x2a3463 VADDSD	%XMM7,%XMM8,%XMM7

  (2254) 0x2a3467 VMINSD	%XMM8,%XMM5,%XMM5

  (2254) 0x2a346c JMP	2a3440

0x2a346e XCHG	%AX,%AX

(2239) 0x2a3470 MOV	-0x38(%RBP),%RBX

(2239) 0x2a3474 MOV	-0x30(%RBP),%R13

(2239) 0x2a3478 MOV	-0x50(%RBP),%RDI

(2239) 0x2a347c MOV	%RDI,%RDX

(2239) 0x2a347f NOT	%RDX

(2239) 0x2a3482 SUB	%R12,%RAX

(2239) 0x2a3485 ADD	-0x48(%RBP),%RAX

(2239) 0x2a3489 MOVQ	$-0x1,(%R11,%RDI,8)

(2239) 0x2a3491 ADD	%RDX,%R14

(2239) 0x2a3494 ADD	%R8,%R14

(2239) 0x2a3497 VUCOMISD	%XMM0,%XMM3

(2239) 0x2a349b JBE	2a3550

(2239) 0x2a34a1 VANDPD	%XMM4,%XMM6,%XMM8

(2239) 0x2a34a5 VANDPD	%XMM4,%XMM7,%XMM7

(2239) 0x2a34a9 VMULSD	%XMM0,%XMM8,%XMM8

(2239) 0x2a34ad VUCOMISD	%XMM8,%XMM7

(2239) 0x2a34b2 JBE	2a3550

(2239) 0x2a34b8 MOV	(%R15,%R10,8),%R8

(2239) 0x2a34bc MOV	(%R15,%R9,8),%RDI

(2239) 0x2a34c0 LEA	0x1(%R8),%RDX

(2239) 0x2a34c4 CMP	%RDI,%RDX

(2239) 0x2a34c7 JGE	2a34e8

(2239) 0x2a34c9 NOPL	(%RAX)

  (2249) 0x2a34d0 MOVQ	$-0x1,(%R11,%RDX,8)

  (2249) 0x2a34d8 INC	%RDX

  (2249) 0x2a34db MOV	(%R15,%R9,8),%RDI

  (2249) 0x2a34df CMP	%RDI,%RDX

  (2249) 0x2a34e2 JL	2a34d0

(2239) 0x2a34e4 MOV	(%R15,%R10,8),%R8

(2239) 0x2a34e8 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a34ec MOV	(%RCX,%R9,8),%RDX

(2239) 0x2a34f0 CMP	%RDX,%R12

(2239) 0x2a34f3 JGE	2a3519

(2239) 0x2a34f5 NOPW	%CS:(%RAX,%RAX,1)

  (2248) 0x2a3500 MOVQ	$-0x1,(%R13,%R12,8)

  (2248) 0x2a3509 INC	%R12

  (2248) 0x2a350c MOV	(%RCX,%R9,8),%RDX

  (2248) 0x2a3510 CMP	%RDX,%R12

  (2248) 0x2a3513 JL	2a3500

(2239) 0x2a3515 MOV	(%RCX,%R10,8),%R12

(2239) 0x2a3519 SUB	%RDI,%R14

(2239) 0x2a351c SUB	%RDX,%RAX

(2239) 0x2a351f LEA	0x1(%R14,%R8,1),%R14

(2239) 0x2a3524 ADD	%R12,%RAX

(2239) 0x2a3527 MOV	0x38(%RBP),%R12

(2239) 0x2a352b MOV	%RAX,%RDX

(2239) 0x2a352e MOV	-0xb8(%RBP),%RDI

(2239) 0x2a3535 CMP	-0x58(%RBP),%R9

(2239) 0x2a3539 JL	2a31d4

0x2a353f JMP	2a38d3

0x2a3544 NOPW	%CS:(%RAX,%RAX,1)

(2239) 0x2a3550 MOV	(%R15,%R10,8),%RDI

(2239) 0x2a3554 MOV	0x20(%RBP),%RDX

(2239) 0x2a3558 MOV	0x38(%RBP),%R12

(2239) 0x2a355c INC	%RDI

(2239) 0x2a355f CMPQ	$0x2,(%RDX)

(2239) 0x2a3563 MOV	(%R15,%R9,8),%RDX

(2239) 0x2a3567 JL	2a3670

(2239) 0x2a356d VUCOMISD	%XMM6,%XMM2

(2239) 0x2a3571 JBE	2a3718

(2239) 0x2a3577 CMP	%RDX,%RDI

(2239) 0x2a357a JGE	2a35de

(2239) 0x2a357c MOV	0x30(%RBP),%R12

(2239) 0x2a3580 MOV	0x28(%RBP),%RDX

(2239) 0x2a3584 VMULSD	%XMM5,%XMM1,%XMM6

(2239) 0x2a3588 MOV	(%RDX),%R8

(2239) 0x2a358b MOV	(%R12),%R12

(2239) 0x2a358f JMP	2a35b4

0x2a3591 NOPW	%CS:(%RAX,%RAX,1)

  (2247) 0x2a35a0 MOVQ	$-0x1,(%R11,%RDI,8)

  (2247) 0x2a35a8 DEC	%R14

  (2247) 0x2a35ab INC	%RDI

  (2247) 0x2a35ae CMP	%RDI,(%R15,%R9,8)

  (2247) 0x2a35b2 JLE	2a35de

  (2247) 0x2a35b4 VUCOMISD	(%RSI,%RDI,8),%XMM6

  (2247) 0x2a35b9 JAE	2a35a0

  (2247) 0x2a35bb MOV	(%R12,%RDI,8),%RDX

  (2247) 0x2a35bf MOV	(%R8,%R10,8),%R13

  (2247) 0x2a35c3 MOV	-0x38(%RBP),%RBX

  (2247) 0x2a35c7 CMP	(%R8,%RDX,8),%R13

  (2247) 0x2a35cb MOV	-0x30(%RBP),%R13

  (2247) 0x2a35cf JNE	2a35a0

  (2247) 0x2a35d1 MOV	%RDX,(%R11,%RDI,8)

  (2247) 0x2a35d5 INC	%RDI

  (2247) 0x2a35d8 CMP	%RDI,(%R15,%R9,8)

  (2247) 0x2a35dc JG	2a35b4

(2239) 0x2a35de MOV	(%RCX,%R10,8),%RDI

(2239) 0x2a35e2 CMP	%RDI,(%RCX,%R9,8)

(2239) 0x2a35e6 JLE	2a3527

(2239) 0x2a35ec MOV	0x68(%RBP),%RDX

(2239) 0x2a35f0 MOV	0x48(%RBP),%R12

(2239) 0x2a35f4 VMULSD	%XMM5,%XMM1,%XMM5

(2239) 0x2a35f8 MOV	(%RDX),%R8

(2239) 0x2a35fb MOV	0x28(%RBP),%RDX

(2239) 0x2a35ff MOV	(%R12),%R12

(2239) 0x2a3603 MOV	(%RDX),%RDX

(2239) 0x2a3606 MOV	%RDX,-0x40(%RBP)

(2239) 0x2a360a MOV	0x40(%RBP),%RDX

(2239) 0x2a360e MOV	(%RDX),%RDX

(2239) 0x2a3611 MOV	%RDX,-0x48(%RBP)

(2239) 0x2a3615 JMP	2a3638

0x2a3617 NOPW	(%RAX,%RAX,1)

  (2246) 0x2a3620 MOVQ	$-0x1,(%R8,%RDI,8)

  (2246) 0x2a3628 DEC	%RAX

  (2246) 0x2a362b INC	%RDI

  (2246) 0x2a362e CMP	%RDI,(%RCX,%R9,8)

  (2246) 0x2a3632 JLE	2a3527

  (2246) 0x2a3638 VUCOMISD	(%RBX,%RDI,8),%XMM5

  (2246) 0x2a363d JAE	2a3620

  (2246) 0x2a363f MOV	-0x40(%RBP),%RDX

  (2246) 0x2a3643 MOV	-0x48(%RBP),%RBX

  (2246) 0x2a3647 MOV	(%RDX,%R10,8),%R13

  (2246) 0x2a364b MOV	(%R12,%RDI,8),%RDX

  (2246) 0x2a364f CMP	(%RBX,%RDX,8),%R13

  (2246) 0x2a3653 MOV	-0x30(%RBP),%R13

  (2246) 0x2a3657 MOV	-0x38(%RBP),%RBX

  (2246) 0x2a365b JNE	2a3620

  (2246) 0x2a365d MOV	%RDX,(%R8,%RDI,8)

  (2246) 0x2a3661 INC	%RDI

  (2246) 0x2a3664 CMP	(%RCX,%R9,8),%RDI

  (2246) 0x2a3668 JL	2a3638

(2239) 0x2a366a JMP	2a3527

0x2a366f NOP

(2239) 0x2a3670 VUCOMISD	%XMM6,%XMM2

(2239) 0x2a3674 JBE	2a3813

(2239) 0x2a367a CMP	%RDX,%RDI

(2239) 0x2a367d JGE	2a36bf

(2239) 0x2a367f MOV	0x30(%RBP),%RDX

(2239) 0x2a3683 VMULSD	%XMM5,%XMM1,%XMM6

(2239) 0x2a3687 MOV	(%RDX),%R8

(2239) 0x2a368a JMP	2a36a1

0x2a368c NOPL	(%RAX)

  (2243) 0x2a3690 MOV	(%R8,%RDI,8),%RDX

  (2243) 0x2a3694 MOV	%RDX,(%R11,%RDI,8)

  (2243) 0x2a3698 INC	%RDI

  (2243) 0x2a369b CMP	%RDI,(%R15,%R9,8)

  (2243) 0x2a369f JLE	2a36bf

  (2243) 0x2a36a1 VUCOMISD	(%RSI,%RDI,8),%XMM6

  (2243) 0x2a36a6 JB	2a3690

  (2243) 0x2a36a8 DEC	%R14

  (2243) 0x2a36ab MOV	$-0x1,%RDX

  (2243) 0x2a36b2 MOV	%RDX,(%R11,%RDI,8)

  (2243) 0x2a36b6 INC	%RDI

  (2243) 0x2a36b9 CMP	%RDI,(%R15,%R9,8)

  (2243) 0x2a36bd JG	2a36a1

(2239) 0x2a36bf MOV	(%RCX,%R10,8),%RDI

(2239) 0x2a36c3 CMP	%RDI,(%RCX,%R9,8)

(2239) 0x2a36c7 JLE	2a31c0

(2239) 0x2a36cd MOV	0x68(%RBP),%RDX

(2239) 0x2a36d1 MOV	0x48(%RBP),%R8

(2239) 0x2a36d5 VMULSD	%XMM5,%XMM1,%XMM5

(2239) 0x2a36d9 MOV	(%RDX),%RDX

(2239) 0x2a36dc MOV	(%R8),%R8

(2239) 0x2a36df JMP	2a3705

0x2a36e1 NOPW	%CS:(%RAX,%RAX,1)

  (2242) 0x2a36f0 MOV	(%R8,%RDI,8),%R10

  (2242) 0x2a36f4 MOV	%R10,(%RDX,%RDI,8)

  (2242) 0x2a36f8 INC	%RDI

  (2242) 0x2a36fb CMP	%RDI,(%RCX,%R9,8)

  (2242) 0x2a36ff JLE	2a31c0

  (2242) 0x2a3705 VUCOMISD	(%RBX,%RDI,8),%XMM5

  (2242) 0x2a370a JB	2a36f0

  (2242) 0x2a370c DEC	%RAX

  (2242) 0x2a370f MOV	$-0x1,%R10

  (2242) 0x2a3716 JMP	2a36f4

(2239) 0x2a3718 CMP	%RDX,%RDI

(2239) 0x2a371b JGE	2a3782

(2239) 0x2a371d MOV	0x30(%RBP),%R12

(2239) 0x2a3721 MOV	0x28(%RBP),%RDX

(2239) 0x2a3725 VMULSD	%XMM5,%XMM1,%XMM6

(2239) 0x2a3729 MOV	(%RDX),%R8

(2239) 0x2a372c MOV	(%R12),%R12

(2239) 0x2a3730 JMP	2a3754

0x2a3732 NOPW	%CS:(%RAX,%RAX,1)

  (2245) 0x2a3740 MOVQ	$-0x1,(%R11,%RDI,8)

  (2245) 0x2a3748 DEC	%R14

  (2245) 0x2a374b INC	%RDI

  (2245) 0x2a374e CMP	%RDI,(%R15,%R9,8)

  (2245) 0x2a3752 JLE	2a3782

  (2245) 0x2a3754 VMOVSD	(%RSI,%RDI,8),%XMM7

  (2245) 0x2a3759 VUCOMISD	%XMM6,%XMM7

  (2245) 0x2a375d JAE	2a3740

  (2245) 0x2a375f MOV	(%R12,%RDI,8),%RDX

  (2245) 0x2a3763 MOV	(%R8,%R10,8),%R13

  (2245) 0x2a3767 MOV	-0x38(%RBP),%RBX

  (2245) 0x2a376b CMP	(%R8,%RDX,8),%R13

  (2245) 0x2a376f MOV	-0x30(%RBP),%R13

  (2245) 0x2a3773 JNE	2a3740

  (2245) 0x2a3775 MOV	%RDX,(%R11,%RDI,8)

  (2245) 0x2a3779 INC	%RDI

  (2245) 0x2a377c CMP	%RDI,(%R15,%R9,8)

  (2245) 0x2a3780 JG	2a3754

(2239) 0x2a3782 MOV	(%RCX,%R10,8),%RDI

(2239) 0x2a3786 CMP	%RDI,(%RCX,%R9,8)

(2239) 0x2a378a JLE	2a3527

(2239) 0x2a3790 MOV	0x68(%RBP),%RDX

(2239) 0x2a3794 MOV	0x48(%RBP),%R12

(2239) 0x2a3798 VMULSD	%XMM5,%XMM1,%XMM5

(2239) 0x2a379c MOV	(%RDX),%R8

(2239) 0x2a379f MOV	0x28(%RBP),%RDX

(2239) 0x2a37a3 MOV	(%R12),%R12

(2239) 0x2a37a7 MOV	(%RDX),%RDX

(2239) 0x2a37aa MOV	%RDX,-0x40(%RBP)

(2239) 0x2a37ae MOV	0x40(%RBP),%RDX

(2239) 0x2a37b2 MOV	(%RDX),%RDX

(2239) 0x2a37b5 MOV	%RDX,-0x48(%RBP)

(2239) 0x2a37b9 JMP	2a37d8

0x2a37bb NOPL	(%RAX,%RAX,1)

  (2244) 0x2a37c0 MOVQ	$-0x1,(%R8,%RDI,8)

  (2244) 0x2a37c8 DEC	%RAX

  (2244) 0x2a37cb INC	%RDI

  (2244) 0x2a37ce CMP	%RDI,(%RCX,%R9,8)

  (2244) 0x2a37d2 JLE	2a3527

  (2244) 0x2a37d8 VMOVSD	(%RBX,%RDI,8),%XMM6

  (2244) 0x2a37dd VUCOMISD	%XMM5,%XMM6

  (2244) 0x2a37e1 JAE	2a37c0

  (2244) 0x2a37e3 MOV	-0x40(%RBP),%RDX

  (2244) 0x2a37e7 MOV	-0x48(%RBP),%RBX

  (2244) 0x2a37eb MOV	(%RDX,%R10,8),%R13

  (2244) 0x2a37ef MOV	(%R12,%RDI,8),%RDX

  (2244) 0x2a37f3 CMP	(%RBX,%RDX,8),%R13

  (2244) 0x2a37f7 MOV	-0x30(%RBP),%R13

  (2244) 0x2a37fb MOV	-0x38(%RBP),%RBX

  (2244) 0x2a37ff JNE	2a37c0

  (2244) 0x2a3801 MOV	%RDX,(%R8,%RDI,8)

  (2244) 0x2a3805 INC	%RDI

  (2244) 0x2a3808 CMP	(%RCX,%R9,8),%RDI

  (2244) 0x2a380c JL	2a37d8

(2239) 0x2a380e JMP	2a3527

(2239) 0x2a3813 VMULSD	%XMM5,%XMM1,%XMM5

(2239) 0x2a3817 CMP	%RDX,%RDI

(2239) 0x2a381a JGE	2a3863

(2239) 0x2a381c MOV	0x30(%RBP),%RDX

(2239) 0x2a3820 MOV	(%RDX),%R8

(2239) 0x2a3823 JMP	2a3841

0x2a3825 NOPW	%CS:(%RAX,%RAX,1)

  (2241) 0x2a3830 MOV	(%R8,%RDI,8),%RDX

  (2241) 0x2a3834 MOV	%RDX,(%R11,%RDI,8)

  (2241) 0x2a3838 INC	%RDI

  (2241) 0x2a383b CMP	%RDI,(%R15,%R9,8)

  (2241) 0x2a383f JLE	2a3863

  (2241) 0x2a3841 VMOVSD	(%RSI,%RDI,8),%XMM6

  (2241) 0x2a3846 VUCOMISD	%XMM5,%XMM6

  (2241) 0x2a384a JB	2a3830

  (2241) 0x2a384c DEC	%R14

  (2241) 0x2a384f MOV	$-0x1,%RDX

  (2241) 0x2a3856 MOV	%RDX,(%R11,%RDI,8)

  (2241) 0x2a385a INC	%RDI

  (2241) 0x2a385d CMP	%RDI,(%R15,%R9,8)

  (2241) 0x2a3861 JG	2a3841

(2239) 0x2a3863 MOV	(%RCX,%R10,8),%RDI

(2239) 0x2a3867 CMP	%RDI,(%RCX,%R9,8)

(2239) 0x2a386b JLE	2a31c0

(2239) 0x2a3871 MOV	0x68(%RBP),%RDX

(2239) 0x2a3875 MOV	0x48(%RBP),%R10

(2239) 0x2a3879 MOV	(%RDX),%R8

(2239) 0x2a387c MOV	(%R10),%RDX

(2239) 0x2a387f JMP	2a38a5

0x2a3881 NOPW	%CS:(%RAX,%RAX,1)

  (2240) 0x2a3890 MOV	(%RDX,%RDI,8),%R10

  (2240) 0x2a3894 MOV	%R10,(%R8,%RDI,8)

  (2240) 0x2a3898 INC	%RDI

  (2240) 0x2a389b CMP	%RDI,(%RCX,%R9,8)

  (2240) 0x2a389f JLE	2a31c0

  (2240) 0x2a38a5 VMOVSD	(%RBX,%RDI,8),%XMM6

  (2240) 0x2a38aa VUCOMISD	%XMM5,%XMM6

  (2240) 0x2a38ae JB	2a3890

  (2240) 0x2a38b0 DEC	%RAX

  (2240) 0x2a38b3 MOV	$-0x1,%R10

  (2240) 0x2a38ba MOV	%R10,(%R8,%RDI,8)

  (2240) 0x2a38be INC	%RDI

  (2240) 0x2a38c1 CMP	(%RCX,%R9,8),%RDI

  (2240) 0x2a38c5 JL	2a38a5

(2239) 0x2a38c7 JMP	2a31c0

0x2a38cc XOR	%EDX,%EDX

0x2a38ce XOR	%R14D,%R14D

0x2a38d1 JMP	2a38e8

0x2a38d3 MOV	-0x90(%RBP),%R15

0x2a38da MOV	-0x98(%RBP),%RBX

0x2a38e1 MOV	0x18(%RBP),%R13

0x2a38e5 MOV	(%R15),%RDI

0x2a38e8 MOV	-0xa0(%RBP),%RAX

0x2a38ef MOV	%RDX,-0x68(%RBP)

0x2a38f3 MOV	%R14,-0x70(%RBP)

0x2a38f7 LEA	-0x68(%RBP),%RDX

0x2a38fb MOV	(%RAX),%RCX

0x2a38fe MOV	0x78(%RBP),%RAX

0x2a3902 LEA	(%RDI,%RCX,8),%RSI

0x2a3906 SAL	$0x3,%RCX

0x2a390a ADD	(%RBX),%RCX

0x2a390d MOV	(%RAX),%R8

0x2a3910 LEA	-0x70(%RBP),%RDI

0x2a3914 CALL	2e0e90 <hypre_prefix_sum_pair>

0x2a3919 MOV	-0x88(%RBP),%RSI

0x2a3920 CMP	%RSI,-0x58(%RBP)

0x2a3924 JLE	2a39f2

0x2a392a MOV	0x68(%RBP),%R11

0x2a392e MOV	0x58(%RBP),%RAX

0x2a3932 MOV	0x80(%RBP),%RCX

0x2a3939 MOV	(%R15),%RDX

0x2a393c MOV	(%RBX),%RDI

0x2a393f MOV	(%R13),%R8

0x2a3943 MOV	(%R12),%R10

0x2a3947 MOV	(%RAX),%R9

0x2a394a MOV	(%R11),%R11

0x2a394d JMP	2a395a

0x2a394f NOP

(2236) 0x2a3950 CMP	%RSI,-0x58(%RBP)

(2236) 0x2a3954 JLE	2a39f2

(2236) 0x2a395a MOV	-0x70(%RBP),%RAX

(2236) 0x2a395e MOV	%RSI,%RBX

(2236) 0x2a3961 ADD	%RAX,(%RDX,%RSI,8)

(2236) 0x2a3965 MOV	-0x68(%RBP),%RAX

(2236) 0x2a3969 ADD	%RAX,(%RDI,%RSI,8)

(2236) 0x2a396d MOV	(%R8,%RSI,8),%R14

(2236) 0x2a3971 MOV	0x8(%R8,%RSI,8),%R15

(2236) 0x2a3976 INC	%RSI

(2236) 0x2a3979 CMP	%R15,%R14

(2236) 0x2a397c JGE	2a39b0

(2236) 0x2a397e MOV	(%RDX,%RBX,8),%R12

(2236) 0x2a3982 MOV	(%RCX),%R13

(2236) 0x2a3985 JMP	2a3998

0x2a3987 NOPW	(%RAX,%RAX,1)

  (2238) 0x2a3990 INC	%R14

  (2238) 0x2a3993 CMP	%R15,%R14

  (2238) 0x2a3996 JGE	2a39b0

  (2238) 0x2a3998 MOV	(%R9,%R14,8),%RAX

  (2238) 0x2a399c TEST	%RAX,%RAX

  (2238) 0x2a399f JS	2a3990

  (2238) 0x2a39a1 MOV	%RAX,(%R13,%R12,8)

  (2238) 0x2a39a6 INC	%R12

  (2238) 0x2a39a9 MOV	(%R8,%RSI,8),%R15

  (2238) 0x2a39ad JMP	2a3990

0x2a39af NOP

(2236) 0x2a39b0 MOV	(%R10,%RBX,8),%R14

(2236) 0x2a39b4 MOV	(%R10,%RSI,8),%R15

(2236) 0x2a39b8 CMP	%R15,%R14

(2236) 0x2a39bb JGE	2a3950

(2236) 0x2a39bd MOV	0x88(%RBP),%RAX

(2236) 0x2a39c4 MOV	(%RDI,%RBX,8),%RBX

(2236) 0x2a39c8 MOV	(%RAX),%R12

(2236) 0x2a39cb JMP	2a39dc

0x2a39cd NOPL	(%RAX)

  (2237) 0x2a39d0 INC	%R14

  (2237) 0x2a39d3 CMP	%R15,%R14

  (2237) 0x2a39d6 JGE	2a3950

  (2237) 0x2a39dc MOV	(%R11,%R14,8),%RAX

  (2237) 0x2a39e0 TEST	%RAX,%RAX

  (2237) 0x2a39e3 JS	2a39d0

  (2237) 0x2a39e5 MOV	%RAX,(%R12,%RBX,8)

  (2237) 0x2a39e9 INC	%RBX

  (2237) 0x2a39ec MOV	(%R10,%RSI,8),%R15

  (2237) 0x2a39f0 JMP	2a39d0

0x2a39f2 ADD	$0x98,%RSP

0x2a39f9 POP	%RBX

0x2a39fa POP	%R12

0x2a39fc POP	%R13

0x2a39fe POP	%R14

0x2a3a00 POP	%R15

0x2a3a02 POP	%RBP

0x2a3a03 RET

0x2a3a04 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.25 to 1.13 cycles (15.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 17.25 to 1.47 cycles (11.74x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 17.25 to 13.25 cycles (1.30x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 408 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	130
nb uops	106
loop length	640
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	17.25	17.25	17.25	17.25	0.25	0.25	0.25	0.25	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	17.25	17.25	17.25	17.25	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.25
Dispatch	17.25
Overall L1	17.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.25 cycles. At this rate:

9% of peak load performance is reached (23.65 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2a30b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x88(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e0220 <hypre_GetSimpleThreadPartition>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV -0x88(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 2a38cc <hypre_BoomerAMGCreateS.omp_outlined.2+0x81c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x93dfd(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x93df5(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R13),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R12),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV (%R11),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2a31d4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2a38d3 <hypre_BoomerAMGCreateS.omp_outlined.2+0x823>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2a38e8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x838>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x90(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x68(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RCX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD (%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x70(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2e0e90 <hypre_prefix_sum_pair>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RSI,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 2a39f2 <hypre_BoomerAMGCreateS.omp_outlined.2+0x942>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2a395a <hypre_BoomerAMGCreateS.omp_outlined.2+0x8aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 17.25 to 13.25 cycles (1.30x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- use the 'restrict' C99 keyword

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_GetSimpleThreadPartition: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:250
hypre_prefix_sum_pair: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:480

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 408 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	130
nb uops	106
loop length	640
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	30

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.33	3.33	3.33	3.33	3.33	3.33	17.25	17.25	17.25	17.25	0.25	0.25	0.25	0.25	0.00	0.00
cycles	3.33	3.33	3.33	3.33	3.33	3.33	17.25	17.25	17.25	17.25	0.25	0.25	0.25	0.25	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.25
Dispatch	17.25
Overall L1	17.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	20%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.25 cycles. At this rate:

9% of peak load performance is reached (23.65 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2a30b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x88(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x58(%RBP),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R9,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,-0xc0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 2e0220 <hypre_GetSimpleThreadPartition>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV -0x88(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R9,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 2a38cc <hypre_BoomerAMGCreateS.omp_outlined.2+0x81c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x50(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %RBX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VMOVSD -0x93dfd(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x93df5(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R13),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %RDI,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RSI,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R12),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R8),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x70(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD (%R8),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.50	scal (12.5%)
MOV (%R11),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R8,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x58(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2a31d4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
JMP 2a38d3 <hypre_BoomerAMGCreateS.omp_outlined.2+0x823>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 2a38e8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x838>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
MOV -0x90(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
LEA -0x68(%RBP),%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RAX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA (%RDI,%RCX,8),%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
SAL $0x3,%RCX	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD (%RBX),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	N/A
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA -0x70(%RBP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
CALL 2e0e90 <hypre_prefix_sum_pair>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RSI,-0x58(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JLE 2a39f2 <hypre_BoomerAMGCreateS.omp_outlined.2+0x942>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x68(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R15),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R13),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%R12),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
JMP 2a395a <hypre_BoomerAMGCreateS.omp_outlined.2+0x8aa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS.omp_outlined.2–	1.12	0.59
▼Loop 2236 - par_strength.c:492-513 - exec–	0.07	0.04
○Loop 2238 - par_strength.c:498-503 - exec	0.32	0.16
○Loop 2237 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2239 - par_strength.c:253-472 - exec–	0.07	0.04
○Loop 2241 - par_strength.c:451-460 - exec	0.34	0.17
○Loop 2251 - par_strength.c:324-327 - exec	0.33	0.16
○Loop 2250 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2240 - par_strength.c:463-472 - exec	0.00	0.01
○Loop 2253 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2242 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 2249 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 2248 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 2247 - par_strength.c:363-373 - exec	0.00	0.00
○Loop 2244 - par_strength.c:405-415 - exec	0.00	0.00
○Loop 2252 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2245 - par_strength.c:392-402 - exec	0.00	0.00
○Loop 2256 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2243 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2257 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2254 - par_strength.c:297-302 - exec	0.00	0.00
○Loop 2246 - par_strength.c:376-386 - exec	0.00	0.00
○Loop 2255 - par_strength.c:289-294 - exec	0.00	0.00

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

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Vectorization ratios

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Cycles and memory resources usage

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ASM code