OV - exec - Function hypre_ParCSRRelaxThreads.omp

	Function: hypre_ParCSRRelaxThreads.omp_outlined.28	Module: exec	Source: ams.c:3662-3682	Coverage (incl. loops): 46.67% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x24d6f0 PUSH	%RBP

0x24d6f1 MOV	%RSP,%RBP

0x24d6f4 PUSH	%R15

0x24d6f6 PUSH	%R14

0x24d6f8 PUSH	%R13

0x24d6fa PUSH	%R12

0x24d6fc PUSH	%RBX

0x24d6fd SUB	$0x38,%RSP

0x24d701 MOV	(%RDX),%R13

0x24d704 MOV	%R9,-0x58(%RBP)

0x24d708 TEST	%R13,%R13

0x24d70b JLE	24d89e

0x24d711 MOV	(%RDI),%ESI

0x24d713 DEC	%R13

0x24d716 MOV	%R8,%R15

0x24d719 MOV	%RCX,%R12

0x24d71c MOVQ	$0,-0x40(%RBP)

0x24d724 MOVQ	$0x1,-0x60(%RBP)

0x24d72c MOVL	$0,-0x38(%RBP)

0x24d733 MOV	%R13,-0x30(%RBP)

0x24d737 SUB	$0x8,%RSP

0x24d73b LEA	-0x60(%RBP),%RAX

0x24d73f LEA	0x96cca(%RIP),%RDI

0x24d746 LEA	-0x38(%RBP),%RCX

0x24d74a LEA	-0x40(%RBP),%R8

0x24d74e LEA	-0x30(%RBP),%R9

0x24d752 MOV	%ESI,-0x34(%RBP)

0x24d755 MOV	$0x22,%EDX

0x24d75a PUSH	$0x1

0x24d75c PUSH	$0x1

0x24d75e PUSH	%RAX

0x24d75f CALL	2e2d50 <@plt_start@+0x90>

0x24d764 ADD	$0x20,%RSP

0x24d768 MOV	-0x30(%RBP),%RAX

0x24d76c CMP	%R13,%RAX

0x24d76f CMOVL	%RAX,%R13

0x24d773 MOV	-0x40(%RBP),%RAX

0x24d777 MOV	%R13,-0x30(%RBP)

0x24d77b CMP	%R13,%RAX

0x24d77e JG	24d88f

0x24d784 MOV	0x10(%RBP),%RCX

0x24d788 MOV	0x38(%RBP),%RDI

0x24d78c MOV	0x58(%RBP),%RBX

0x24d790 MOV	0x30(%RBP),%R11

0x24d794 MOV	0x28(%RBP),%R10

0x24d798 MOV	0x20(%RBP),%R9

0x24d79c MOV	0x18(%RBP),%R8

0x24d7a0 MOV	(%R15),%RSI

0x24d7a3 MOV	0x40(%RBP),%R14

0x24d7a7 MOV	(%R12),%RDX

0x24d7ab MOV	(%RCX),%RCX

0x24d7ae MOV	(%RDI),%R15

0x24d7b1 MOV	0x48(%RBP),%RDI

0x24d7b5 MOV	(%RBX),%RBX

0x24d7b8 MOV	(%R8),%R8

0x24d7bb MOV	(%R9),%R9

0x24d7be MOV	(%R10),%R10

0x24d7c1 MOV	(%R11),%R11

0x24d7c4 MOV	(%R14),%R12

0x24d7c7 MOV	%RCX,-0x50(%RBP)

0x24d7cb MOV	(%RDI),%RCX

0x24d7ce MOV	%RBX,-0x48(%RBP)

0x24d7d2 JMP	24d7ec

0x24d7d4 NOPW	%CS:(%RAX,%RAX,1)

(371) 0x24d7e0 INC	%RAX

(371) 0x24d7e3 CMP	%R13,%RAX

(371) 0x24d7e6 JG	24d88f

(371) 0x24d7ec MOV	(%RSI,%RAX,8),%RDI

(371) 0x24d7f0 MOV	-0x58(%RBP),%RBX

(371) 0x24d7f4 VMOVSD	(%RDX,%RDI,8),%XMM0

(371) 0x24d7f9 VUCOMISD	(%RBX),%XMM0

(371) 0x24d7fd JNE	24d801

(371) 0x24d7ff JNP	24d7e0

(371) 0x24d801 MOV	-0x50(%RBP),%RBX

(371) 0x24d805 MOV	0x8(%RSI,%RAX,8),%R14

(371) 0x24d80a VMOVSD	(%RBX,%RAX,8),%XMM0

(371) 0x24d80f CMP	%R14,%RDI

(371) 0x24d812 JGE	24d837

(371) 0x24d814 NOPW	%CS:(%RAX,%RAX,1)

  (373) 0x24d820 MOV	(%R8,%RDI,8),%RBX

  (373) 0x24d824 VMOVSD	(%RDX,%RDI,8),%XMM1

  (373) 0x24d829 INC	%RDI

  (373) 0x24d82c VFNMADD231SD	(%R9,%RBX,8),%XMM1,%XMM0

  (373) 0x24d832 CMP	%RDI,%R14

  (373) 0x24d835 JNE	24d820

(371) 0x24d837 MOV	(%R10,%RAX,8),%RDI

(371) 0x24d83b MOV	0x8(%R10,%RAX,8),%R14

(371) 0x24d840 CMP	%R14,%RDI

(371) 0x24d843 JGE	24d868

(371) 0x24d845 NOPW	%CS:(%RAX,%RAX,1)

  (372) 0x24d850 MOV	(%R11,%RDI,8),%RBX

  (372) 0x24d854 VMOVSD	(%R15,%RDI,8),%XMM1

  (372) 0x24d85a INC	%RDI

  (372) 0x24d85d VFNMADD231SD	(%R12,%RBX,8),%XMM1,%XMM0

  (372) 0x24d863 CMP	%RDI,%R14

  (372) 0x24d866 JNE	24d850

(371) 0x24d868 MOV	0x50(%RBP),%RDI

(371) 0x24d86c MOV	-0x48(%RBP),%RBX

(371) 0x24d870 VMULSD	(%RDI),%XMM0,%XMM0

(371) 0x24d874 VDIVSD	(%RBX,%RAX,8),%XMM0,%XMM0

(371) 0x24d879 VADDSD	(%RCX,%RAX,8),%XMM0,%XMM0

(371) 0x24d87e VMOVSD	%XMM0,(%RCX,%RAX,8)

(371) 0x24d883 INC	%RAX

(371) 0x24d886 CMP	%R13,%RAX

(371) 0x24d889 JLE	24d7ec

0x24d88f MOV	-0x34(%RBP),%ESI

0x24d892 LEA	0x96b8f(%RIP),%RDI

0x24d899 CALL	2e2d60 <@plt_start@+0xa0>

0x24d89e ADD	$0x38,%RSP

0x24d8a2 POP	%RBX

0x24d8a3 POP	%R12

0x24d8a5 POP	%R13

0x24d8a7 POP	%R14

0x24d8a9 POP	%R15

0x24d8ab POP	%RBP

0x24d8ac RET

0x24d8ad NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
►96.38+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.89+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:334	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:243	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.63 to 0.69 cycles (13.98x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3664

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	76
nb uops	77
loop length	273
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Dispatch	9.00
Overall L1	9.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.63 cycles. At this rate:

7% of peak load performance is reached (19.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.63 to 9.00 cycles (1.07x speedup).

ASM code

In the binary file, the address of the function is: 24d6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 24d89e <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x60(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x96cca(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2e2d50 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 24d88f <hypre_ParCSRRelaxThreads.omp_outlined.28+0x19f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 24d7ec <hypre_ParCSRRelaxThreads.omp_outlined.28+0xfc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x96b8f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CALL 2e2d60 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-989-6379/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3664

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	76
nb uops	77
loop length	273
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.63
Dispatch	9.00
Overall L1	9.63

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	9%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.63 cycles. At this rate:

7% of peak load performance is reached (19.95 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.65 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 24d6f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %R9,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
TEST %R13,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JLE 24d89e <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
DEC %R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVQ $0x1,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x60(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x96cca(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x40(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 2e2d50 <@plt_start@+0x90>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R13	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	1	0.33	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R13,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %R13,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JG 24d88f <hypre_ParCSRRelaxThreads.omp_outlined.28+0x19f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x58(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R15),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x40(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R12),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RCX),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RDI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R10),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RBX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
JMP 24d7ec <hypre_ParCSRRelaxThreads.omp_outlined.28+0xfc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
LEA 0x96b8f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CALL 2e2d60 <@plt_start@+0xa0>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads.omp_outlined.28–	46.67	24.59
▼Loop 371 - ams.c:3664-3682 - exec–	15.05	7.45
○Loop 373 - ams.c:3672-3675 - exec	31.52	15.60
○Loop 372 - ams.c:3677-3680 - exec	0.10	0.05

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code