Loop Id: 5895 | Module: exec | Source: csr_matvec.c:178-196 [...] | Coverage: 0.01% |
---|
Loop Id: 5895 | Module: exec | Source: csr_matvec.c:178-196 [...] | Coverage: 0.01% |
---|
0x58f0fe MOV -0x70(%RBP),%RAX |
0x58f102 ADDSD (%RAX,%RSI,8),%XMM0 |
0x58f107 MOVSD %XMM0,(%RAX,%RSI,8) |
0x58f10c LEA 0x1(%RDX),%RAX |
0x58f110 CMP -0x60(%RBP),%RDX |
0x58f114 MOV %RAX,%RDX |
0x58f117 JE 58f03b |
0x58f11d LEA (%R11,%RDX,1),%RAX |
0x58f121 MOV (%R15,%RAX,8),%RSI |
0x58f125 MOV (%R10,%RSI,8),%RDI |
0x58f129 MOV 0x8(%R10,%RSI,8),%RAX |
0x58f12e XORPD %XMM0,%XMM0 |
0x58f132 SUB %RDI,%RAX |
0x58f135 JLE 58f0fe |
0x58f137 CMP $0x8,%RAX |
0x58f13b JB 58f1f3 |
0x58f141 MOV %RAX,%R8 |
0x58f144 SHR $0x3,%R8 |
0x58f148 LEA (,%RDI,8),%R9 |
(5896) 0x58f150 MOV 0x10(%R14,%R9,1),%RCX |
(5896) 0x58f155 MOVSD (%RBX,%RCX,8),%XMM1 |
(5896) 0x58f15a MOV 0x18(%R14,%R9,1),%RCX |
(5896) 0x58f15f MOVHPD (%RBX,%RCX,8),%XMM1 |
(5896) 0x58f164 MOV 0x30(%R14,%R9,1),%RCX |
(5896) 0x58f169 MOVSD (%RBX,%RCX,8),%XMM2 |
(5896) 0x58f16e MOV 0x38(%R14,%R9,1),%RCX |
(5896) 0x58f173 MOVHPD (%RBX,%RCX,8),%XMM2 |
(5896) 0x58f178 MOV (%R14,%R9,1),%RCX |
(5896) 0x58f17c MOVSD (%RBX,%RCX,8),%XMM3 |
(5896) 0x58f181 MOV 0x8(%R14,%R9,1),%RCX |
(5896) 0x58f186 MOVHPD (%RBX,%RCX,8),%XMM3 |
(5896) 0x58f18b MOV 0x20(%R14,%R9,1),%RCX |
(5896) 0x58f190 MOVSD (%RBX,%RCX,8),%XMM4 |
(5896) 0x58f195 MOV 0x28(%R14,%R9,1),%RCX |
(5896) 0x58f19a MOVHPD (%RBX,%RCX,8),%XMM4 |
(5896) 0x58f19f MOVUPD 0x10(%R12,%R9,1),%XMM5 |
(5896) 0x58f1a6 MULPD %XMM5,%XMM1 |
(5896) 0x58f1aa MOVUPD 0x30(%R12,%R9,1),%XMM5 |
(5896) 0x58f1b1 MULPD %XMM5,%XMM2 |
(5896) 0x58f1b5 MOVUPD (%R12,%R9,1),%XMM5 |
(5896) 0x58f1bb ADDPD %XMM1,%XMM2 |
(5896) 0x58f1bf MOVUPD 0x20(%R12,%R9,1),%XMM1 |
(5896) 0x58f1c6 MULPD %XMM5,%XMM3 |
(5896) 0x58f1ca MULPD %XMM1,%XMM4 |
(5896) 0x58f1ce ADDPD %XMM3,%XMM4 |
(5896) 0x58f1d2 ADDPD %XMM2,%XMM4 |
(5896) 0x58f1d6 MOVAPD %XMM4,%XMM1 |
(5896) 0x58f1da UNPCKHPD %XMM4,%XMM1 |
(5896) 0x58f1de ADDSD %XMM4,%XMM1 |
(5896) 0x58f1e2 ADDSD %XMM1,%XMM0 |
(5896) 0x58f1e6 ADD $0x40,%R9 |
(5896) 0x58f1ea DEC %R8 |
(5896) 0x58f1ed JNE 58f150 |
0x58f1f3 MOV %EAX,%ECX |
0x58f1f5 AND $0x7,%ECX |
0x58f1f8 DEC %RCX |
0x58f1fb CMP $0x6,%RCX |
0x58f1ff JA 58f0fe |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 178 - 196 |
-------------------------------------------------------------------------------- |
178: #pragma omp parallel for private(i,j,jj,m,tempx) HYPRE_SMP_SCHEDULE |
179: #endif |
180: |
181: for (i = 0; i < num_rownnz; i++) |
182: { |
183: m = A_rownnz[i]; |
[...] |
194: for (jj = A_i[m]; jj < A_i[m+1]; jj++) |
195: tempx += A_data[jj] * x_data[A_j[jj]]; |
196: y_data[m] += tempx; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.92 |
CQA speedup if FP arith vectorized | 2.88 |
CQA speedup if fully vectorized | 7.08 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.39 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source | csr_matvec.c:178-178,csr_matvec.c:181-183,csr_matvec.c:194-196 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.83 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.33 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 3.83 |
DIV/SQRT cycles | 2.75 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.00 |
P4 cycles | 2.33 |
P5 cycles | 2.33 |
P6 cycles | 2.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 24.00 |
Nb uops | 23.00 |
Nb loads | 6.00 |
Nb stores | 1.00 |
Nb stack references | 2.00 |
FLOP/cycle | 0.26 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.61 |
Bytes prefetched | 0.00 |
Bytes loaded | 48.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 14.29 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 20.00 |
Vector-efficiency ratio all | 14.29 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.92 |
CQA speedup if FP arith vectorized | 2.88 |
CQA speedup if fully vectorized | 7.08 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.39 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source | csr_matvec.c:178-178,csr_matvec.c:181-183,csr_matvec.c:194-196 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.83 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 1.33 |
CQA cycles if fully vectorized | 0.54 |
Front-end cycles | 3.83 |
DIV/SQRT cycles | 2.75 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.00 |
P4 cycles | 2.33 |
P5 cycles | 2.33 |
P6 cycles | 2.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 24.00 |
Nb uops | 23.00 |
Nb loads | 6.00 |
Nb stores | 1.00 |
Nb stack references | 2.00 |
FLOP/cycle | 0.26 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 14.61 |
Bytes prefetched | 0.00 |
Bytes loaded | 48.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 14.29 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 20.00 |
Vector-efficiency ratio all | 14.29 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 15.00 |
Path / |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source file and lines | csr_matvec.c:178-196 |
Module | exec |
nb instructions | 24 |
nb uops | 23 |
loop length | 100 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
micro-operation queue | 3.83 cycles |
front end | 3.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 | 0.50 | 0.50 | 0.50 | 0.50 |
cycles | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 | 0.50 | 0.50 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.83 |
Dispatch | 2.75 |
Overall L1 | 3.83 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 33% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 20% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 16% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADDSD (%RAX,%RSI,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
MOVSD %XMM0,(%RAX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%RDX),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0x60(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 58f03b <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xbb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%R11,%RDX,1),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%R15,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R10,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%R10,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XORPD %XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 58f0fe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 58f1f3 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x273> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R8 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 58f0fe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted.19 |
Source file and lines | csr_matvec.c:178-196 |
Module | exec |
nb instructions | 24 |
nb uops | 23 |
loop length | 100 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 2 |
micro-operation queue | 3.83 cycles |
front end | 3.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 | 0.50 | 0.50 | 0.50 | 0.50 |
cycles | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 | 0.50 | 0.50 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.83 |
Dispatch | 2.75 |
Overall L1 | 3.83 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 33% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 14% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 20% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 16% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 15% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x70(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADDSD (%RAX,%RSI,8),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
MOVSD %XMM0,(%RAX,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%RDX),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0x60(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 58f03b <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0xbb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%R11,%RDX,1),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%R15,%RAX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%R10,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%R10,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XORPD %XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 58f0fe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 58f1f3 <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x273> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R8 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %EAX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%ECX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%RCX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 58f0fe <hypre_CSRMatrixMatvecOutOfPlace.extracted.19+0x17e> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |