Loop Id: 680 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.02% |
---|
Loop Id: 680 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.02% |
---|
0x2ab6b0 MOV %R14,%R15 |
0x2ab6b3 MOV %R13,%R12 |
0x2ab6b6 CMP %R9,-0x98(%RBP) |
0x2ab6bd JLE 2abaa2 |
0x2ab6c3 MOV -0x100(%RBP),%RAX |
0x2ab6ca MOV %R9,%RDX |
0x2ab6cd CMPQ $0,(%RAX) |
0x2ab6d1 JE 2ab6ff |
0x2ab6d3 MOV -0xf8(%RBP),%RAX |
0x2ab6da MOV %R12,(%RDI,%RDX,8) |
0x2ab6de MOV -0xe8(%RBP),%RCX |
0x2ab6e5 LEA 0x1(%R12),%R13 |
0x2ab6ea VMOVSD (%RAX),%XMM0 |
0x2ab6ee MOV -0xf0(%RBP),%RAX |
0x2ab6f5 VMOVSD %XMM0,(%RAX,%R12,8) |
0x2ab6fb MOV %RDX,(%RCX,%R12,8) |
0x2ab6ff MOV -0x108(%RBP),%RAX |
0x2ab706 CMPQ $0,(%RAX) |
0x2ab70a JE 2ab8d0 |
0x2ab710 MOV -0xb0(%RBP),%RCX |
0x2ab717 LEA 0x1(%RDX),%R9 |
0x2ab71b MOV (%RCX,%RDX,8),%RAX |
0x2ab71f CMP %RAX,0x8(%RCX,%RDX,8) |
0x2ab724 JLE 2ab8d4 |
0x2ab72a MOV %R9,-0x50(%RBP) |
0x2ab72e MOV %R15,%R14 |
0x2ab731 MOV -0xb8(%RBP),%RCX |
0x2ab738 MOV (%RCX),%RCX |
0x2ab73b MOV %RCX,-0x40(%RBP) |
0x2ab73f MOV -0xc0(%RBP),%RCX |
0x2ab746 MOV (%RCX),%RCX |
0x2ab749 MOV %RCX,-0x48(%RBP) |
0x2ab74d MOV %RDX,-0x38(%RBP) |
0x2ab751 JMP 2ab779 |
(684) 0x2ab760 MOV -0xb0(%RBP),%RCX |
(684) 0x2ab767 MOV -0x38(%RBP),%RDX |
(684) 0x2ab76b INC %RAX |
(684) 0x2ab76e CMP %RAX,0x8(%RCX,%RDX,8) |
(684) 0x2ab773 JLE 2ab8e0 |
(684) 0x2ab779 MOV -0x138(%RBP),%RCX |
(684) 0x2ab780 MOV -0x130(%RBP),%RSI |
(684) 0x2ab787 MOV -0x68(%RBP),%RDX |
(684) 0x2ab78b MOV (%RCX,%RAX,8),%R9 |
(684) 0x2ab78f VMOVSD (%RSI,%RAX,8),%XMM0 |
(684) 0x2ab794 MOV (%RDX,%R9,8),%R10 |
(684) 0x2ab798 MOV 0x8(%RDX,%R9,8),%RCX |
(684) 0x2ab79d CMP %RCX,%R10 |
(684) 0x2ab7a0 JGE 2ab830 |
(684) 0x2ab7a6 MOV -0xa0(%RBP),%R11 |
(684) 0x2ab7ad MOV -0x110(%RBP),%RDX |
(684) 0x2ab7b4 MOV -0xa8(%RBP),%R8 |
(684) 0x2ab7bb MOV (%RDX),%RSI |
(684) 0x2ab7be MOV (%R11),%R11 |
(684) 0x2ab7c1 MOV (%R8),%RDX |
(684) 0x2ab7c4 MOV %RDX,-0x30(%RBP) |
(684) 0x2ab7c8 JMP 2ab7ea |
(686) 0x2ab7d0 VMOVSD (%RSI,%R10,8),%XMM1 |
(686) 0x2ab7d6 VFMADD213SD (%R11,%R8,8),%XMM0,%XMM1 |
(686) 0x2ab7dc VMOVSD %XMM1,(%R11,%R8,8) |
(686) 0x2ab7e2 INC %R10 |
(686) 0x2ab7e5 CMP %RCX,%R10 |
(686) 0x2ab7e8 JGE 2ab830 |
(686) 0x2ab7ea MOV -0x40(%RBP),%RDX |
(686) 0x2ab7ee MOV (%RDX,%R10,8),%RDX |
(686) 0x2ab7f2 ADD (%RBX),%RDX |
(686) 0x2ab7f5 MOV (%RDI,%RDX,8),%R8 |
(686) 0x2ab7f9 CMP %R15,%R8 |
(686) 0x2ab7fc JGE 2ab7d0 |
(686) 0x2ab7fe MOV %R14,(%RDI,%RDX,8) |
(686) 0x2ab802 MOV -0x30(%RBP),%RCX |
(686) 0x2ab806 VMULSD (%RSI,%R10,8),%XMM0,%XMM1 |
(686) 0x2ab80c VMOVSD %XMM1,(%R11,%R14,8) |
(686) 0x2ab812 SUB (%RBX),%RDX |
(686) 0x2ab815 MOV %RDX,(%RCX,%R14,8) |
(686) 0x2ab819 MOV -0x68(%RBP),%RDX |
(686) 0x2ab81d INC %R14 |
(686) 0x2ab820 MOV 0x8(%RDX,%R9,8),%RCX |
(686) 0x2ab825 JMP 2ab7e2 |
(684) 0x2ab830 MOV -0x60(%RBP),%RCX |
(684) 0x2ab834 MOV (%RCX,%R9,8),%RSI |
(684) 0x2ab838 MOV 0x8(%RCX,%R9,8),%R11 |
(684) 0x2ab83d CMP %R11,%RSI |
(684) 0x2ab840 JGE 2ab760 |
(684) 0x2ab846 MOV -0x80(%RBP),%R10 |
(684) 0x2ab84a MOV -0x118(%RBP),%RCX |
(684) 0x2ab851 MOV -0x88(%RBP),%RDX |
(684) 0x2ab858 MOV (%RCX),%R8 |
(684) 0x2ab85b MOV (%R10),%R10 |
(684) 0x2ab85e MOV (%RDX),%RCX |
(684) 0x2ab861 MOV %RCX,-0x30(%RBP) |
(684) 0x2ab865 JMP 2ab88e |
(685) 0x2ab870 VMOVSD (%R8,%RSI,8),%XMM1 |
(685) 0x2ab876 VFMADD213SD (%R10,%RCX,8),%XMM0,%XMM1 |
(685) 0x2ab87c VMOVSD %XMM1,(%R10,%RCX,8) |
(685) 0x2ab882 INC %RSI |
(685) 0x2ab885 CMP %R11,%RSI |
(685) 0x2ab888 JGE 2ab760 |
(685) 0x2ab88e MOV -0x48(%RBP),%RCX |
(685) 0x2ab892 MOV (%RCX,%RSI,8),%RDX |
(685) 0x2ab896 MOV (%RDI,%RDX,8),%RCX |
(685) 0x2ab89a CMP %R12,%RCX |
(685) 0x2ab89d JGE 2ab870 |
(685) 0x2ab89f MOV %R13,(%RDI,%RDX,8) |
(685) 0x2ab8a3 MOV -0x30(%RBP),%RCX |
(685) 0x2ab8a7 VMULSD (%R8,%RSI,8),%XMM0,%XMM1 |
(685) 0x2ab8ad VMOVSD %XMM1,(%R10,%R13,8) |
(685) 0x2ab8b3 MOV %RDX,(%RCX,%R13,8) |
(685) 0x2ab8b7 MOV -0x60(%RBP),%RDX |
(685) 0x2ab8bb INC %R13 |
(685) 0x2ab8be MOV 0x8(%RDX,%R9,8),%R11 |
(685) 0x2ab8c3 JMP 2ab882 |
0x2ab8d0 LEA 0x1(%RDX),%R9 |
0x2ab8d4 MOV %R15,%R14 |
0x2ab8d7 JMP 2ab8e4 |
0x2ab8e0 MOV -0x50(%RBP),%R9 |
0x2ab8e4 MOV -0x58(%RBP),%RAX |
0x2ab8e8 MOV (%RAX,%RDX,8),%R8 |
0x2ab8ec CMP %R8,(%RAX,%R9,8) |
0x2ab8f0 JLE 2ab6b0 |
0x2ab8f6 MOV -0xc8(%RBP),%RAX |
0x2ab8fd MOV (%RAX),%RAX |
0x2ab900 MOV %RAX,-0x40(%RBP) |
0x2ab904 MOV -0xd0(%RBP),%RAX |
0x2ab90b MOV (%RAX),%RAX |
0x2ab90e MOV %RAX,-0x70(%RBP) |
0x2ab912 MOV -0xd8(%RBP),%RAX |
0x2ab919 MOV (%RAX),%RAX |
0x2ab91c MOV %RAX,-0x48(%RBP) |
0x2ab920 MOV -0xe0(%RBP),%RAX |
0x2ab927 MOV (%RAX),%RAX |
0x2ab92a MOV %RAX,-0x30(%RBP) |
0x2ab92e MOV %R9,-0x50(%RBP) |
0x2ab932 JMP 2ab955 |
(681) 0x2ab940 MOV -0x50(%RBP),%R9 |
(681) 0x2ab944 MOV -0x58(%RBP),%RAX |
(681) 0x2ab948 INC %R8 |
(681) 0x2ab94b CMP %R8,(%RAX,%R9,8) |
(681) 0x2ab94f JLE 2ab6b0 |
(681) 0x2ab955 MOV -0x90(%RBP),%RAX |
(681) 0x2ab95c MOV -0x140(%RBP),%RDX |
(681) 0x2ab963 MOV -0x78(%RBP),%RCX |
(681) 0x2ab967 MOV (%RAX,%R8,8),%R9 |
(681) 0x2ab96b VMOVSD (%RDX,%R8,8),%XMM0 |
(681) 0x2ab971 MOV (%RCX,%R9,8),%RSI |
(681) 0x2ab975 MOV 0x8(%RCX,%R9,8),%RCX |
(681) 0x2ab97a CMP %RCX,%RSI |
(681) 0x2ab97d JGE 2ab9f0 |
(681) 0x2ab97f MOV -0x80(%RBP),%R10 |
(681) 0x2ab983 MOV -0x128(%RBP),%RAX |
(681) 0x2ab98a MOV -0x88(%RBP),%R11 |
(681) 0x2ab991 MOV (%RAX),%RDX |
(681) 0x2ab994 MOV (%R10),%R10 |
(681) 0x2ab997 MOV (%R11),%RAX |
(681) 0x2ab99a MOV %RAX,-0x38(%RBP) |
(681) 0x2ab99e JMP 2ab9b9 |
(683) 0x2ab9a0 VMOVSD (%RDX,%RSI,8),%XMM1 |
(683) 0x2ab9a5 VFMADD213SD (%R10,%R11,8),%XMM0,%XMM1 |
(683) 0x2ab9ab VMOVSD %XMM1,(%R10,%R11,8) |
(683) 0x2ab9b1 INC %RSI |
(683) 0x2ab9b4 CMP %RCX,%RSI |
(683) 0x2ab9b7 JGE 2ab9f0 |
(683) 0x2ab9b9 MOV -0x40(%RBP),%RAX |
(683) 0x2ab9bd MOV (%RAX,%RSI,8),%RAX |
(683) 0x2ab9c1 MOV (%RDI,%RAX,8),%R11 |
(683) 0x2ab9c5 CMP %R12,%R11 |
(683) 0x2ab9c8 JGE 2ab9a0 |
(683) 0x2ab9ca MOV %R13,(%RDI,%RAX,8) |
(683) 0x2ab9ce MOV -0x38(%RBP),%RCX |
(683) 0x2ab9d2 VMULSD (%RDX,%RSI,8),%XMM0,%XMM1 |
(683) 0x2ab9d7 VMOVSD %XMM1,(%R10,%R13,8) |
(683) 0x2ab9dd MOV %RAX,(%RCX,%R13,8) |
(683) 0x2ab9e1 MOV -0x78(%RBP),%RCX |
(683) 0x2ab9e5 INC %R13 |
(683) 0x2ab9e8 MOV 0x8(%RCX,%R9,8),%RCX |
(683) 0x2ab9ed JMP 2ab9b1 |
(681) 0x2ab9f0 MOV -0x148(%RBP),%RAX |
(681) 0x2ab9f7 CMPQ $0,(%RAX) |
(681) 0x2ab9fb JE 2ab940 |
(681) 0x2aba01 MOV -0x70(%RBP),%RAX |
(681) 0x2aba05 MOV (%RAX,%R9,8),%R10 |
(681) 0x2aba09 MOV 0x8(%RAX,%R9,8),%R11 |
(681) 0x2aba0e CMP %R11,%R10 |
(681) 0x2aba11 JGE 2ab940 |
(681) 0x2aba17 MOV -0xa0(%RBP),%RDX |
(681) 0x2aba1e MOV -0x120(%RBP),%RAX |
(681) 0x2aba25 MOV -0xa8(%RBP),%RCX |
(681) 0x2aba2c MOV (%RAX),%RSI |
(681) 0x2aba2f MOV (%RDX),%RDX |
(681) 0x2aba32 MOV (%RCX),%RAX |
(681) 0x2aba35 MOV %RAX,-0x38(%RBP) |
(681) 0x2aba39 JMP 2aba5d |
(682) 0x2aba40 VMOVSD (%RSI,%R10,8),%XMM1 |
(682) 0x2aba46 VFMADD213SD (%RDX,%RAX,8),%XMM0,%XMM1 |
(682) 0x2aba4c VMOVSD %XMM1,(%RDX,%RAX,8) |
(682) 0x2aba51 INC %R10 |
(682) 0x2aba54 CMP %R11,%R10 |
(682) 0x2aba57 JGE 2ab940 |
(682) 0x2aba5d MOV -0x30(%RBP),%RAX |
(682) 0x2aba61 MOV -0x48(%RBP),%RCX |
(682) 0x2aba65 MOV (%RAX,%R10,8),%RAX |
(682) 0x2aba69 MOV (%RCX,%RAX,8),%RCX |
(682) 0x2aba6d ADD (%RBX),%RCX |
(682) 0x2aba70 MOV (%RDI,%RCX,8),%RAX |
(682) 0x2aba74 CMP %R15,%RAX |
(682) 0x2aba77 JGE 2aba40 |
(682) 0x2aba79 MOV %R14,(%RDI,%RCX,8) |
(682) 0x2aba7d MOV -0x38(%RBP),%RAX |
(682) 0x2aba81 VMULSD (%RSI,%R10,8),%XMM0,%XMM1 |
(682) 0x2aba87 VMOVSD %XMM1,(%RDX,%R14,8) |
(682) 0x2aba8d SUB (%RBX),%RCX |
(682) 0x2aba90 MOV %RCX,(%RAX,%R14,8) |
(682) 0x2aba94 MOV -0x70(%RBP),%RCX |
(682) 0x2aba98 INC %R14 |
(682) 0x2aba9b MOV 0x8(%RCX,%R9,8),%R11 |
(682) 0x2abaa0 JMP 2aba51 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 5.33 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.71 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.43 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..9#0x2ab3e0 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:917-917,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 13.33 |
CQA cycles if no scalar integer | 2.50 |
CQA cycles if FP arith vectorized | 13.33 |
CQA cycles if fully vectorized | 2.83 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.50 |
P3 cycles | 4.00 |
P4 cycles | 13.33 |
P5 cycles | 13.33 |
P6 cycles | 13.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 56.00 |
Nb uops | 56.00 |
Nb loads | 28.00 |
Nb stores | 12.00 |
Nb stack references | 20.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 224.00 |
Bytes stored | 96.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 5.33 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.71 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.43 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..9#0x2ab3e0 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:917-917,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 13.33 |
CQA cycles if no scalar integer | 2.50 |
CQA cycles if FP arith vectorized | 13.33 |
CQA cycles if fully vectorized | 2.83 |
Front-end cycles | 9.33 |
DIV/SQRT cycles | 4.00 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.50 |
P3 cycles | 4.00 |
P4 cycles | 13.33 |
P5 cycles | 13.33 |
P6 cycles | 13.33 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 56.00 |
Nb uops | 56.00 |
Nb loads | 28.00 |
Nb stores | 12.00 |
Nb stack references | 20.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 224.00 |
Bytes stored | 96.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | .omp_outlined..9#0x2ab3e0 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 56 |
nb uops | 56 |
loop length | 256 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 20 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 2.75 | 2.75 | 2.50 | 4.00 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 4.00 | 2.75 | 2.75 | 2.50 | 4.00 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 9.33 |
Dispatch | 13.33 |
Overall L1 | 13.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R14,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R9,-0x98(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2abaa2 <.omp_outlined..9+0x6c2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x100(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R9,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RAX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 2ab6ff <.omp_outlined..9+0x31f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xf8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xe8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%R12),%R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD (%RAX),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0xf0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM0,(%RAX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %RDX,(%RCX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMPQ $0,(%RAX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 2ab8d0 <.omp_outlined..9+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDX),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%RCX,%RDX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RAX,0x8(%RCX,%RDX,8) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2ab8d4 <.omp_outlined..9+0x4f4> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R9,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xb8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RDX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 2ab779 <.omp_outlined..9+0x399> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA 0x1(%RDX),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 2ab8e4 <.omp_outlined..9+0x504> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x50(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R8,(%RAX,%R9,8) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2ab6b0 <.omp_outlined..9+0x2d0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xd0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xd8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xe0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R9,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 2ab955 <.omp_outlined..9+0x575> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | .omp_outlined..9#0x2ab3e0 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 56 |
nb uops | 56 |
loop length | 256 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 20 |
micro-operation queue | 9.33 cycles |
front end | 9.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.00 | 2.75 | 2.75 | 2.50 | 4.00 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 4.00 | 2.75 | 2.75 | 2.50 | 4.00 | 13.33 | 13.33 | 13.33 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 9.33 |
Dispatch | 13.33 |
Overall L1 | 13.33 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %R14,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %R9,-0x98(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2abaa2 <.omp_outlined..9+0x6c2> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x100(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R9,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,(%RAX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 2ab6ff <.omp_outlined..9+0x31f> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xf8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xe8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%R12),%R13 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
VMOVSD (%RAX),%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV -0xf0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
VMOVSD %XMM0,(%RAX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV %RDX,(%RCX,%R12,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x108(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMPQ $0,(%RAX) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 2ab8d0 <.omp_outlined..9+0x4f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xb0(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDX),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%RCX,%RDX,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RAX,0x8(%RCX,%RDX,8) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2ab8d4 <.omp_outlined..9+0x4f4> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R9,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R15,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0xb8(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xc0(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RCX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RDX,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 2ab779 <.omp_outlined..9+0x399> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA 0x1(%RDX),%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R15,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 2ab8e4 <.omp_outlined..9+0x504> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x50(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX,%RDX,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %R8,(%RAX,%R9,8) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JLE 2ab6b0 <.omp_outlined..9+0x2d0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0xc8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x40(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xd0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xd8(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xe0(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %R9,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JMP 2ab955 <.omp_outlined..9+0x575> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |