Loop Id: 4021 | Module: exec | Source: ams.c:3662-3682 | Coverage: 8.2% |
---|
Loop Id: 4021 | Module: exec | Source: ams.c:3662-3682 | Coverage: 8.2% |
---|
0x5249e5 MOV -0x30(%RBP),%R9 |
0x5249e9 NOPL (%RAX) |
0x5249f0 MULSD %XMM0,%XMM2 |
0x5249f4 MOV -0x70(%RBP),%RDI |
0x5249f8 DIVSD (%RDI,%RSI,8),%XMM2 |
0x5249fd MOV -0x60(%RBP),%RDI |
0x524a01 ADDSD (%RDI,%RSI,8),%XMM2 |
0x524a06 MOVSD %XMM2,(%RDI,%RSI,8) |
(4020) 0x524a0b LEA 0x1(%RDX),%RSI |
(4020) 0x524a0f CMP %RCX,%RDX |
(4020) 0x524a12 MOV %RSI,%RDX |
(4020) 0x524a15 JE 5249bd |
(4020) 0x524a17 MOV -0x78(%RBP),%RAX |
(4020) 0x524a1b LEA (%RAX,%RDX,1),%RSI |
(4020) 0x524a1f MOV (%R9,%RSI,8),%RDI |
(4020) 0x524a23 UCOMISD (%R14,%RDI,8),%XMM1 |
(4020) 0x524a29 JE 524a0b |
0x524a2b MOV -0x68(%RBP),%R8 |
0x524a2f MOVSD (%R8,%RSI,8),%XMM2 |
0x524a35 MOV 0x8(%R9,%RSI,8),%R8 |
0x524a3a SUB %RDI,%R8 |
0x524a3d JLE 524c07 |
0x524a43 CMP $0x8,%R8 |
0x524a47 JB 524b0b |
0x524a4d MOV %R8,%R9 |
0x524a50 SHR $0x3,%R9 |
0x524a54 LEA (,%RDI,8),%R10 |
0x524a5c NOPL (%RAX) |
(4023) 0x524a60 MOV 0x10(%RBX,%R10,1),%R11 |
(4023) 0x524a65 MOVSD (%R15,%R11,8),%XMM3 |
(4023) 0x524a6b MOV 0x18(%RBX,%R10,1),%R11 |
(4023) 0x524a70 MOVHPD (%R15,%R11,8),%XMM3 |
(4023) 0x524a76 MOV 0x30(%RBX,%R10,1),%R11 |
(4023) 0x524a7b MOVSD (%R15,%R11,8),%XMM4 |
(4023) 0x524a81 MOV 0x38(%RBX,%R10,1),%R11 |
(4023) 0x524a86 MOVHPD (%R15,%R11,8),%XMM4 |
(4023) 0x524a8c MOV (%RBX,%R10,1),%R11 |
(4023) 0x524a90 MOVSD (%R15,%R11,8),%XMM5 |
(4023) 0x524a96 MOV 0x8(%RBX,%R10,1),%R11 |
(4023) 0x524a9b MOVHPD (%R15,%R11,8),%XMM5 |
(4023) 0x524aa1 MOV 0x20(%RBX,%R10,1),%R11 |
(4023) 0x524aa6 MOVSD (%R15,%R11,8),%XMM6 |
(4023) 0x524aac MOV 0x28(%RBX,%R10,1),%R11 |
(4023) 0x524ab1 MOVHPD (%R15,%R11,8),%XMM6 |
(4023) 0x524ab7 MOVUPD 0x10(%R14,%R10,1),%XMM7 |
(4023) 0x524abe MULPD %XMM7,%XMM3 |
(4023) 0x524ac2 MOVUPD 0x30(%R14,%R10,1),%XMM7 |
(4023) 0x524ac9 MULPD %XMM7,%XMM4 |
(4023) 0x524acd MOVUPD (%R14,%R10,1),%XMM7 |
(4023) 0x524ad3 ADDPD %XMM3,%XMM4 |
(4023) 0x524ad7 MOVUPD 0x20(%R14,%R10,1),%XMM3 |
(4023) 0x524ade MULPD %XMM7,%XMM5 |
(4023) 0x524ae2 MULPD %XMM3,%XMM6 |
(4023) 0x524ae6 ADDPD %XMM5,%XMM6 |
(4023) 0x524aea ADDPD %XMM4,%XMM6 |
(4023) 0x524aee MOVAPD %XMM6,%XMM3 |
(4023) 0x524af2 UNPCKHPD %XMM6,%XMM3 |
(4023) 0x524af6 ADDSD %XMM6,%XMM3 |
(4023) 0x524afa SUBSD %XMM3,%XMM2 |
(4023) 0x524afe ADD $0x40,%R10 |
(4023) 0x524b02 DEC %R9 |
(4023) 0x524b05 JNE 524a60 |
0x524b0b MOV %R8D,%R9D |
0x524b0e AND $0x7,%R9D |
0x524b12 DEC %R9 |
0x524b15 CMP $0x6,%R9 |
0x524b19 JA 524b51 |
0x524b51 MOV -0x30(%RBP),%R9 |
0x524b55 JMP 524c07 |
0x524c07 MOV -0x58(%RBP),%RAX |
0x524c0b MOV (%RAX,%RSI,8),%RDI |
0x524c0f MOV 0x8(%RAX,%RSI,8),%R8 |
0x524c14 SUB %RDI,%R8 |
0x524c17 JLE 5249f0 |
0x524c1d CMP $0x8,%R8 |
0x524c21 JB 524cec |
0x524c27 MOV %R8,%R9 |
0x524c2a SHR $0x3,%R9 |
0x524c2e LEA (,%RDI,8),%R10 |
0x524c36 MOV -0x38(%RBP),%RAX |
0x524c3a NOPW (%RAX,%RAX,1) |
(4022) 0x524c40 MOV 0x10(%R13,%R10,1),%R11 |
(4022) 0x524c45 MOVSD (%R12,%R11,8),%XMM3 |
(4022) 0x524c4b MOV 0x18(%R13,%R10,1),%R11 |
(4022) 0x524c50 MOVHPD (%R12,%R11,8),%XMM3 |
(4022) 0x524c56 MOV 0x30(%R13,%R10,1),%R11 |
(4022) 0x524c5b MOVSD (%R12,%R11,8),%XMM4 |
(4022) 0x524c61 MOV 0x38(%R13,%R10,1),%R11 |
(4022) 0x524c66 MOVHPD (%R12,%R11,8),%XMM4 |
(4022) 0x524c6c MOV (%R13,%R10,1),%R11 |
(4022) 0x524c71 MOVSD (%R12,%R11,8),%XMM5 |
(4022) 0x524c77 MOV 0x8(%R13,%R10,1),%R11 |
(4022) 0x524c7c MOVHPD (%R12,%R11,8),%XMM5 |
(4022) 0x524c82 MOV 0x20(%R13,%R10,1),%R11 |
(4022) 0x524c87 MOVSD (%R12,%R11,8),%XMM6 |
(4022) 0x524c8d MOV 0x28(%R13,%R10,1),%R11 |
(4022) 0x524c92 MOVHPD (%R12,%R11,8),%XMM6 |
(4022) 0x524c98 MOVUPD 0x10(%RAX,%R10,1),%XMM7 |
(4022) 0x524c9f MULPD %XMM7,%XMM3 |
(4022) 0x524ca3 MOVUPD 0x30(%RAX,%R10,1),%XMM7 |
(4022) 0x524caa MULPD %XMM7,%XMM4 |
(4022) 0x524cae MOVUPD (%RAX,%R10,1),%XMM7 |
(4022) 0x524cb4 ADDPD %XMM3,%XMM4 |
(4022) 0x524cb8 MOVUPD 0x20(%RAX,%R10,1),%XMM3 |
(4022) 0x524cbf MULPD %XMM7,%XMM5 |
(4022) 0x524cc3 MULPD %XMM3,%XMM6 |
(4022) 0x524cc7 ADDPD %XMM5,%XMM6 |
(4022) 0x524ccb ADDPD %XMM4,%XMM6 |
(4022) 0x524ccf MOVAPD %XMM6,%XMM3 |
(4022) 0x524cd3 UNPCKHPD %XMM6,%XMM3 |
(4022) 0x524cd7 ADDSD %XMM6,%XMM3 |
(4022) 0x524cdb SUBSD %XMM3,%XMM2 |
(4022) 0x524cdf ADD $0x40,%R10 |
(4022) 0x524ce3 DEC %R9 |
(4022) 0x524ce6 JNE 524c40 |
0x524cec MOV %R8D,%R9D |
0x524cef AND $0x7,%R9D |
0x524cf3 DEC %R9 |
0x524cf6 CMP $0x6,%R9 |
0x524cfa JA 5249e5 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682 |
-------------------------------------------------------------------------------- |
3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE |
3663: #endif |
3664: for (i = 0; i < n; i++) |
3665: { |
3666: /*----------------------------------------------------------- |
3667: * If diagonal is nonzero, relax point i; otherwise, skip it. |
3668: *-----------------------------------------------------------*/ |
3669: if (A_diag_data[A_diag_i[i]] != zero) |
3670: { |
3671: res = f_data[i]; |
3672: for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++) |
3673: { |
3674: ii = A_diag_j[jj]; |
3675: res -= A_diag_data[jj] * Vtemp_data[ii]; |
3676: } |
3677: for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++) |
3678: { |
3679: ii = A_offd_j[jj]; |
3680: res -= A_offd_data[jj] * Vext_data[ii]; |
3681: } |
3682: u_data[i] += (relax_weight*res)/l1_norms[i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.30 |
CQA speedup if FP arith vectorized | 3.00 |
CQA speedup if fully vectorized | 5.20 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRRelaxThreads.extracted.57 |
Source | ams.c:3662-3662,ams.c:3669-3677,ams.c:3682-3682 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.50 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 2.17 |
CQA cycles if fully vectorized | 1.25 |
Front-end cycles | 6.50 |
DIV/SQRT cycles | 4.25 |
P0 cycles | 4.25 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 3.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 5.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 43.00 |
Nb uops | 39.00 |
Nb loads | 13.00 |
Nb stores | 1.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.46 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.23 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.30 |
CQA speedup if FP arith vectorized | 3.00 |
CQA speedup if fully vectorized | 5.20 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | NA |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRRelaxThreads.extracted.57 |
Source | ams.c:3662-3662,ams.c:3669-3677,ams.c:3682-3682 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.50 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 2.17 |
CQA cycles if fully vectorized | 1.25 |
Front-end cycles | 6.50 |
DIV/SQRT cycles | 4.25 |
P0 cycles | 4.25 |
P1 cycles | 4.00 |
P2 cycles | 4.00 |
P3 cycles | 3.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.50 |
P10 cycles | 0.50 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 5.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 43.00 |
Nb uops | 39.00 |
Nb loads | 13.00 |
Nb stores | 1.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.46 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 1.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 17.23 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | 0.00 |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | 12.50 |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParCSRRelaxThreads.extracted.57 |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 43 |
nb uops | 39 |
loop length | 193 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 6.50 cycles |
front end | 6.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.25 | 4.25 | 4.00 | 4.00 | 3.50 | 4.67 | 4.67 | 4.67 | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 |
cycles | 4.25 | 4.25 | 4.00 | 4.00 | 3.50 | 4.67 | 4.67 | 4.67 | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | 5.00 |
Front-end | 6.50 |
Dispatch | 4.67 |
DIV/SQRT | 5.00 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MULSD %XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x70(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
DIVSD (%RDI,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADDSD (%RDI,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
MOVSD %XMM2,(%RDI,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV -0x68(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVSD (%R8,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%R9,%RSI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %RDI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 524c07 <hypre_ParCSRRelaxThreads.extracted.57+0x2f7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 524b0b <hypre_ParCSRRelaxThreads.extracted.57+0x1fb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R9 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 524b51 <hypre_ParCSRRelaxThreads.extracted.57+0x241> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 524c07 <hypre_ParCSRRelaxThreads.extracted.57+0x2f7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%RAX,%RSI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %RDI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 5249f0 <hypre_ParCSRRelaxThreads.extracted.57+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 524cec <hypre_ParCSRRelaxThreads.extracted.57+0x3dc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R9 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 5249e5 <hypre_ParCSRRelaxThreads.extracted.57+0xd5> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | hypre_ParCSRRelaxThreads.extracted.57 |
Source file and lines | ams.c:3662-3682 |
Module | exec |
nb instructions | 43 |
nb uops | 39 |
loop length | 193 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 2 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 6.50 cycles |
front end | 6.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 4.25 | 4.25 | 4.00 | 4.00 | 3.50 | 4.67 | 4.67 | 4.67 | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 |
cycles | 4.25 | 4.25 | 4.00 | 4.00 | 3.50 | 4.67 | 4.67 | 4.67 | 1.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | 5.00 |
Front-end | 6.50 |
Dispatch | 4.67 |
DIV/SQRT | 5.00 |
Overall L1 | 6.50 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | NA (no other vectorizable/vectorized instructions) |
all | 0% |
load | 0% |
store | 0% |
mul | 0% |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | 12% |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MULSD %XMM0,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 0.50 |
MOV -0x70(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
DIVSD (%RDI,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 13 | 5 |
MOV -0x60(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
ADDSD (%RDI,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 3 | 0.50 |
MOVSD %XMM2,(%RDI,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
MOV -0x68(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOVSD (%R8,%RSI,8),%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV 0x8(%R9,%RSI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %RDI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 524c07 <hypre_ParCSRRelaxThreads.extracted.57+0x2f7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 524b0b <hypre_ParCSRRelaxThreads.extracted.57+0x1fb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R9 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPL (%RAX) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 524b51 <hypre_ParCSRRelaxThreads.extracted.57+0x241> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x30(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 524c07 <hypre_ParCSRRelaxThreads.extracted.57+0x2f7> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RAX,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%RAX,%RSI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
SUB %RDI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 5249f0 <hypre_ParCSRRelaxThreads.extracted.57+0xe0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 524cec <hypre_ParCSRRelaxThreads.extracted.57+0x3dc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R9 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
NOPW (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R9D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 5249e5 <hypre_ParCSRRelaxThreads.extracted.57+0xd5> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |