Loop Id: 4722 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.03% |
---|
Loop Id: 4722 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.03% |
---|
0x54ee60 MOV -0x78(%RBP),%RSI |
0x54ee64 MOV -0x48(%RBP),%RDI |
0x54ee68 MOV %RBX,(%RSI,%RDI,8) |
0x54ee6c MOV -0x70(%RBP),%RSI |
0x54ee70 MOV %R8,(%RSI,%RDI,8) |
0x54ee74 MOV %RDX,%RDI |
0x54ee77 MOV %R13,%R8 |
0x54ee7a MOV %RAX,%RBX |
0x54ee7d CMP -0x40(%RBP),%RDX |
0x54ee81 JGE 54f07c |
0x54ee87 CMPQ $0,0x78(%RBP) |
0x54ee8c JE 54ee96 |
0x54ee8e MOV %RBX,(%R14,%RDI,8) |
0x54ee92 LEA 0x1(%RBX),%RAX |
0x54ee96 CMPQ $0,0x70(%RBP) |
0x54ee9b MOV %RDI,-0x48(%RBP) |
0x54ee9f JE 54ef70 |
0x54eea5 MOV 0x10(%RBP),%RSI |
0x54eea9 MOV (%RSI,%RDI,8),%R10 |
0x54eead LEA 0x1(%RDI),%RDX |
0x54eeb1 CMP 0x8(%RSI,%RDI,8),%R10 |
0x54eeb6 JGE 54ef74 |
0x54eebc MOV %R8,%R13 |
0x54eebf JMP 54eee6 |
(4726) 0x54eed0 INC %R10 |
(4726) 0x54eed3 MOV 0x10(%RBP),%RSI |
(4726) 0x54eed7 MOV -0x48(%RBP),%RDI |
(4726) 0x54eedb CMP 0x8(%RSI,%RDI,8),%R10 |
(4726) 0x54eee0 JGE 54ef77 |
(4726) 0x54eee6 MOV 0x18(%RBP),%RSI |
(4726) 0x54eeea MOV (%RSI,%R10,8),%R12 |
(4726) 0x54eeee MOV 0x50(%RBP),%RDI |
(4726) 0x54eef2 MOV (%RDI,%R12,8),%RSI |
(4726) 0x54eef6 MOV 0x8(%RDI,%R12,8),%RDI |
(4726) 0x54eefb JMP 54ef03 |
(4728) 0x54ef00 INC %RSI |
(4728) 0x54ef03 CMP %RDI,%RSI |
(4728) 0x54ef06 JGE 54ef30 |
(4728) 0x54ef08 MOV 0x58(%RBP),%R9 |
(4728) 0x54ef0c MOV (%R9,%RSI,8),%R9 |
(4728) 0x54ef10 ADD %R15,%R9 |
(4728) 0x54ef13 CMP %R8,(%R14,%R9,8) |
(4728) 0x54ef17 JGE 54ef00 |
(4728) 0x54ef19 MOV %R13,(%R14,%R9,8) |
(4728) 0x54ef1d INC %R13 |
(4728) 0x54ef20 MOV 0x50(%RBP),%RDI |
(4728) 0x54ef24 MOV 0x8(%RDI,%R12,8),%RDI |
(4728) 0x54ef29 JMP 54ef00 |
(4726) 0x54ef30 MOV 0x40(%RBP),%RDI |
(4726) 0x54ef34 MOV (%RDI,%R12,8),%RSI |
(4726) 0x54ef38 MOV 0x8(%RDI,%R12,8),%RDI |
(4726) 0x54ef3d JMP 54ef43 |
(4727) 0x54ef40 INC %RSI |
(4727) 0x54ef43 CMP %RDI,%RSI |
(4727) 0x54ef46 JGE 54eed0 |
(4727) 0x54ef48 MOV 0x48(%RBP),%R9 |
(4727) 0x54ef4c MOV (%R9,%RSI,8),%R9 |
(4727) 0x54ef50 CMP %RBX,(%R14,%R9,8) |
(4727) 0x54ef54 JGE 54ef40 |
(4727) 0x54ef56 MOV %RAX,(%R14,%R9,8) |
(4727) 0x54ef5a INC %RAX |
(4727) 0x54ef5d MOV 0x40(%RBP),%RDI |
(4727) 0x54ef61 MOV 0x8(%RDI,%R12,8),%RDI |
(4727) 0x54ef66 JMP 54ef40 |
0x54ef70 LEA 0x1(%RDI),%RDX |
0x54ef74 MOV %R8,%R13 |
0x54ef77 MOV -0x50(%RBP),%RSI |
0x54ef7b MOV (%RSI,%RDI,8),%R10 |
0x54ef7f JMP 54ef97 |
(4723) 0x54ef90 INC %R10 |
(4723) 0x54ef93 MOV -0x50(%RBP),%RSI |
(4723) 0x54ef97 CMP (%RSI,%RDX,8),%R10 |
(4723) 0x54ef9b JGE 54ee60 |
(4723) 0x54efa1 MOV -0x80(%RBP),%RSI |
(4723) 0x54efa5 MOV (%RSI,%R10,8),%R12 |
(4723) 0x54efa9 MOV 0x20(%RBP),%RDI |
(4723) 0x54efad MOV (%RDI,%R12,8),%RSI |
(4723) 0x54efb1 MOV 0x8(%RDI,%R12,8),%RDI |
(4723) 0x54efb6 JMP 54efc3 |
(4725) 0x54efc0 INC %RSI |
(4725) 0x54efc3 CMP %RDI,%RSI |
(4725) 0x54efc6 JGE 54eff0 |
(4725) 0x54efc8 MOV (%RCX,%RSI,8),%R9 |
(4725) 0x54efcc CMP %RBX,(%R14,%R9,8) |
(4725) 0x54efd0 JGE 54efc0 |
(4725) 0x54efd2 MOV %RAX,(%R14,%R9,8) |
(4725) 0x54efd6 INC %RAX |
(4725) 0x54efd9 MOV 0x20(%RBP),%RDI |
(4725) 0x54efdd MOV 0x8(%RDI,%R12,8),%RDI |
(4725) 0x54efe2 JMP 54efc0 |
(4723) 0x54eff0 CMPQ $0,0x88(%RBP) |
(4723) 0x54eff8 JE 54ef90 |
(4723) 0x54effa MOV 0x30(%RBP),%RDI |
(4723) 0x54effe MOV (%RDI,%R12,8),%RSI |
(4723) 0x54f002 MOV 0x8(%RDI,%R12,8),%RDI |
(4723) 0x54f007 JMP 54f013 |
(4724) 0x54f010 INC %RSI |
(4724) 0x54f013 CMP %RDI,%RSI |
(4724) 0x54f016 JGE 54ef90 |
(4724) 0x54f01c MOV 0x38(%RBP),%R9 |
(4724) 0x54f020 MOV (%R9,%RSI,8),%R9 |
(4724) 0x54f024 MOV 0x60(%RBP),%R11 |
(4724) 0x54f028 MOV (%R11,%R9,8),%R9 |
(4724) 0x54f02c ADD %R15,%R9 |
(4724) 0x54f02f CMP %R8,(%R14,%R9,8) |
(4724) 0x54f033 JGE 54f010 |
(4724) 0x54f035 MOV %R13,(%R14,%R9,8) |
(4724) 0x54f039 INC %R13 |
(4724) 0x54f03c MOV 0x30(%RBP),%RDI |
(4724) 0x54f040 MOV 0x8(%RDI,%R12,8),%RDI |
(4724) 0x54f045 JMP 54f010 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242 |
-------------------------------------------------------------------------------- |
127: for (i1 = ns; i1 < ne; i1++) |
[...] |
135: if ( allsquare ) { |
136: B_marker[i1] = jj_count_diag; |
137: jj_count_diag++; |
[...] |
144: if (num_cols_offd_A) |
145: { |
146: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
147: { |
148: i2 = A_offd_j[jj2]; |
[...] |
154: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
155: { |
156: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
164: if (B_marker[i3] < jj_row_begin_offd) |
165: { |
166: B_marker[i3] = jj_count_offd; |
167: jj_count_offd++; |
168: } |
169: } |
170: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
171: { |
172: i3 = B_ext_diag_j[jj3]; |
173: |
174: if (B_marker[i3] < jj_row_begin_diag) |
175: { |
176: B_marker[i3] = jj_count_diag; |
177: jj_count_diag++; |
[...] |
187: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
188: { |
189: i2 = A_diag_j[jj2]; |
[...] |
195: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
196: { |
197: i3 = B_diag_j[jj3]; |
[...] |
205: if (B_marker[i3] < jj_row_begin_diag) |
206: { |
207: B_marker[i3] = jj_count_diag; |
208: jj_count_diag++; |
[...] |
216: if (num_cols_offd_B) |
217: { |
218: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
219: { |
220: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
228: if (B_marker[i3] < jj_row_begin_offd) |
229: { |
230: B_marker[i3] = jj_count_offd; |
231: jj_count_offd++; |
[...] |
241: (*C_diag_i)[i1] = jj_row_begin_diag; |
242: (*C_offd_i)[i1] = jj_row_begin_offd; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.62 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.03 |
Bottlenecks | P5, P6, P7, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 5.00 |
CQA cycles if fully vectorized | 1.08 |
Front-end cycles | 4.83 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.50 |
P1 cycles | 2.25 |
P2 cycles | 2.25 |
P3 cycles | 3.00 |
P4 cycles | 5.00 |
P5 cycles | 5.00 |
P6 cycles | 5.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 29.00 |
Nb uops | 29.00 |
Nb loads | 11.00 |
Nb stores | 4.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.62 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.03 |
Bottlenecks | P5, P6, P7, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 5.00 |
CQA cycles if no scalar integer | 5.00 |
CQA cycles if FP arith vectorized | 5.00 |
CQA cycles if fully vectorized | 1.08 |
Front-end cycles | 4.83 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.50 |
P1 cycles | 2.25 |
P2 cycles | 2.25 |
P3 cycles | 3.00 |
P4 cycles | 5.00 |
P5 cycles | 5.00 |
P6 cycles | 5.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 29.00 |
Nb uops | 29.00 |
Nb loads | 11.00 |
Nb stores | 4.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 32.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 29 |
nb uops | 29 |
loop length | 114 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 4.83 cycles |
front end | 4.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.50 | 2.25 | 2.25 | 3.00 | 5.00 | 5.00 | 5.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 2.50 | 2.25 | 2.25 | 3.00 | 5.00 | 5.00 | 5.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.83 |
Dispatch | 5.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0x40(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 54f07c <hypre_ParMatmul_RowSizes.extracted+0x2fc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMPQ $0,0x78(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 54ee96 <hypre_ParMatmul_RowSizes.extracted+0x116> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMPQ $0,0x70(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RDI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 54ef70 <hypre_ParMatmul_RowSizes.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 54ef74 <hypre_ParMatmul_RowSizes.extracted+0x1f4> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 54eee6 <hypre_ParMatmul_RowSizes.extracted+0x166> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 54ef97 <hypre_ParMatmul_RowSizes.extracted+0x217> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 29 |
nb uops | 29 |
loop length | 114 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 4.83 cycles |
front end | 4.83 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.50 | 2.25 | 2.25 | 3.00 | 5.00 | 5.00 | 5.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 3.00 | 2.50 | 2.25 | 2.25 | 3.00 | 5.00 | 5.00 | 5.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 4.83 |
Dispatch | 5.00 |
Overall L1 | 5.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x48(%RBP),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x70(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP -0x40(%RBP),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 54f07c <hypre_ParMatmul_RowSizes.extracted+0x2fc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMPQ $0,0x78(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JE 54ee96 <hypre_ParMatmul_RowSizes.extracted+0x116> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMPQ $0,0x70(%RBP) | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
MOV %RDI,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
JE 54ef70 <hypre_ParMatmul_RowSizes.extracted+0x1f0> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 54ef74 <hypre_ParMatmul_RowSizes.extracted+0x1f4> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 54eee6 <hypre_ParMatmul_RowSizes.extracted+0x166> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
LEA 0x1(%RDI),%RDX | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 54ef97 <hypre_ParMatmul_RowSizes.extracted+0x217> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |