Loop Id: 1188 | Module: exec | Source: par_multi_interp.c:917-997 [...] | Coverage: 0.07% |
---|
Loop Id: 1188 | Module: exec | Source: par_multi_interp.c:917-997 [...] | Coverage: 0.07% |
---|
0x46d110 MOV -0x150(%RBP),%RSI |
0x46d117 INC %RSI |
0x46d11a CMP -0xd0(%RBP),%RSI |
0x46d121 JGE 46d531 |
0x46d127 MOV -0x90(%RBP),%RDX |
0x46d12e MOV %RSI,-0x150(%RBP) |
0x46d135 MOV (%RDX,%RSI,8),%RDI |
0x46d139 MOV -0x98(%RBP),%RDX |
0x46d140 MOV %RAX,(%RDX,%RDI,8) |
0x46d144 MOV -0x40(%RBP),%RDX |
0x46d148 MOV %RCX,(%RDX,%RDI,8) |
0x46d14c MOV -0xa8(%RBP),%RDX |
0x46d153 MOV (%RDX,%RDI,8),%R8 |
0x46d157 JMP 46d16a |
(1191) 0x46d159 MOV -0x58(%RBP),%R14 |
(1191) 0x46d15d NOPL (%RAX) |
(1191) 0x46d160 INC %R8 |
(1191) 0x46d163 MOV -0xa8(%RBP),%RDX |
(1191) 0x46d16a CMP 0x8(%RDX,%RDI,8),%R8 |
(1191) 0x46d16f JGE 46d440 |
(1191) 0x46d175 MOV -0x118(%RBP),%RDX |
(1191) 0x46d17c MOV (%RDX,%R8,8),%R13 |
(1191) 0x46d180 MOV -0x108(%RBP),%RDX |
(1191) 0x46d187 CMP %R14,(%RDX,%R13,8) |
(1191) 0x46d18b JNE 46d160 |
(1191) 0x46d18d MOV -0x60(%RBP),%RDX |
(1191) 0x46d191 MOV 0x8(%RDX,%R13,8),%R10 |
(1191) 0x46d196 TEST %R10,%R10 |
(1191) 0x46d199 JLE 46d2ef |
(1191) 0x46d19f MOV -0x98(%RBP),%RDX |
(1191) 0x46d1a6 MOV %R13,-0x38(%RBP) |
(1191) 0x46d1aa MOV (%RDX,%R13,8),%R11 |
(1191) 0x46d1ae ADD %R11,%R10 |
(1191) 0x46d1b1 LEA 0x1(%R11),%RDX |
(1191) 0x46d1b5 CMP %RDX,%R10 |
(1191) 0x46d1b8 CMOVLE %RDX,%R10 |
(1191) 0x46d1bc MOV -0x48(%RBP),%RDX |
(1191) 0x46d1c0 MOV -0x8(%RDX,%R12,8),%RSI |
(1191) 0x46d1c5 MOV %R10,%RDX |
(1191) 0x46d1c8 SUB %R11,%RDX |
(1191) 0x46d1cb CMP $0x4,%RDX |
(1191) 0x46d1cf MOV %RDX,-0x78(%RBP) |
(1191) 0x46d1d3 JAE 46d228 |
(1191) 0x46d1d5 MOV -0x78(%RBP),%R9 |
(1191) 0x46d1d9 MOV %R9,%RDX |
(1191) 0x46d1dc AND $-0x4,%RDX |
(1191) 0x46d1e0 CMP %R9,%RDX |
(1191) 0x46d1e3 JAE 46d2e7 |
(1191) 0x46d1e9 ADD %RDX,%R11 |
(1191) 0x46d1ec MOV -0x58(%RBP),%R14 |
(1191) 0x46d1f0 MOV -0x38(%RBP),%R13 |
(1191) 0x46d1f4 JMP 46d20c |
(1194) 0x46d200 INC %R11 |
(1194) 0x46d203 CMP %R11,%R10 |
(1194) 0x46d206 JE 46d2ef |
(1194) 0x46d20c MOV (%RSI,%R11,8),%RDX |
(1194) 0x46d210 CMP %RDI,(%RBX,%RDX,8) |
(1194) 0x46d214 JE 46d200 |
(1194) 0x46d216 INC %RAX |
(1194) 0x46d219 MOV -0x60(%RBP),%R9 |
(1194) 0x46d21d INCQ 0x8(%R9,%RDI,8) |
(1194) 0x46d222 MOV %RDI,(%RBX,%RDX,8) |
(1194) 0x46d226 JMP 46d200 |
(1191) 0x46d228 MOV %RDX,%R14 |
(1191) 0x46d22b SHR $0x2,%R14 |
(1191) 0x46d22f LEA (%RSI,%R11,8),%R13 |
(1191) 0x46d233 ADD $0x18,%R13 |
(1191) 0x46d237 JMP 46d249 |
(1195) 0x46d240 ADD $0x20,%R13 |
(1195) 0x46d244 DEC %R14 |
(1195) 0x46d247 JE 46d1d5 |
(1195) 0x46d249 MOV -0x18(%R13),%RDX |
(1195) 0x46d24d CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d251 JNE 46d280 |
(1195) 0x46d253 MOV -0x10(%R13),%RDX |
(1195) 0x46d257 CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d25b JNE 46d29a |
(1195) 0x46d25d MOV -0x8(%R13),%RDX |
(1195) 0x46d261 CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d265 JNE 46d2b4 |
(1195) 0x46d267 MOV (%R13),%RDX |
(1195) 0x46d26b CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d26f JE 46d240 |
(1195) 0x46d271 JMP 46d2d2 |
(1195) 0x46d280 INC %RAX |
(1195) 0x46d283 MOV -0x60(%RBP),%R9 |
(1195) 0x46d287 INCQ 0x8(%R9,%RDI,8) |
(1195) 0x46d28c MOV %RDI,(%RBX,%RDX,8) |
(1195) 0x46d290 MOV -0x10(%R13),%RDX |
(1195) 0x46d294 CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d298 JE 46d25d |
(1195) 0x46d29a INC %RAX |
(1195) 0x46d29d MOV -0x60(%RBP),%R9 |
(1195) 0x46d2a1 INCQ 0x8(%R9,%RDI,8) |
(1195) 0x46d2a6 MOV %RDI,(%RBX,%RDX,8) |
(1195) 0x46d2aa MOV -0x8(%R13),%RDX |
(1195) 0x46d2ae CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d2b2 JE 46d267 |
(1195) 0x46d2b4 INC %RAX |
(1195) 0x46d2b7 MOV -0x60(%RBP),%R9 |
(1195) 0x46d2bb INCQ 0x8(%R9,%RDI,8) |
(1195) 0x46d2c0 MOV %RDI,(%RBX,%RDX,8) |
(1195) 0x46d2c4 MOV (%R13),%RDX |
(1195) 0x46d2c8 CMP %RDI,(%RBX,%RDX,8) |
(1195) 0x46d2cc JE 46d240 |
(1195) 0x46d2d2 INC %RAX |
(1195) 0x46d2d5 MOV -0x60(%RBP),%R9 |
(1195) 0x46d2d9 INCQ 0x8(%R9,%RDI,8) |
(1195) 0x46d2de MOV %RDI,(%RBX,%RDX,8) |
(1195) 0x46d2e2 JMP 46d240 |
(1191) 0x46d2e7 MOV -0x58(%RBP),%R14 |
(1191) 0x46d2eb MOV -0x38(%RBP),%R13 |
(1191) 0x46d2ef MOV -0x68(%RBP),%RDX |
(1191) 0x46d2f3 MOV 0x8(%RDX,%R13,8),%R10 |
(1191) 0x46d2f8 TEST %R10,%R10 |
(1191) 0x46d2fb JLE 46d160 |
(1191) 0x46d301 MOV -0x40(%RBP),%RDX |
(1191) 0x46d305 MOV (%RDX,%R13,8),%R9 |
(1191) 0x46d309 ADD %R9,%R10 |
(1191) 0x46d30c LEA 0x1(%R9),%RDX |
(1191) 0x46d310 CMP %RDX,%R10 |
(1191) 0x46d313 CMOVLE %RDX,%R10 |
(1191) 0x46d317 MOV -0x50(%RBP),%RDX |
(1191) 0x46d31b MOV -0x8(%RDX,%R12,8),%RSI |
(1191) 0x46d320 MOV %R10,%R11 |
(1191) 0x46d323 SUB %R9,%R11 |
(1191) 0x46d326 CMP $0x4,%R11 |
(1191) 0x46d32a MOV %R11,-0x38(%RBP) |
(1191) 0x46d32e JAE 46d378 |
(1191) 0x46d330 MOV -0x38(%RBP),%RDX |
(1191) 0x46d334 MOV %RDX,%R11 |
(1191) 0x46d337 AND $-0x4,%R11 |
(1191) 0x46d33b CMP %RDX,%R11 |
(1191) 0x46d33e JAE 46d159 |
(1191) 0x46d344 ADD %R11,%R9 |
(1191) 0x46d347 MOV -0x58(%RBP),%R14 |
(1191) 0x46d34b JMP 46d35c |
(1192) 0x46d350 INC %R9 |
(1192) 0x46d353 CMP %R9,%R10 |
(1192) 0x46d356 JE 46d160 |
(1192) 0x46d35c MOV (%RSI,%R9,8),%RDX |
(1192) 0x46d360 CMP %RDI,(%R15,%RDX,8) |
(1192) 0x46d364 JE 46d350 |
(1192) 0x46d366 INC %RCX |
(1192) 0x46d369 MOV -0x68(%RBP),%R11 |
(1192) 0x46d36d INCQ 0x8(%R11,%RDI,8) |
(1192) 0x46d372 MOV %RDI,(%R15,%RDX,8) |
(1192) 0x46d376 JMP 46d350 |
(1191) 0x46d378 SHR $0x2,%R11 |
(1191) 0x46d37c LEA (%RSI,%R9,8),%R14 |
(1191) 0x46d380 ADD $0x18,%R14 |
(1191) 0x46d384 JMP 46d399 |
(1193) 0x46d390 ADD $0x20,%R14 |
(1193) 0x46d394 DEC %R11 |
(1193) 0x46d397 JE 46d330 |
(1193) 0x46d399 MOV -0x18(%R14),%R13 |
(1193) 0x46d39d CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d3a1 JNE 46d3d0 |
(1193) 0x46d3a3 MOV -0x10(%R14),%R13 |
(1193) 0x46d3a7 CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d3ab JNE 46d3ea |
(1193) 0x46d3ad MOV -0x8(%R14),%R13 |
(1193) 0x46d3b1 CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d3b5 JNE 46d404 |
(1193) 0x46d3b7 MOV (%R14),%R13 |
(1193) 0x46d3ba CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d3be JE 46d390 |
(1193) 0x46d3c0 JMP 46d421 |
(1193) 0x46d3d0 INC %RCX |
(1193) 0x46d3d3 MOV -0x68(%RBP),%RDX |
(1193) 0x46d3d7 INCQ 0x8(%RDX,%RDI,8) |
(1193) 0x46d3dc MOV %RDI,(%R15,%R13,8) |
(1193) 0x46d3e0 MOV -0x10(%R14),%R13 |
(1193) 0x46d3e4 CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d3e8 JE 46d3ad |
(1193) 0x46d3ea INC %RCX |
(1193) 0x46d3ed MOV -0x68(%RBP),%RDX |
(1193) 0x46d3f1 INCQ 0x8(%RDX,%RDI,8) |
(1193) 0x46d3f6 MOV %RDI,(%R15,%R13,8) |
(1193) 0x46d3fa MOV -0x8(%R14),%R13 |
(1193) 0x46d3fe CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d402 JE 46d3b7 |
(1193) 0x46d404 INC %RCX |
(1193) 0x46d407 MOV -0x68(%RBP),%RDX |
(1193) 0x46d40b INCQ 0x8(%RDX,%RDI,8) |
(1193) 0x46d410 MOV %RDI,(%R15,%R13,8) |
(1193) 0x46d414 MOV (%R14),%R13 |
(1193) 0x46d417 CMP %RDI,(%R15,%R13,8) |
(1193) 0x46d41b JE 46d390 |
(1193) 0x46d421 INC %RCX |
(1193) 0x46d424 MOV -0x68(%RBP),%RDX |
(1193) 0x46d428 INCQ 0x8(%RDX,%RDI,8) |
(1193) 0x46d42d MOV %RDI,(%R15,%R13,8) |
(1193) 0x46d431 JMP 46d390 |
0x46d440 MOV -0xa0(%RBP),%RDX |
0x46d447 MOV (%RDX,%RDI,8),%R8 |
0x46d44b MOV 0x8(%RDX,%RDI,8),%RSI |
0x46d450 CMP %RSI,%R8 |
0x46d453 JL 46d46c |
0x46d455 JMP 46d110 |
(1189) 0x46d460 INC %R8 |
(1189) 0x46d463 CMP %RSI,%R8 |
(1189) 0x46d466 JGE 46d110 |
(1189) 0x46d46c MOV -0x120(%RBP),%RDX |
(1189) 0x46d473 MOV (%RDX,%R8,8),%R9 |
(1189) 0x46d477 MOV -0x110(%RBP),%RDX |
(1189) 0x46d47e CMP %R14,(%RDX,%R9,8) |
(1189) 0x46d482 JNE 46d460 |
(1189) 0x46d484 MOV -0x100(%RBP),%RDX |
(1189) 0x46d48b MOV 0x8(%RDX,%R9,8),%RDX |
(1189) 0x46d490 TEST %RDX,%RDX |
(1189) 0x46d493 JLE 46d460 |
(1189) 0x46d495 MOV -0xf0(%RBP),%RSI |
(1189) 0x46d49c MOV (%RSI,%R9,8),%RSI |
(1189) 0x46d4a0 ADD %RSI,%RDX |
(1189) 0x46d4a3 MOV -0xf8(%RBP),%R9 |
(1189) 0x46d4aa MOV (%R9,%R12,8),%R9 |
(1189) 0x46d4ae LEA 0x1(%RSI),%R10 |
(1189) 0x46d4b2 CMP %R10,%RDX |
(1189) 0x46d4b5 CMOVLE %R10,%RDX |
(1189) 0x46d4b9 JMP 46d4d0 |
(1190) 0x46d4c0 INCQ 0x8(%R11,%RDI,8) |
(1190) 0x46d4c5 MOV %RDI,(%R10) |
(1190) 0x46d4c8 INC %RSI |
(1190) 0x46d4cb CMP %RSI,%RDX |
(1190) 0x46d4ce JE 46d510 |
(1190) 0x46d4d0 MOV (%R9,%RSI,8),%R10 |
(1190) 0x46d4d4 TEST %R10,%R10 |
(1190) 0x46d4d7 JS 46d4f0 |
(1190) 0x46d4d9 CMP %RDI,(%R15,%R10,8) |
(1190) 0x46d4dd JE 46d4c8 |
(1190) 0x46d4df LEA (%R15,%R10,8),%R10 |
(1190) 0x46d4e3 INC %RCX |
(1190) 0x46d4e6 MOV -0x68(%RBP),%R11 |
(1190) 0x46d4ea JMP 46d4c0 |
(1190) 0x46d4f0 NOT %R10 |
(1190) 0x46d4f3 CMP %RDI,(%RBX,%R10,8) |
(1190) 0x46d4f7 JE 46d4c8 |
(1190) 0x46d4f9 LEA (%RBX,%R10,8),%R10 |
(1190) 0x46d4fd INC %RAX |
(1190) 0x46d500 MOV -0x60(%RBP),%R11 |
(1190) 0x46d504 JMP 46d4c0 |
(1189) 0x46d510 MOV -0xa0(%RBP),%RDX |
(1189) 0x46d517 MOV 0x8(%RDX,%RDI,8),%RSI |
(1189) 0x46d51c INC %R8 |
(1189) 0x46d51f CMP %RSI,%R8 |
(1189) 0x46d522 JL 46d46c |
0x46d528 JMP 46d110 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 997 |
-------------------------------------------------------------------------------- |
917: for (i=0; i < n_coarse; i++) |
[...] |
939: for (i=thread_start; i < thread_stop; i++) |
940: { |
941: i1 = pass_array[i]; |
942: P_diag_start[i1] = cnt_nz; |
943: P_offd_start[i1] = cnt_nz_offd; |
944: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
945: { |
946: j1 = S_diag_j[j]; |
947: if (assigned[j1] == pass-1) |
948: { |
949: j_start = P_diag_start[j1]; |
950: j_end = j_start+P_diag_i[j1+1]; |
951: for (k=j_start; k < j_end; k++) |
952: { |
953: k1 = P_diag_pass[pass-1][k]; |
954: if (P_marker[k1] != i1) |
955: { |
956: cnt_nz++; |
957: P_diag_i[i1+1]++; |
958: P_marker[k1] = i1; |
959: } |
960: } |
961: j_start = P_offd_start[j1]; |
962: j_end = j_start+P_offd_i[j1+1]; |
963: for (k=j_start; k < j_end; k++) |
964: { |
965: k1 = P_offd_pass[pass-1][k]; |
966: if (P_marker_offd[k1] != i1) |
967: { |
968: cnt_nz_offd++; |
969: P_offd_i[i1+1]++; |
970: P_marker_offd[k1] = i1; |
[...] |
976: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
977: { |
978: j1 = S_offd_j[j]; |
979: if (assigned_offd[j1] == pass-1) |
980: { |
981: j_start = Pext_start[j1]; |
982: j_end = j_start+Pext_i[j1+1]; |
983: for (k=j_start; k < j_end; k++) |
984: { |
985: k1 = Pext_pass[pass][k]; |
986: if (k1 < 0) |
987: { |
988: if (P_marker[-k1-1] != i1) |
989: { |
990: cnt_nz++; |
991: P_diag_i[i1+1]++; |
992: P_marker[-k1-1] = i1; |
993: } |
994: } |
995: else if (P_marker_offd[k1] != i1) |
996: { |
997: cnt_nz_offd++; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.48 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P5, P6, P7, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.67 |
CQA cycles if no scalar integer | 4.67 |
CQA cycles if FP arith vectorized | 4.67 |
CQA cycles if fully vectorized | 1.04 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 2.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 11.00 |
Nb stores | 3.00 |
Nb stack references | 7.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 4.48 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.33 |
Bottlenecks | P5, P6, P7, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:939-944,par_multi_interp.c:947-947,par_multi_interp.c:970-970,par_multi_interp.c:976-976 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 4.67 |
CQA cycles if no scalar integer | 4.67 |
CQA cycles if FP arith vectorized | 4.67 |
CQA cycles if fully vectorized | 1.04 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.00 |
P1 cycles | 1.00 |
P2 cycles | 1.00 |
P3 cycles | 2.50 |
P4 cycles | 4.67 |
P5 cycles | 4.67 |
P6 cycles | 4.67 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.00 |
P12 cycles | 0.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 11.00 |
Nb stores | 3.00 |
Nb stack references | 7.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 24.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-997 |
Module | exec |
nb instructions | 21 |
nb uops | 21 |
loop length | 104 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.00 | 1.00 | 1.00 | 2.50 | 4.67 | 4.67 | 4.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 2.50 | 1.00 | 1.00 | 1.00 | 2.50 | 4.67 | 4.67 | 4.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.50 |
Dispatch | 4.67 |
Overall L1 | 4.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x150(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
INC %RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0xd0(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 46d531 <hypre_BoomerAMGBuildMultipass.extracted.34+0x691> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x90(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RSI,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDX,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x98(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,(%RDX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,(%RDX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RDX,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 46d16a <hypre_BoomerAMGBuildMultipass.extracted.34+0x2ca> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RDX,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%RDX,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RSI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 46d46c <hypre_BoomerAMGBuildMultipass.extracted.34+0x5cc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
JMP 46d110 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 46d110 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-997 |
Module | exec |
nb instructions | 21 |
nb uops | 21 |
loop length | 104 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 7 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.00 | 1.00 | 1.00 | 2.50 | 4.67 | 4.67 | 4.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
cycles | 2.50 | 1.00 | 1.00 | 1.00 | 2.50 | 4.67 | 4.67 | 4.67 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.50 |
Dispatch | 4.67 |
Overall L1 | 4.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x150(%RBP),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
INC %RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP -0xd0(%RBP),%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JGE 46d531 <hypre_BoomerAMGBuildMultipass.extracted.34+0x691> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV -0x90(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RSI,-0x150(%RBP) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV (%RDX,%RSI,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV -0x98(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RAX,(%RDX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV %RCX,(%RDX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RDX,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
JMP 46d16a <hypre_BoomerAMGBuildMultipass.extracted.34+0x2ca> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV (%RDX,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%RDX,%RDI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
CMP %RSI,%R8 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JL 46d46c <hypre_BoomerAMGBuildMultipass.extracted.34+0x5cc> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
JMP 46d110 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
JMP 46d110 <hypre_BoomerAMGBuildMultipass.extracted.34+0x270> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |