Loop Id: 1118 | Module: exec | Source: vector.c:451-452 | Coverage: 0.6% |
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Loop Id: 1118 | Module: exec | Source: vector.c:451-452 | Coverage: 0.6% |
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0x2cd1b0 VMOVUPD -0xc0(%R10,%R15,8),%ZMM1 [1] |
0x2cd1b8 VMOVUPD -0x80(%R10,%R15,8),%ZMM2 [1] |
0x2cd1c0 VMOVUPD -0x40(%R10,%R15,8),%ZMM3 [1] |
0x2cd1c8 VMOVUPD (%R10,%R15,8),%ZMM4 [1] |
0x2cd1cf VFMADD213PD -0xc0(%R11,%R15,8),%ZMM0,%ZMM1 [2] |
0x2cd1d7 VFMADD213PD -0x80(%R11,%R15,8),%ZMM0,%ZMM2 [2] |
0x2cd1df VFMADD213PD -0x40(%R11,%R15,8),%ZMM0,%ZMM3 [2] |
0x2cd1e7 VFMADD213PD (%R11,%R15,8),%ZMM0,%ZMM4 [2] |
0x2cd1ee VMOVUPD %ZMM1,-0xc0(%R11,%R15,8) [2] |
0x2cd1f6 VMOVUPD %ZMM2,-0x80(%R11,%R15,8) [2] |
0x2cd1fe VMOVUPD %ZMM3,-0x40(%R11,%R15,8) [2] |
0x2cd206 VMOVUPD %ZMM4,(%R11,%R15,8) [2] |
0x2cd20d ADD $0x20,%R15 |
0x2cd211 CMP %R15,%R9 |
0x2cd214 JNE 2cd1b0 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 451 - 452 |
-------------------------------------------------------------------------------- |
451: for (i = 0; i < size; i++) |
452: y_data[i] += alpha * x_data[i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.67 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..16#0x2cd040 |
Source | vector.c:451-452 |
Source loop unroll info | unrolled by 32 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 32 |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 6.67 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 6.67 |
P5 cycles | 6.67 |
P6 cycles | 6.67 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 15.00 |
Nb uops | 18.00 |
Nb loads | 8.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 9.60 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 115.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 256.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 1.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.67 |
Bottlenecks | P5, P6, P7, |
Function | .omp_outlined..16#0x2cd040 |
Source | vector.c:451-452 |
Source loop unroll info | unrolled by 32 |
Source loop unroll confidence level | high |
Unroll/vectorization loop type | main |
Unroll factor | 32 |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 6.67 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 0.50 |
P0 cycles | 0.50 |
P1 cycles | 0.25 |
P2 cycles | 0.25 |
P3 cycles | 0.50 |
P4 cycles | 6.67 |
P5 cycles | 6.67 |
P6 cycles | 6.67 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 4.00 |
P12 cycles | 4.00 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | 1 |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 15.00 |
Nb uops | 18.00 |
Nb loads | 8.00 |
Nb stores | 4.00 |
Nb stack references | 0.00 |
FLOP/cycle | 9.60 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 115.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 512.00 |
Bytes stored | 256.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | 100.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 100.00 |
Vector-efficiency ratio load | 100.00 |
Vector-efficiency ratio store | 100.00 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 100.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | .omp_outlined..16#0x2cd040 |
Source file and lines | vector.c:451-452 |
Module | exec |
nb instructions | 15 |
nb uops | 18 |
loop length | 102 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 5 |
nb stack references | 0 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 4.00 | 4.00 | 4.00 | 2.00 | 2.00 | 0.00 | 0.00 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 6.67 | 6.67 | 6.67 | 4.00 | 4.00 | 0.00 | 0.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 3.00 |
Dispatch | 6.67 |
Data deps. | 1.00 |
Overall L1 | 6.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD -0xc0(%R10,%R15,8),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD -0x80(%R10,%R15,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD -0x40(%R10,%R15,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%R10,%R15,8),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFMADD213PD -0xc0(%R11,%R15,8),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD -0x80(%R11,%R15,8),%ZMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD -0x40(%R11,%R15,8),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD (%R11,%R15,8),%ZMM0,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVUPD %ZMM1,-0xc0(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM2,-0x80(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM3,-0x40(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM4,(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x20,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 2cd1b0 <.omp_outlined..16+0x170> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | .omp_outlined..16#0x2cd040 |
Source file and lines | vector.c:451-452 |
Module | exec |
nb instructions | 15 |
nb uops | 18 |
loop length | 102 |
used x86 registers | 4 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 5 |
nb stack references | 0 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 4.00 | 4.00 | 4.00 | 2.00 | 2.00 | 0.00 | 0.00 | 4.00 | 4.00 |
cycles | 0.50 | 0.50 | 0.25 | 0.25 | 0.50 | 6.67 | 6.67 | 6.67 | 4.00 | 4.00 | 0.00 | 0.00 | 4.00 | 4.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00 |
Front-end | 3.00 |
Dispatch | 6.67 |
Data deps. | 1.00 |
Overall L1 | 6.67 |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | 100% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVUPD -0xc0(%R10,%R15,8),%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD -0x80(%R10,%R15,8),%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD -0x40(%R10,%R15,8),%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVUPD (%R10,%R15,8),%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFMADD213PD -0xc0(%R11,%R15,8),%ZMM0,%ZMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD -0x80(%R11,%R15,8),%ZMM0,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD -0x40(%R11,%R15,8),%ZMM0,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VFMADD213PD (%R11,%R15,8),%ZMM0,%ZMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 1 |
VMOVUPD %ZMM1,-0xc0(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM2,-0x80(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM3,-0x40(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
VMOVUPD %ZMM4,(%R11,%R15,8) | 2 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 1 | 1 | 5 | 2 |
ADD $0x20,%R15 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R15,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JNE 2cd1b0 <.omp_outlined..16+0x170> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |