Loop Id: 5889 | Module: exec | Source: csr_matvec.c:248-263 [...] | Coverage: 0.9% |
---|
Loop Id: 5889 | Module: exec | Source: csr_matvec.c:248-263 [...] | Coverage: 0.9% |
---|
0x58d1d3 MOVSD %XMM0,(%RAX,%RDI,8) |
0x58d1d8 LEA 0x1(%RSI),%RDI |
0x58d1dc CMP %R12,%RSI |
0x58d1df MOV %RDI,%RSI |
0x58d1e2 JE 58ea84 |
0x58d1e8 LEA (%RBX,%RSI,1),%RDI |
0x58d1ec MOV (%R13,%RDI,8),%R8 |
0x58d1f1 MOV 0x8(%R13,%RDI,8),%R9 |
0x58d1f6 XORPD %XMM0,%XMM0 |
0x58d1fa SUB %R8,%R9 |
0x58d1fd JLE 58d1d3 |
0x58d1ff CMP $0x8,%R9 |
0x58d203 JB 58d2cb |
0x58d209 MOV %R9,%R10 |
0x58d20c SHR $0x3,%R10 |
0x58d210 LEA (,%R8,8),%R11 |
0x58d218 NOPL (%RAX,%RAX,1) |
(5890) 0x58d220 MOV 0x10(%RDX,%R11,1),%R15 |
(5890) 0x58d225 MOVSD (%RCX,%R15,8),%XMM1 |
(5890) 0x58d22b MOV 0x18(%RDX,%R11,1),%R15 |
(5890) 0x58d230 MOVHPD (%RCX,%R15,8),%XMM1 |
(5890) 0x58d236 MOV 0x30(%RDX,%R11,1),%R15 |
(5890) 0x58d23b MOVSD (%RCX,%R15,8),%XMM2 |
(5890) 0x58d241 MOV 0x38(%RDX,%R11,1),%R15 |
(5890) 0x58d246 MOVHPD (%RCX,%R15,8),%XMM2 |
(5890) 0x58d24c MOV (%RDX,%R11,1),%R15 |
(5890) 0x58d250 MOVSD (%RCX,%R15,8),%XMM3 |
(5890) 0x58d256 MOV 0x8(%RDX,%R11,1),%R15 |
(5890) 0x58d25b MOVHPD (%RCX,%R15,8),%XMM3 |
(5890) 0x58d261 MOV 0x20(%RDX,%R11,1),%R15 |
(5890) 0x58d266 MOVSD (%RCX,%R15,8),%XMM4 |
(5890) 0x58d26c MOV 0x28(%RDX,%R11,1),%R15 |
(5890) 0x58d271 MOVHPD (%RCX,%R15,8),%XMM4 |
(5890) 0x58d277 MOVUPD 0x10(%R14,%R11,1),%XMM5 |
(5890) 0x58d27e MULPD %XMM5,%XMM1 |
(5890) 0x58d282 MOVUPD 0x30(%R14,%R11,1),%XMM5 |
(5890) 0x58d289 MULPD %XMM5,%XMM2 |
(5890) 0x58d28d MOVUPD (%R14,%R11,1),%XMM5 |
(5890) 0x58d293 ADDPD %XMM1,%XMM2 |
(5890) 0x58d297 MOVUPD 0x20(%R14,%R11,1),%XMM1 |
(5890) 0x58d29e MULPD %XMM5,%XMM3 |
(5890) 0x58d2a2 MULPD %XMM1,%XMM4 |
(5890) 0x58d2a6 ADDPD %XMM3,%XMM4 |
(5890) 0x58d2aa ADDPD %XMM2,%XMM4 |
(5890) 0x58d2ae MOVAPD %XMM4,%XMM1 |
(5890) 0x58d2b2 UNPCKHPD %XMM4,%XMM1 |
(5890) 0x58d2b6 ADDSD %XMM4,%XMM1 |
(5890) 0x58d2ba ADDSD %XMM1,%XMM0 |
(5890) 0x58d2be ADD $0x40,%R11 |
(5890) 0x58d2c2 DEC %R10 |
(5890) 0x58d2c5 JNE 58d220 |
0x58d2cb MOV %R9D,%R10D |
0x58d2ce AND $0x7,%R10D |
0x58d2d2 DEC %R10 |
0x58d2d5 CMP $0x6,%R10 |
0x58d2d9 JA 58d1d3 |
/beegfs/hackathon/users/eoseret/qaas_runs/170-859-5251/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 248 - 263 |
-------------------------------------------------------------------------------- |
248: hypre_assert(iBegin <= iEnd); |
[...] |
256: for (i = iBegin; i < iEnd; i++) |
257: { |
258: tempx = 0.0; |
259: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
260: { |
261: tempx += A_data[jj] * x_data[A_j[jj]]; |
262: } |
263: y_data[i] = tempx; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.67 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
Source | csr_matvec.c:248-248,csr_matvec.c:256-256,csr_matvec.c:259-259,csr_matvec.c:263-263 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.33 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 3.33 |
CQA cycles if fully vectorized | 0.42 |
Front-end cycles | 3.33 |
DIV/SQRT cycles | 2.75 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 22.00 |
Nb uops | 20.00 |
Nb loads | 2.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 16.67 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 14.58 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 16.67 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.67 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.21 |
Bottlenecks | micro-operation queue, |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
Source | csr_matvec.c:248-248,csr_matvec.c:256-256,csr_matvec.c:259-259,csr_matvec.c:263-263 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.33 |
CQA cycles if no scalar integer | 2.00 |
CQA cycles if FP arith vectorized | 3.33 |
CQA cycles if fully vectorized | 0.42 |
Front-end cycles | 3.33 |
DIV/SQRT cycles | 2.75 |
P0 cycles | 2.75 |
P1 cycles | 2.75 |
P2 cycles | 2.75 |
P3 cycles | 2.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.00 |
P11 cycles | 0.50 |
P12 cycles | 0.50 |
P13 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | NA |
Stall cycles (UFS) | NA |
Nb insns | 22.00 |
Nb uops | 20.00 |
Nb loads | 2.00 |
Nb stores | 1.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.20 |
Bytes prefetched | 0.00 |
Bytes loaded | 16.00 |
Bytes stored | 8.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 16.67 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 33.33 |
Vector-efficiency ratio all | 14.58 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 16.67 |
Path / |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
Source file and lines | csr_matvec.c:248-263 |
Module | exec |
nb instructions | 22 |
nb uops | 20 |
loop length | 97 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.33 cycles |
front end | 3.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.33 |
Dispatch | 2.75 |
Overall L1 | 3.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 33% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSD %XMM0,(%RAX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%RSI),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R12,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 58ea84 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1a84> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%RBX,%RSI,1),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%R13,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%R13,%RDI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XORPD %XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R8,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 58d1d3 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1d3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 58d2cb <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x2cb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R10 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R9D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 58d1d3 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1d3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
Source file and lines | csr_matvec.c:248-263 |
Module | exec |
nb instructions | 22 |
nb uops | 20 |
loop length | 97 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 1 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 3.33 cycles |
front end | 3.33 cycles |
ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
cycles | 2.75 | 2.75 | 2.75 | 2.75 | 2.00 | 1.00 | 1.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.50 | 0.50 |
Cycles executing div or sqrt instructions | NA |
Front-end | 3.33 |
Dispatch | 2.75 |
Overall L1 | 3.33 |
all | 0% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 50% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 33% |
all | 12% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 18% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 14% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 16% |
Instruction | Nb FU | ALU0/BRU0 | ALU1 | ALU2 | ALU3 | BRU1 | AGU0 | AGU1 | AGU2 | FP0 | FP1 | FP2 | FP3 | FP4 | FP5 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOVSD %XMM0,(%RAX,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 1 | 1 |
LEA 0x1(%RSI),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP %R12,%RSI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV %RDI,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JE 58ea84 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1a84> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
LEA (%RBX,%RSI,1),%RDI | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
MOV (%R13,%RDI,8),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
MOV 0x8(%R13,%RDI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.33 |
XORPD %XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB %R8,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JLE 58d1d3 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1d3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
CMP $0x8,%R9 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JB 58d2cb <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x2cb> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |
MOV %R9,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SHR $0x3,%R10 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
LEA (,%R8,8),%R11 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
NOPL (%RAX,%RAX,1) | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.09 |
MOV %R9D,%R10D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
AND $0x7,%R10D | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
DEC %R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
CMP $0x6,%R10 | 1 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
JA 58d1d3 <hypre_CSRMatrixMatvecOutOfPlace.extracted+0x1d3> | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50-1 |