Loop Id: 463 | Module: libparcsr_ls.so | Source: ams.c:3388-3389 | Coverage: 0.02% |
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Loop Id: 463 | Module: libparcsr_ls.so | Source: ams.c:3388-3389 | Coverage: 0.02% |
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0x23510 VMOVSD (%R12,%RDI,8),%XMM1 [1] |
0x23516 VANDPD %XMM5,%XMM1,%XMM1 |
0x2351a VADDSD %XMM1,%XMM0,%XMM0 |
0x2351e INC %RDI |
0x23521 CMP %RDI,%R10 |
0x23524 JNE 23510 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3388 - 3389 |
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3388: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
3389: l1_norm[i] += fabs(A_diag_data[j]); |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 3.69 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 3.60 |
Bottlenecks | |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3388-3389 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | peel/tail |
Unroll factor | 1 |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 3.00 |
CQA cycles if FP arith vectorized | 0.81 |
CQA cycles if fully vectorized | 0.38 |
Front-end cycles | 0.83 |
DIV/SQRT cycles | 0.83 |
P0 cycles | 0.83 |
P1 cycles | 0.33 |
P2 cycles | 0.33 |
P3 cycles | 0.00 |
P4 cycles | 0.83 |
P5 cycles | 0.50 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 3.11 |
Stall cycles (UFS) | 1.43 |
Nb insns | 6.00 |
Nb uops | 5.00 |
Nb loads | 1.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.33 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 2.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 8.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 16.67 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 3.69 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 3.60 |
Bottlenecks | |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source | ams.c:3388-3389 |
Source loop unroll info | unrolled by 4 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | peel/tail |
Unroll factor | 1 |
CQA cycles | 3.00 |
CQA cycles if no scalar integer | 3.00 |
CQA cycles if FP arith vectorized | 0.81 |
CQA cycles if fully vectorized | 0.38 |
Front-end cycles | 0.83 |
DIV/SQRT cycles | 0.83 |
P0 cycles | 0.83 |
P1 cycles | 0.33 |
P2 cycles | 0.33 |
P3 cycles | 0.00 |
P4 cycles | 0.83 |
P5 cycles | 0.50 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 0.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 3.11 |
Stall cycles (UFS) | 1.43 |
Nb insns | 6.00 |
Nb uops | 5.00 |
Nb loads | 1.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.33 |
Nb FLOP add-sub | 1.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 2.67 |
Bytes prefetched | 0.00 |
Bytes loaded | 8.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 33.33 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 16.67 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 25.00 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3388-3389 |
Module | libparcsr_ls.so |
nb instructions | 6 |
nb uops | 5 |
loop length | 22 |
used x86 registers | 3 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 0.83 cycles |
front end | 0.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.83 | 0.83 | 0.33 | 0.33 | 0.00 | 0.83 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 0.33 |
cycles | 0.83 | 0.83 | 0.33 | 0.33 | 0.00 | 0.83 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 0.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 3.11 |
Stall cycles | 1.43 |
ROB full (events) | 1.97 |
Front-end | 0.83 |
Dispatch | 0.83 |
Data deps. | 3.00 |
Overall L1 | 3.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R12,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM5,%XMM1,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 23510 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1ad0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParCSRComputeL1NormsThreads.extracted |
Source file and lines | ams.c:3388-3389 |
Module | libparcsr_ls.so |
nb instructions | 6 |
nb uops | 5 |
loop length | 22 |
used x86 registers | 3 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 0.83 cycles |
front end | 0.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.83 | 0.83 | 0.33 | 0.33 | 0.00 | 0.83 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 0.33 |
cycles | 0.83 | 0.83 | 0.33 | 0.33 | 0.00 | 0.83 | 0.50 | 0.00 | 0.00 | 0.00 | 0.00 | 0.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 3.11 |
Stall cycles | 1.43 |
ROB full (events) | 1.97 |
Front-end | 0.83 |
Dispatch | 0.83 |
Data deps. | 3.00 |
Overall L1 | 3.00 |
all | 33% |
load | 0% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 16% |
load | 12% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVSD (%R12,%RDI,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VANDPD %XMM5,%XMM1,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
INC %RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 23510 <hypre_ParCSRComputeL1NormsThreads.extracted+0x1ad0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |