Loop Id: 988 | Module: exec | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.07% |
---|
Loop Id: 988 | Module: exec | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.07% |
---|
0x445300 MOV -0x80(%RBP),%RSI |
0x445304 INC %RSI |
0x445307 CMP -0xc8(%RBP),%RSI |
0x44530e JGE 445811 |
0x445314 MOV -0x88(%RBP),%RDX |
0x44531b MOV %RSI,-0x80(%RBP) |
0x44531f MOV (%RDX,%RSI,8),%RSI |
0x445323 MOV -0xa8(%RBP),%RDX |
0x44532a MOV (%RDX,%RSI,8),%R8 |
0x44532e MOV %RSI,%RDI |
0x445331 NOT %RDI |
0x445334 MOV %RSI,-0x50(%RBP) |
0x445338 JMP 445352 |
(991) 0x445340 MOV -0x38(%RBP),%R10 |
(991) 0x445344 INC %R8 |
(991) 0x445347 MOV -0xa8(%RBP),%RDX |
(991) 0x44534e MOV -0x50(%RBP),%RSI |
(991) 0x445352 CMP 0x8(%RDX,%RSI,8),%R8 |
(991) 0x445357 JGE 445640 |
(991) 0x44535d MOV -0x128(%RBP),%RDX |
(991) 0x445364 MOV (%RDX,%R8,8),%R14 |
(991) 0x445368 MOV -0x118(%RBP),%RDX |
(991) 0x44536f CMP %R10,(%RDX,%R14,8) |
(991) 0x445373 JNE 445344 |
(991) 0x445375 MOV -0x58(%RBP),%RDX |
(991) 0x445379 MOV 0x8(%RDX,%R14,8),%R10 |
(991) 0x44537e TEST %R10,%R10 |
(991) 0x445381 JLE 4454d7 |
(991) 0x445387 MOV -0x90(%RBP),%RDX |
(991) 0x44538e MOV %R14,-0x30(%RBP) |
(991) 0x445392 MOV (%RDX,%R14,8),%R11 |
(991) 0x445396 ADD %R11,%R10 |
(991) 0x445399 MOV -0x40(%RBP),%RDX |
(991) 0x44539d MOV -0x8(%RDX,%R12,8),%RSI |
(991) 0x4453a2 LEA 0x1(%R11),%RDX |
(991) 0x4453a6 CMP %RDX,%R10 |
(991) 0x4453a9 CMOVLE %RDX,%R10 |
(991) 0x4453ad MOV %R10,%RDX |
(991) 0x4453b0 SUB %R11,%RDX |
(991) 0x4453b3 CMP $0x4,%RDX |
(991) 0x4453b7 MOV %RDX,-0xd0(%RBP) |
(991) 0x4453be JAE 44540b |
(991) 0x4453c0 MOV -0xd0(%RBP),%R9 |
(991) 0x4453c7 MOV %R9,%RDX |
(991) 0x4453ca AND $-0x4,%RDX |
(991) 0x4453ce CMP %R9,%RDX |
(991) 0x4453d1 JAE 4454d3 |
(991) 0x4453d7 ADD %RDX,%R11 |
(991) 0x4453da MOV -0x30(%RBP),%R14 |
(991) 0x4453de JMP 4453ec |
(994) 0x4453e0 INC %R11 |
(994) 0x4453e3 CMP %R11,%R10 |
(994) 0x4453e6 JE 4454d7 |
(994) 0x4453ec MOV (%RSI,%R11,8),%RDX |
(994) 0x4453f0 CMP %RDI,(%RBX,%RDX,8) |
(994) 0x4453f4 JE 4453e0 |
(994) 0x4453f6 MOV -0x40(%RBP),%R9 |
(994) 0x4453fa MOV (%R9,%R12,8),%R9 |
(994) 0x4453fe MOV %RDX,(%R9,%RAX,8) |
(994) 0x445402 INC %RAX |
(994) 0x445405 MOV %RDI,(%RBX,%RDX,8) |
(994) 0x445409 JMP 4453e0 |
(991) 0x44540b SHR $0x2,%RDX |
(991) 0x44540f LEA 0x18(%RSI,%R11,8),%R13 |
(991) 0x445414 JMP 445429 |
(995) 0x445420 ADD $0x20,%R13 |
(995) 0x445424 DEC %RDX |
(995) 0x445427 JE 4453c0 |
(995) 0x445429 MOV -0x18(%R13),%R14 |
(995) 0x44542d CMP %RDI,(%RBX,%R14,8) |
(995) 0x445431 JNE 445460 |
(995) 0x445433 MOV -0x10(%R13),%R14 |
(995) 0x445437 CMP %RDI,(%RBX,%R14,8) |
(995) 0x44543b JNE 44547d |
(995) 0x44543d MOV -0x8(%R13),%R14 |
(995) 0x445441 CMP %RDI,(%RBX,%R14,8) |
(995) 0x445445 JNE 44549a |
(995) 0x445447 MOV (%R13),%R14 |
(995) 0x44544b CMP %RDI,(%RBX,%R14,8) |
(995) 0x44544f JE 445420 |
(995) 0x445451 JMP 4454bb |
(995) 0x445460 MOV -0x40(%RBP),%R9 |
(995) 0x445464 MOV (%R9,%R12,8),%R9 |
(995) 0x445468 MOV %R14,(%R9,%RAX,8) |
(995) 0x44546c INC %RAX |
(995) 0x44546f MOV %RDI,(%RBX,%R14,8) |
(995) 0x445473 MOV -0x10(%R13),%R14 |
(995) 0x445477 CMP %RDI,(%RBX,%R14,8) |
(995) 0x44547b JE 44543d |
(995) 0x44547d MOV -0x40(%RBP),%R9 |
(995) 0x445481 MOV (%R9,%R12,8),%R9 |
(995) 0x445485 MOV %R14,(%R9,%RAX,8) |
(995) 0x445489 INC %RAX |
(995) 0x44548c MOV %RDI,(%RBX,%R14,8) |
(995) 0x445490 MOV -0x8(%R13),%R14 |
(995) 0x445494 CMP %RDI,(%RBX,%R14,8) |
(995) 0x445498 JE 445447 |
(995) 0x44549a MOV -0x40(%RBP),%R9 |
(995) 0x44549e MOV (%R9,%R12,8),%R9 |
(995) 0x4454a2 MOV %R14,(%R9,%RAX,8) |
(995) 0x4454a6 INC %RAX |
(995) 0x4454a9 MOV %RDI,(%RBX,%R14,8) |
(995) 0x4454ad MOV (%R13),%R14 |
(995) 0x4454b1 CMP %RDI,(%RBX,%R14,8) |
(995) 0x4454b5 JE 445420 |
(995) 0x4454bb MOV -0x40(%RBP),%R9 |
(995) 0x4454bf MOV (%R9,%R12,8),%R9 |
(995) 0x4454c3 MOV %R14,(%R9,%RAX,8) |
(995) 0x4454c7 INC %RAX |
(995) 0x4454ca MOV %RDI,(%RBX,%R14,8) |
(995) 0x4454ce JMP 445420 |
(991) 0x4454d3 MOV -0x30(%RBP),%R14 |
(991) 0x4454d7 MOV -0x60(%RBP),%RDX |
(991) 0x4454db MOV 0x8(%RDX,%R14,8),%R10 |
(991) 0x4454e0 TEST %R10,%R10 |
(991) 0x4454e3 JLE 445340 |
(991) 0x4454e9 MOV -0x98(%RBP),%RDX |
(991) 0x4454f0 MOV (%RDX,%R14,8),%R9 |
(991) 0x4454f4 ADD %R9,%R10 |
(991) 0x4454f7 MOV -0x48(%RBP),%RDX |
(991) 0x4454fb MOV -0x8(%RDX,%R12,8),%RSI |
(991) 0x445500 LEA 0x1(%R9),%RDX |
(991) 0x445504 CMP %RDX,%R10 |
(991) 0x445507 CMOVLE %RDX,%R10 |
(991) 0x44550b MOV %R10,%R11 |
(991) 0x44550e SUB %R9,%R11 |
(991) 0x445511 CMP $0x4,%R11 |
(991) 0x445515 MOV %R11,-0x30(%RBP) |
(991) 0x445519 JAE 44556b |
(991) 0x44551b MOV -0x30(%RBP),%RDX |
(991) 0x44551f MOV %RDX,%R11 |
(991) 0x445522 AND $-0x4,%R11 |
(991) 0x445526 CMP %RDX,%R11 |
(991) 0x445529 JAE 445340 |
(991) 0x44552f ADD %R11,%R9 |
(991) 0x445532 JMP 44554c |
(992) 0x445540 INC %R9 |
(992) 0x445543 CMP %R9,%R10 |
(992) 0x445546 JE 445340 |
(992) 0x44554c MOV (%RSI,%R9,8),%RDX |
(992) 0x445550 CMP %RDI,(%R15,%RDX,8) |
(992) 0x445554 JE 445540 |
(992) 0x445556 MOV -0x48(%RBP),%R11 |
(992) 0x44555a MOV (%R11,%R12,8),%R11 |
(992) 0x44555e MOV %RDX,(%R11,%RCX,8) |
(992) 0x445562 INC %RCX |
(992) 0x445565 MOV %RDI,(%R15,%RDX,8) |
(992) 0x445569 JMP 445540 |
(991) 0x44556b SHR $0x2,%R11 |
(991) 0x44556f LEA 0x18(%RSI,%R9,8),%R14 |
(991) 0x445574 JMP 445589 |
(993) 0x445580 ADD $0x20,%R14 |
(993) 0x445584 DEC %R11 |
(993) 0x445587 JE 44551b |
(993) 0x445589 MOV -0x18(%R14),%R13 |
(993) 0x44558d CMP %RDI,(%R15,%R13,8) |
(993) 0x445591 JNE 4455c0 |
(993) 0x445593 MOV -0x10(%R14),%R13 |
(993) 0x445597 CMP %RDI,(%R15,%R13,8) |
(993) 0x44559b JNE 4455dd |
(993) 0x44559d MOV -0x8(%R14),%R13 |
(993) 0x4455a1 CMP %RDI,(%R15,%R13,8) |
(993) 0x4455a5 JNE 4455fa |
(993) 0x4455a7 MOV (%R14),%R13 |
(993) 0x4455aa CMP %RDI,(%R15,%R13,8) |
(993) 0x4455ae JE 445580 |
(993) 0x4455b0 JMP 44561a |
(993) 0x4455c0 MOV -0x48(%RBP),%RDX |
(993) 0x4455c4 MOV (%RDX,%R12,8),%RDX |
(993) 0x4455c8 MOV %R13,(%RDX,%RCX,8) |
(993) 0x4455cc INC %RCX |
(993) 0x4455cf MOV %RDI,(%R15,%R13,8) |
(993) 0x4455d3 MOV -0x10(%R14),%R13 |
(993) 0x4455d7 CMP %RDI,(%R15,%R13,8) |
(993) 0x4455db JE 44559d |
(993) 0x4455dd MOV -0x48(%RBP),%RDX |
(993) 0x4455e1 MOV (%RDX,%R12,8),%RDX |
(993) 0x4455e5 MOV %R13,(%RDX,%RCX,8) |
(993) 0x4455e9 INC %RCX |
(993) 0x4455ec MOV %RDI,(%R15,%R13,8) |
(993) 0x4455f0 MOV -0x8(%R14),%R13 |
(993) 0x4455f4 CMP %RDI,(%R15,%R13,8) |
(993) 0x4455f8 JE 4455a7 |
(993) 0x4455fa MOV -0x48(%RBP),%RDX |
(993) 0x4455fe MOV (%RDX,%R12,8),%RDX |
(993) 0x445602 MOV %R13,(%RDX,%RCX,8) |
(993) 0x445606 INC %RCX |
(993) 0x445609 MOV %RDI,(%R15,%R13,8) |
(993) 0x44560d MOV (%R14),%R13 |
(993) 0x445610 CMP %RDI,(%R15,%R13,8) |
(993) 0x445614 JE 445580 |
(993) 0x44561a MOV -0x48(%RBP),%RDX |
(993) 0x44561e MOV (%RDX,%R12,8),%RDX |
(993) 0x445622 MOV %R13,(%RDX,%RCX,8) |
(993) 0x445626 INC %RCX |
(993) 0x445629 MOV %RDI,(%R15,%R13,8) |
(993) 0x44562d JMP 445580 |
0x445640 MOV -0xa0(%RBP),%RDX |
0x445647 MOV -0x50(%RBP),%RSI |
0x44564b MOV (%RDX,%RSI,8),%R8 |
0x44564f MOV 0x8(%RDX,%RSI,8),%RDX |
0x445654 CMP %RDX,%R8 |
0x445657 JL 44566c |
0x445659 JMP 445300 |
(989) 0x445660 INC %R8 |
(989) 0x445663 CMP %RDX,%R8 |
(989) 0x445666 JGE 445300 |
(989) 0x44566c MOV -0x130(%RBP),%RSI |
(989) 0x445673 MOV (%RSI,%R8,8),%R9 |
(989) 0x445677 MOV -0x120(%RBP),%RSI |
(989) 0x44567e CMP %R10,(%RSI,%R9,8) |
(989) 0x445682 JNE 445660 |
(989) 0x445684 MOV -0x110(%RBP),%RSI |
(989) 0x44568b MOV 0x8(%RSI,%R9,8),%RSI |
(989) 0x445690 TEST %RSI,%RSI |
(989) 0x445693 JLE 445660 |
(989) 0x445695 MOV -0x100(%RBP),%RDX |
(989) 0x44569c MOV (%RDX,%R9,8),%R9 |
(989) 0x4456a0 ADD %R9,%RSI |
(989) 0x4456a3 MOV -0x108(%RBP),%RDX |
(989) 0x4456aa MOV (%RDX,%R12,8),%R11 |
(989) 0x4456ae LEA 0x1(%R9),%R10 |
(989) 0x4456b2 CMP %R10,%RSI |
(989) 0x4456b5 CMOVLE %R10,%RSI |
(989) 0x4456b9 MOV %RSI,%RDX |
(989) 0x4456bc SUB %R9,%RDX |
(989) 0x4456bf CMP %R10,%RSI |
(989) 0x4456c2 MOV %R11,-0x30(%RBP) |
(989) 0x4456c6 JNE 44570e |
(989) 0x4456c8 XOR %R11D,%R11D |
(989) 0x4456cb TEST $0x1,%DL |
(989) 0x4456ce MOV -0x38(%RBP),%R10 |
(989) 0x4456d2 JE 4457f0 |
(989) 0x4456d8 ADD %R11,%R9 |
(989) 0x4456db MOV -0x30(%RBP),%RDX |
(989) 0x4456df MOV (%RDX,%R9,8),%RDX |
(989) 0x4456e3 TEST %RDX,%RDX |
(989) 0x4456e6 JS 4457c7 |
(989) 0x4456ec CMP %RDI,(%R15,%RDX,8) |
(989) 0x4456f0 JE 4457f0 |
(989) 0x4456f6 MOV -0x48(%RBP),%RSI |
(989) 0x4456fa MOV (%RSI,%R12,8),%RSI |
(989) 0x4456fe MOV %RDX,(%RSI,%RCX,8) |
(989) 0x445702 INC %RCX |
(989) 0x445705 MOV %RDI,(%R15,%RDX,8) |
(989) 0x445709 JMP 4457f0 |
(989) 0x44570e MOV %RDX,%RSI |
(989) 0x445711 AND $-0x2,%RSI |
(989) 0x445715 LEA 0x8(%R11,%R9,8),%R10 |
(989) 0x44571a XOR %R11D,%R11D |
(989) 0x44571d JMP 445729 |
(990) 0x445720 ADD $0x2,%R11 |
(990) 0x445724 CMP %R11,%RSI |
(990) 0x445727 JE 4456cb |
(990) 0x445729 MOV -0x8(%R10,%R11,8),%R14 |
(990) 0x44572e TEST %R14,%R14 |
(990) 0x445731 JS 445750 |
(990) 0x445733 CMP %RDI,(%R15,%R14,8) |
(990) 0x445737 JE 445770 |
(990) 0x445739 MOV -0x48(%RBP),%R13 |
(990) 0x44573d MOV (%R13,%R12,8),%R13 |
(990) 0x445742 MOV %R14,(%R13,%RCX,8) |
(990) 0x445747 INC %RCX |
(990) 0x44574a MOV %RDI,(%R15,%R14,8) |
(990) 0x44574e JMP 445770 |
(990) 0x445750 NOT %R14 |
(990) 0x445753 CMP %RDI,(%RBX,%R14,8) |
(990) 0x445757 JE 445770 |
(990) 0x445759 MOV -0x40(%RBP),%R13 |
(990) 0x44575d MOV (%R13,%R12,8),%R13 |
(990) 0x445762 MOV %R14,(%R13,%RAX,8) |
(990) 0x445767 INC %RAX |
(990) 0x44576a MOV %RDI,(%RBX,%R14,8) |
(990) 0x44576e XCHG %AX,%AX |
(990) 0x445770 MOV (%R10,%R11,8),%R14 |
(990) 0x445774 TEST %R14,%R14 |
(990) 0x445777 JS 4457a0 |
(990) 0x445779 CMP %RDI,(%R15,%R14,8) |
(990) 0x44577d JE 445720 |
(990) 0x44577f MOV -0x48(%RBP),%R13 |
(990) 0x445783 MOV (%R13,%R12,8),%R13 |
(990) 0x445788 MOV %R14,(%R13,%RCX,8) |
(990) 0x44578d INC %RCX |
(990) 0x445790 MOV %RDI,(%R15,%R14,8) |
(990) 0x445794 JMP 445720 |
(990) 0x4457a0 NOT %R14 |
(990) 0x4457a3 CMP %RDI,(%RBX,%R14,8) |
(990) 0x4457a7 JE 445720 |
(990) 0x4457ad MOV -0x40(%RBP),%R13 |
(990) 0x4457b1 MOV (%R13,%R12,8),%R13 |
(990) 0x4457b6 MOV %R14,(%R13,%RAX,8) |
(990) 0x4457bb INC %RAX |
(990) 0x4457be MOV %RDI,(%RBX,%R14,8) |
(990) 0x4457c2 JMP 445720 |
(989) 0x4457c7 NOT %RDX |
(989) 0x4457ca CMP %RDI,(%RBX,%RDX,8) |
(989) 0x4457ce JE 4457f0 |
(989) 0x4457d0 MOV -0x40(%RBP),%RSI |
(989) 0x4457d4 MOV (%RSI,%R12,8),%RSI |
(989) 0x4457d8 MOV %RDX,(%RSI,%RAX,8) |
(989) 0x4457dc INC %RAX |
(989) 0x4457df MOV %RDI,(%RBX,%RDX,8) |
(989) 0x4457e3 NOPW %CS:(%RAX,%RAX,1) |
(989) 0x4457f0 MOV -0xa0(%RBP),%RDX |
(989) 0x4457f7 MOV -0x50(%RBP),%RSI |
(989) 0x4457fb MOV 0x8(%RDX,%RSI,8),%RDX |
(989) 0x445800 INC %R8 |
(989) 0x445803 CMP %RDX,%R8 |
(989) 0x445806 JL 44566c |
0x44580c JMP 445300 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 1125 |
-------------------------------------------------------------------------------- |
917: for (i=0; i < n_coarse; i++) |
[...] |
1072: for (i=thread_start; i < thread_stop; i++) |
1073: { |
1074: i1 = pass_array[i]; |
1075: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1076: { |
1077: j1 = S_diag_j[j]; |
1078: if (assigned[j1] == pass-1) |
1079: { |
1080: j_start = P_diag_start[j1]; |
1081: j_end = j_start+P_diag_i[j1+1]; |
1082: for (k=j_start; k < j_end; k++) |
1083: { |
1084: k1 = P_diag_pass[pass-1][k]; |
1085: if (P_marker[k1] != -i1-1) |
1086: { |
1087: P_diag_pass[pass][cnt_nz++] = k1; |
1088: P_marker[k1] = -i1-1; |
1089: } |
1090: } |
1091: j_start = P_offd_start[j1]; |
1092: j_end = j_start+P_offd_i[j1+1]; |
1093: for (k=j_start; k < j_end; k++) |
1094: { |
1095: k1 = P_offd_pass[pass-1][k]; |
1096: if (P_marker_offd[k1] != -i1-1) |
1097: { |
1098: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1099: P_marker_offd[k1] = -i1-1; |
1100: } |
1101: } |
1102: } |
1103: } |
1104: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1105: { |
1106: j1 = S_offd_j[j]; |
1107: if (assigned_offd[j1] == pass-1) |
1108: { |
1109: j_start = Pext_start[j1]; |
1110: j_end = j_start+Pext_i[j1+1]; |
1111: for (k=j_start; k < j_end; k++) |
1112: { |
1113: k1 = Pext_pass[pass][k]; |
1114: if (k1 < 0) |
1115: { |
1116: if (P_marker[-k1-1] != -i1-1) |
1117: { |
1118: P_diag_pass[pass][cnt_nz++] = -k1-1; |
1119: P_marker[-k1-1] = -i1-1; |
1120: } |
1121: } |
1122: else if (P_marker_offd[k1] != -i1-1) |
1123: { |
1124: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1125: P_marker_offd[k1] = -i1-1; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.44 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 3.96 |
Stall cycles (UFS) | 0.30 |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 10.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.43 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.05 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.50 |
CQA cycles if no scalar integer | 3.50 |
CQA cycles if FP arith vectorized | 3.50 |
CQA cycles if fully vectorized | 0.44 |
Front-end cycles | 3.50 |
DIV/SQRT cycles | 1.00 |
P0 cycles | 1.00 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.00 |
P4 cycles | 1.00 |
P5 cycles | 1.00 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 1.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 3.96 |
Stall cycles (UFS) | 0.30 |
Nb insns | 21.00 |
Nb uops | 21.00 |
Nb loads | 10.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.43 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | exec |
nb instructions | 21 |
nb uops | 21 |
loop length | 93 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 3.33 | 3.33 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
cycles | 1.00 | 1.00 | 3.33 | 3.33 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.96 |
Stall cycles | 0.30 |
LM full (events) | 0.80 |
Front-end | 3.50 |
Dispatch | 3.33 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xc8(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 445811 <hypre_BoomerAMGBuildMultipass.extracted.34+0xf91> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 445352 <hypre_BoomerAMGBuildMultipass.extracted.34+0xad2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDX,%RSI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44566c <hypre_BoomerAMGBuildMultipass.extracted.34+0xdec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 445300 <hypre_BoomerAMGBuildMultipass.extracted.34+0xa80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 445300 <hypre_BoomerAMGBuildMultipass.extracted.34+0xa80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | exec |
nb instructions | 21 |
nb uops | 21 |
loop length | 93 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.50 cycles |
front end | 3.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 1.00 | 3.33 | 3.33 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
cycles | 1.00 | 1.00 | 3.33 | 3.33 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 1.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.96 |
Stall cycles | 0.30 |
LM full (events) | 0.80 |
Front-end | 3.50 |
Dispatch | 3.33 |
Overall L1 | 3.50 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xc8(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 445811 <hypre_BoomerAMGBuildMultipass.extracted.34+0xf91> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x88(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x80(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 445352 <hypre_BoomerAMGBuildMultipass.extracted.34+0xad2> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0xa0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDX,%RSI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JL 44566c <hypre_BoomerAMGBuildMultipass.extracted.34+0xdec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 445300 <hypre_BoomerAMGBuildMultipass.extracted.34+0xa80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 445300 <hypre_BoomerAMGBuildMultipass.extracted.34+0xa80> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |