Loop Id: 1544 | Module: libparcsr_ls.so | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.07% |
---|
Loop Id: 1544 | Module: libparcsr_ls.so | Source: par_multi_interp.c:917-1125 [...] | Coverage: 0.07% |
---|
0x6dec0 MOV -0x98(%RBP),%RSI |
0x6dec7 INC %RSI |
0x6deca CMP -0xd8(%RBP),%RSI |
0x6ded1 JGE 6e400 |
0x6ded7 MOV -0x48(%RBP),%RDX |
0x6dedb MOV %RSI,-0x98(%RBP) |
0x6dee2 MOV (%RDX,%RSI,8),%RSI |
0x6dee6 MOV -0xb0(%RBP),%RDX |
0x6deed MOV (%RDX,%RSI,8),%R8 |
0x6def1 MOV %RSI,%RDI |
0x6def4 NOT %RDI |
0x6def7 MOV %RSI,-0x38(%RBP) |
0x6defb JMP 6df1e |
(1547) 0x6df00 MOV -0x30(%RBP),%R12 |
(1547) 0x6df04 NOPW %CS:(%RAX,%RAX,1) |
(1547) 0x6df10 INC %R8 |
(1547) 0x6df13 MOV -0xb0(%RBP),%RDX |
(1547) 0x6df1a MOV -0x38(%RBP),%RSI |
(1547) 0x6df1e CMP 0x8(%RDX,%RSI,8),%R8 |
(1547) 0x6df23 JGE 6e2c0 |
(1547) 0x6df29 MOV -0x128(%RBP),%RDX |
(1547) 0x6df30 MOV (%RDX,%R8,8),%R13 |
(1547) 0x6df34 MOV -0x118(%RBP),%RDX |
(1547) 0x6df3b CMP %R12,(%RDX,%R13,8) |
(1547) 0x6df3f JNE 6df10 |
(1547) 0x6df41 MOV -0x70(%RBP),%RDX |
(1547) 0x6df45 MOV 0x8(%RDX,%R13,8),%R10 |
(1547) 0x6df4a TEST %R10,%R10 |
(1547) 0x6df4d JLE 6e10b |
(1547) 0x6df53 MOV -0x50(%RBP),%RDX |
(1547) 0x6df57 MOV %R13,-0x90(%RBP) |
(1547) 0x6df5e MOV (%RDX,%R13,8),%R11 |
(1547) 0x6df62 ADD %R11,%R10 |
(1547) 0x6df65 MOV -0x60(%RBP),%RDX |
(1547) 0x6df69 MOV -0x8(%RDX,%R14,8),%RSI |
(1547) 0x6df6e LEA 0x1(%R11),%RDX |
(1547) 0x6df72 CMP %RDX,%R10 |
(1547) 0x6df75 CMOVLE %RDX,%R10 |
(1547) 0x6df79 MOV %R10,%RDX |
(1547) 0x6df7c SUB %R11,%RDX |
(1547) 0x6df7f CMP $0x4,%RDX |
(1547) 0x6df83 MOV %RDX,-0xe0(%RBP) |
(1547) 0x6df8a JAE 6e000 |
(1547) 0x6df8c MOV -0xe0(%RBP),%R9 |
(1547) 0x6df93 MOV %R9,%RDX |
(1547) 0x6df96 AND $-0x4,%RDX |
(1547) 0x6df9a CMP %R9,%RDX |
(1547) 0x6df9d JAE 6e100 |
(1547) 0x6dfa3 ADD %RDX,%R11 |
(1547) 0x6dfa6 MOV -0x30(%RBP),%R12 |
(1547) 0x6dfaa MOV -0x90(%RBP),%R13 |
(1547) 0x6dfb1 JMP 6dfcc |
(1550) 0x6dfc0 INC %R11 |
(1550) 0x6dfc3 CMP %R11,%R10 |
(1550) 0x6dfc6 JE 6e10b |
(1550) 0x6dfcc MOV (%RSI,%R11,8),%RDX |
(1550) 0x6dfd0 CMP %RDI,(%RBX,%RDX,8) |
(1550) 0x6dfd4 JE 6dfc0 |
(1550) 0x6dfd6 MOV -0x60(%RBP),%R9 |
(1550) 0x6dfda MOV (%R9,%R14,8),%R9 |
(1550) 0x6dfde MOV %RDX,(%R9,%RAX,8) |
(1550) 0x6dfe2 INC %RAX |
(1550) 0x6dfe5 MOV %RDI,(%RBX,%RDX,8) |
(1550) 0x6dfe9 JMP 6dfc0 |
(1547) 0x6e000 SHR $0x2,%RDX |
(1547) 0x6e004 LEA 0x18(%RSI,%R11,8),%R13 |
(1547) 0x6e009 JMP 6e04d |
(1551) 0x6e040 ADD $0x20,%R13 |
(1551) 0x6e044 DEC %RDX |
(1551) 0x6e047 JE 6df8c |
(1551) 0x6e04d MOV -0x18(%R13),%R12 |
(1551) 0x6e051 CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e055 JNE 6e080 |
(1551) 0x6e057 MOV -0x10(%R13),%R12 |
(1551) 0x6e05b CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e05f JNE 6e09d |
(1551) 0x6e061 MOV -0x8(%R13),%R12 |
(1551) 0x6e065 CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e069 JNE 6e0ba |
(1551) 0x6e06b MOV (%R13),%R12 |
(1551) 0x6e06f CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e073 JE 6e040 |
(1551) 0x6e075 JMP 6e0db |
(1551) 0x6e080 MOV -0x60(%RBP),%R9 |
(1551) 0x6e084 MOV (%R9,%R14,8),%R9 |
(1551) 0x6e088 MOV %R12,(%R9,%RAX,8) |
(1551) 0x6e08c INC %RAX |
(1551) 0x6e08f MOV %RDI,(%RBX,%R12,8) |
(1551) 0x6e093 MOV -0x10(%R13),%R12 |
(1551) 0x6e097 CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e09b JE 6e061 |
(1551) 0x6e09d MOV -0x60(%RBP),%R9 |
(1551) 0x6e0a1 MOV (%R9,%R14,8),%R9 |
(1551) 0x6e0a5 MOV %R12,(%R9,%RAX,8) |
(1551) 0x6e0a9 INC %RAX |
(1551) 0x6e0ac MOV %RDI,(%RBX,%R12,8) |
(1551) 0x6e0b0 MOV -0x8(%R13),%R12 |
(1551) 0x6e0b4 CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e0b8 JE 6e06b |
(1551) 0x6e0ba MOV -0x60(%RBP),%R9 |
(1551) 0x6e0be MOV (%R9,%R14,8),%R9 |
(1551) 0x6e0c2 MOV %R12,(%R9,%RAX,8) |
(1551) 0x6e0c6 INC %RAX |
(1551) 0x6e0c9 MOV %RDI,(%RBX,%R12,8) |
(1551) 0x6e0cd MOV (%R13),%R12 |
(1551) 0x6e0d1 CMP %RDI,(%RBX,%R12,8) |
(1551) 0x6e0d5 JE 6e040 |
(1551) 0x6e0db MOV -0x60(%RBP),%R9 |
(1551) 0x6e0df MOV (%R9,%R14,8),%R9 |
(1551) 0x6e0e3 MOV %R12,(%R9,%RAX,8) |
(1551) 0x6e0e7 INC %RAX |
(1551) 0x6e0ea MOV %RDI,(%RBX,%R12,8) |
(1551) 0x6e0ee JMP 6e040 |
(1547) 0x6e100 MOV -0x30(%RBP),%R12 |
(1547) 0x6e104 MOV -0x90(%RBP),%R13 |
(1547) 0x6e10b MOV -0x78(%RBP),%RDX |
(1547) 0x6e10f MOV 0x8(%RDX,%R13,8),%R10 |
(1547) 0x6e114 TEST %R10,%R10 |
(1547) 0x6e117 JLE 6df10 |
(1547) 0x6e11d MOV -0x58(%RBP),%RDX |
(1547) 0x6e121 MOV (%RDX,%R13,8),%R9 |
(1547) 0x6e125 ADD %R9,%R10 |
(1547) 0x6e128 MOV -0x40(%RBP),%RDX |
(1547) 0x6e12c MOV -0x8(%RDX,%R14,8),%RSI |
(1547) 0x6e131 LEA 0x1(%R9),%RDX |
(1547) 0x6e135 CMP %RDX,%R10 |
(1547) 0x6e138 CMOVLE %RDX,%R10 |
(1547) 0x6e13c MOV %R10,%R11 |
(1547) 0x6e13f SUB %R9,%R11 |
(1547) 0x6e142 CMP $0x4,%R11 |
(1547) 0x6e146 MOV %R11,-0x90(%RBP) |
(1547) 0x6e14d JAE 6e1c0 |
(1547) 0x6e14f MOV -0x90(%RBP),%RDX |
(1547) 0x6e156 MOV %RDX,%R11 |
(1547) 0x6e159 AND $-0x4,%R11 |
(1547) 0x6e15d CMP %RDX,%R11 |
(1547) 0x6e160 JAE 6df00 |
(1547) 0x6e166 ADD %R11,%R9 |
(1547) 0x6e169 MOV -0x30(%RBP),%R12 |
(1547) 0x6e16d JMP 6e18c |
(1548) 0x6e180 INC %R9 |
(1548) 0x6e183 CMP %R9,%R10 |
(1548) 0x6e186 JE 6df10 |
(1548) 0x6e18c MOV (%RSI,%R9,8),%RDX |
(1548) 0x6e190 CMP %RDI,(%R15,%RDX,8) |
(1548) 0x6e194 JE 6e180 |
(1548) 0x6e196 MOV -0x40(%RBP),%R11 |
(1548) 0x6e19a MOV (%R11,%R14,8),%R11 |
(1548) 0x6e19e MOV %RDX,(%R11,%RCX,8) |
(1548) 0x6e1a2 INC %RCX |
(1548) 0x6e1a5 MOV %RDI,(%R15,%RDX,8) |
(1548) 0x6e1a9 JMP 6e180 |
(1547) 0x6e1c0 SHR $0x2,%R11 |
(1547) 0x6e1c4 LEA 0x18(%RSI,%R9,8),%R12 |
(1547) 0x6e1c9 JMP 6e20d |
(1549) 0x6e200 ADD $0x20,%R12 |
(1549) 0x6e204 DEC %R11 |
(1549) 0x6e207 JE 6e14f |
(1549) 0x6e20d MOV -0x18(%R12),%R13 |
(1549) 0x6e212 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e216 JNE 6e240 |
(1549) 0x6e218 MOV -0x10(%R12),%R13 |
(1549) 0x6e21d CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e221 JNE 6e25e |
(1549) 0x6e223 MOV -0x8(%R12),%R13 |
(1549) 0x6e228 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e22c JNE 6e27c |
(1549) 0x6e22e MOV (%R12),%R13 |
(1549) 0x6e232 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e236 JE 6e200 |
(1549) 0x6e238 JMP 6e29d |
(1549) 0x6e240 MOV -0x40(%RBP),%RDX |
(1549) 0x6e244 MOV (%RDX,%R14,8),%RDX |
(1549) 0x6e248 MOV %R13,(%RDX,%RCX,8) |
(1549) 0x6e24c INC %RCX |
(1549) 0x6e24f MOV %RDI,(%R15,%R13,8) |
(1549) 0x6e253 MOV -0x10(%R12),%R13 |
(1549) 0x6e258 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e25c JE 6e223 |
(1549) 0x6e25e MOV -0x40(%RBP),%RDX |
(1549) 0x6e262 MOV (%RDX,%R14,8),%RDX |
(1549) 0x6e266 MOV %R13,(%RDX,%RCX,8) |
(1549) 0x6e26a INC %RCX |
(1549) 0x6e26d MOV %RDI,(%R15,%R13,8) |
(1549) 0x6e271 MOV -0x8(%R12),%R13 |
(1549) 0x6e276 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e27a JE 6e22e |
(1549) 0x6e27c MOV -0x40(%RBP),%RDX |
(1549) 0x6e280 MOV (%RDX,%R14,8),%RDX |
(1549) 0x6e284 MOV %R13,(%RDX,%RCX,8) |
(1549) 0x6e288 INC %RCX |
(1549) 0x6e28b MOV %RDI,(%R15,%R13,8) |
(1549) 0x6e28f MOV (%R12),%R13 |
(1549) 0x6e293 CMP %RDI,(%R15,%R13,8) |
(1549) 0x6e297 JE 6e200 |
(1549) 0x6e29d MOV -0x40(%RBP),%RDX |
(1549) 0x6e2a1 MOV (%RDX,%R14,8),%RDX |
(1549) 0x6e2a5 MOV %R13,(%RDX,%RCX,8) |
(1549) 0x6e2a9 INC %RCX |
(1549) 0x6e2ac MOV %RDI,(%R15,%R13,8) |
(1549) 0x6e2b0 JMP 6e200 |
0x6e2c0 MOV -0xa8(%RBP),%RDX |
0x6e2c7 MOV -0x38(%RBP),%R8 |
0x6e2cb MOV (%RDX,%R8,8),%RSI |
0x6e2cf MOV 0x8(%RDX,%R8,8),%R8 |
0x6e2d4 JMP 6e313 |
(1545) 0x6e300 MOV -0xa8(%RBP),%RDX |
(1545) 0x6e307 MOV -0x38(%RBP),%R8 |
(1545) 0x6e30b MOV 0x8(%RDX,%R8,8),%R8 |
(1545) 0x6e310 INC %RSI |
(1545) 0x6e313 CMP %R8,%RSI |
(1545) 0x6e316 JGE 6dec0 |
(1545) 0x6e31c MOV -0x130(%RBP),%RDX |
(1545) 0x6e323 MOV (%RDX,%RSI,8),%R9 |
(1545) 0x6e327 MOV -0x120(%RBP),%RDX |
(1545) 0x6e32e CMP %R12,(%RDX,%R9,8) |
(1545) 0x6e332 JNE 6e310 |
(1545) 0x6e334 MOV -0x110(%RBP),%RDX |
(1545) 0x6e33b MOV 0x8(%RDX,%R9,8),%RDX |
(1545) 0x6e340 TEST %RDX,%RDX |
(1545) 0x6e343 JLE 6e310 |
(1545) 0x6e345 MOV -0x100(%RBP),%R8 |
(1545) 0x6e34c MOV (%R8,%R9,8),%R8 |
(1545) 0x6e350 ADD %R8,%RDX |
(1545) 0x6e353 MOV -0x108(%RBP),%R9 |
(1545) 0x6e35a MOV (%R9,%R14,8),%R9 |
(1545) 0x6e35e JMP 6e38c |
(1546) 0x6e380 INC %R8 |
(1546) 0x6e383 CMP %RDX,%R8 |
(1546) 0x6e386 JGE 6e300 |
(1546) 0x6e38c MOV (%R9,%R8,8),%R10 |
(1546) 0x6e390 TEST %R10,%R10 |
(1546) 0x6e393 JS 6e3c0 |
(1546) 0x6e395 CMP %RDI,(%R15,%R10,8) |
(1546) 0x6e399 JE 6e380 |
(1546) 0x6e39b MOV -0x40(%RBP),%R11 |
(1546) 0x6e39f MOV (%R11,%R14,8),%R11 |
(1546) 0x6e3a3 MOV %R10,(%R11,%RCX,8) |
(1546) 0x6e3a7 INC %RCX |
(1546) 0x6e3aa MOV %RDI,(%R15,%R10,8) |
(1546) 0x6e3ae JMP 6e380 |
(1546) 0x6e3c0 NOT %R10 |
(1546) 0x6e3c3 CMP %RDI,(%RBX,%R10,8) |
(1546) 0x6e3c7 JE 6e380 |
(1546) 0x6e3c9 MOV -0x60(%RBP),%R11 |
(1546) 0x6e3cd MOV (%R11,%R14,8),%R11 |
(1546) 0x6e3d1 MOV %R10,(%R11,%RAX,8) |
(1546) 0x6e3d5 INC %RAX |
(1546) 0x6e3d8 MOV %RDI,(%RBX,%R10,8) |
(1546) 0x6e3dc JMP 6e380 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 917 - 1125 |
-------------------------------------------------------------------------------- |
917: for (i=0; i < n_coarse; i++) |
[...] |
1072: for (i=thread_start; i < thread_stop; i++) |
1073: { |
1074: i1 = pass_array[i]; |
1075: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1076: { |
1077: j1 = S_diag_j[j]; |
1078: if (assigned[j1] == pass-1) |
1079: { |
1080: j_start = P_diag_start[j1]; |
1081: j_end = j_start+P_diag_i[j1+1]; |
1082: for (k=j_start; k < j_end; k++) |
1083: { |
1084: k1 = P_diag_pass[pass-1][k]; |
1085: if (P_marker[k1] != -i1-1) |
1086: { |
1087: P_diag_pass[pass][cnt_nz++] = k1; |
1088: P_marker[k1] = -i1-1; |
1089: } |
1090: } |
1091: j_start = P_offd_start[j1]; |
1092: j_end = j_start+P_offd_i[j1+1]; |
1093: for (k=j_start; k < j_end; k++) |
1094: { |
1095: k1 = P_offd_pass[pass-1][k]; |
1096: if (P_marker_offd[k1] != -i1-1) |
1097: { |
1098: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1099: P_marker_offd[k1] = -i1-1; |
1100: } |
1101: } |
1102: } |
1103: } |
1104: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1105: { |
1106: j1 = S_offd_j[j]; |
1107: if (assigned_offd[j1] == pass-1) |
1108: { |
1109: j_start = Pext_start[j1]; |
1110: j_end = j_start+Pext_i[j1+1]; |
1111: for (k=j_start; k < j_end; k++) |
1112: { |
1113: k1 = Pext_pass[pass][k]; |
1114: if (k1 < 0) |
1115: { |
1116: if (P_marker[-k1-1] != -i1-1) |
1117: { |
1118: P_diag_pass[pass][cnt_nz++] = -k1-1; |
1119: P_marker[-k1-1] = -i1-1; |
1120: } |
1121: } |
1122: else if (P_marker_offd[k1] != -i1-1) |
1123: { |
1124: P_offd_pass[pass][cnt_nz_offd++] = k1; |
1125: P_marker_offd[k1] = -i1-1; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.11 |
Bottlenecks | P2, P3, P11, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.33 |
CQA cycles if no scalar integer | 3.33 |
CQA cycles if FP arith vectorized | 3.33 |
CQA cycles if fully vectorized | 0.42 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 0.70 |
P0 cycles | 0.60 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.00 |
P4 cycles | 0.60 |
P5 cycles | 0.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.60 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 3.85 |
Stall cycles (UFS) | 0.69 |
Nb insns | 18.00 |
Nb uops | 18.00 |
Nb loads | 10.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.80 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.11 |
Bottlenecks | P2, P3, P11, |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source | par_multi_interp.c:1072-1075,par_multi_interp.c:1078-1078,par_multi_interp.c:1099-1099,par_multi_interp.c:1104-1104 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 3.33 |
CQA cycles if no scalar integer | 3.33 |
CQA cycles if FP arith vectorized | 3.33 |
CQA cycles if fully vectorized | 0.42 |
Front-end cycles | 3.00 |
DIV/SQRT cycles | 0.70 |
P0 cycles | 0.60 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 1.00 |
P4 cycles | 0.60 |
P5 cycles | 0.50 |
P6 cycles | 1.00 |
P7 cycles | 1.00 |
P8 cycles | 1.00 |
P9 cycles | 0.60 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 3.85 |
Stall cycles (UFS) | 0.69 |
Nb insns | 18.00 |
Nb uops | 18.00 |
Nb loads | 10.00 |
Nb stores | 2.00 |
Nb stack references | 6.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 28.80 |
Bytes prefetched | 0.00 |
Bytes loaded | 80.00 |
Bytes stored | 16.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | NA |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | NA |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | libparcsr_ls.so |
nb instructions | 18 |
nb uops | 18 |
loop length | 83 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.70 | 0.60 | 3.33 | 3.33 | 1.00 | 0.60 | 0.50 | 1.00 | 1.00 | 1.00 | 0.60 | 3.33 |
cycles | 0.70 | 0.60 | 3.33 | 3.33 | 1.00 | 0.60 | 0.50 | 1.00 | 1.00 | 1.00 | 0.60 | 3.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.85 |
Stall cycles | 0.69 |
LM full (events) | 2.04 |
Front-end | 3.00 |
Dispatch | 3.33 |
Overall L1 | 3.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x98(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xd8(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 6e400 <hypre_BoomerAMGBuildMultipass.extracted.34+0x1180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 6df1e <hypre_BoomerAMGBuildMultipass.extracted.34+0xc9e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDX,%R8,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 6e313 <hypre_BoomerAMGBuildMultipass.extracted.34+0x1093> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_BoomerAMGBuildMultipass.extracted.34 |
Source file and lines | par_multi_interp.c:917-1125 |
Module | libparcsr_ls.so |
nb instructions | 18 |
nb uops | 18 |
loop length | 83 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 6 |
micro-operation queue | 3.00 cycles |
front end | 3.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 0.70 | 0.60 | 3.33 | 3.33 | 1.00 | 0.60 | 0.50 | 1.00 | 1.00 | 1.00 | 0.60 | 3.33 |
cycles | 0.70 | 0.60 | 3.33 | 3.33 | 1.00 | 0.60 | 0.50 | 1.00 | 1.00 | 1.00 | 0.60 | 3.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 3.85 |
Stall cycles | 0.69 |
LM full (events) | 2.04 |
Front-end | 3.00 |
Dispatch | 3.33 |
Overall L1 | 3.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x98(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
INC %RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0xd8(%RBP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 6e400 <hypre_BoomerAMGBuildMultipass.extracted.34+0x1180> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0x98(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0xb0(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOT %RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 6df1e <hypre_BoomerAMGBuildMultipass.extracted.34+0xc9e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0xa8(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x38(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDX,%R8,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 6e313 <hypre_BoomerAMGBuildMultipass.extracted.34+0x1093> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |