Loop Id: 24 | Module: libIJ_mv.so | Source: IJMatrix_parcsr.c:199-200 | Coverage: 0.01% |
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Loop Id: 24 | Module: libIJ_mv.so | Source: IJMatrix_parcsr.c:199-200 | Coverage: 0.01% |
---|
0x76b0 ADD -0x38(%R12,%RSI,1),%RCX [1] |
0x76b5 MOV %RCX,-0x30(%RAX,%RSI,1) [2] |
0x76ba ADD -0x30(%R12,%RSI,1),%RCX [1] |
0x76bf MOV %RCX,-0x28(%RAX,%RSI,1) [2] |
0x76c4 ADD -0x28(%R12,%RSI,1),%RCX [1] |
0x76c9 MOV %RCX,-0x20(%RAX,%RSI,1) [2] |
0x76ce ADD -0x20(%R12,%RSI,1),%RCX [1] |
0x76d3 MOV %RCX,-0x18(%RAX,%RSI,1) [2] |
0x76d8 ADD -0x18(%R12,%RSI,1),%RCX [1] |
0x76dd MOV %RCX,-0x10(%RAX,%RSI,1) [2] |
0x76e2 ADD -0x10(%R12,%RSI,1),%RCX [1] |
0x76e7 MOV %RCX,-0x8(%RAX,%RSI,1) [2] |
0x76ec ADD -0x8(%R12,%RSI,1),%RCX [1] |
0x76f1 MOV %RCX,(%RAX,%RSI,1) [2] |
0x76f5 ADD (%R12,%RSI,1),%RCX [1] |
0x76f9 MOV %RCX,0x8(%RAX,%RSI,1) [2] |
0x76fe ADD $0x40,%RSI |
0x7702 DEC %RDX |
0x7705 JNE 76b0 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 199 - 200 |
-------------------------------------------------------------------------------- |
199: for (i = 0; i < local_num_rows; i++) |
200: diag_i[i+1] = diag_i[i] + diag_sizes[i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.85 |
Bottlenecks | |
Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
Source | IJMatrix_parcsr.c:199-200 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 1.00 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 1.90 |
P0 cycles | 1.80 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 4.00 |
P4 cycles | 1.80 |
P5 cycles | 1.70 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 1.80 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | 8.13 |
Stall cycles (UFS) | 3.27 |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 8.00 |
Nb stores | 8.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.85 |
Bottlenecks | |
Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
Source | IJMatrix_parcsr.c:199-200 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 8.00 |
CQA cycles if no scalar integer | 8.00 |
CQA cycles if FP arith vectorized | 8.00 |
CQA cycles if fully vectorized | 1.00 |
Front-end cycles | 4.33 |
DIV/SQRT cycles | 1.90 |
P0 cycles | 1.80 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 4.00 |
P4 cycles | 1.80 |
P5 cycles | 1.70 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 1.80 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 8 |
FE+BE cycles (UFS) | 8.13 |
Stall cycles (UFS) | 3.27 |
Nb insns | 19.00 |
Nb uops | 18.00 |
Nb loads | 8.00 |
Nb stores | 8.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 16.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 64.00 |
Bytes stored | 64.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 0.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | NA |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 12.50 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | NA |
Path / |
Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
Source file and lines | IJMatrix_parcsr.c:199-200 |
Module | libIJ_mv.so |
nb instructions | 19 |
nb uops | 18 |
loop length | 87 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.90 | 1.80 | 2.67 | 2.67 | 4.00 | 1.80 | 1.70 | 4.00 | 4.00 | 4.00 | 1.80 | 2.67 |
cycles | 1.90 | 1.80 | 2.67 | 2.67 | 4.00 | 1.80 | 1.70 | 4.00 | 4.00 | 4.00 | 1.80 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
FE+BE cycles | 8.13 |
Stall cycles | 3.27 |
RS full (events) | 7.15 |
Front-end | 4.33 |
Dispatch | 4.00 |
Data deps. | 8.00 |
Overall L1 | 8.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD -0x38(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x30(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x30(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x28(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x28(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x20(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x20(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x18(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x18(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x10(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x10(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x8(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD (%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 76b0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
Source file and lines | IJMatrix_parcsr.c:199-200 |
Module | libIJ_mv.so |
nb instructions | 19 |
nb uops | 18 |
loop length | 87 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.33 cycles |
front end | 4.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.90 | 1.80 | 2.67 | 2.67 | 4.00 | 1.80 | 1.70 | 4.00 | 4.00 | 4.00 | 1.80 | 2.67 |
cycles | 1.90 | 1.80 | 2.67 | 2.67 | 4.00 | 1.80 | 1.70 | 4.00 | 4.00 | 4.00 | 1.80 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 8.00 |
FE+BE cycles | 8.13 |
Stall cycles | 3.27 |
RS full (events) | 7.15 |
Front-end | 4.33 |
Dispatch | 4.00 |
Data deps. | 8.00 |
Overall L1 | 8.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ADD -0x38(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x30(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x30(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x28(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x28(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x20(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x20(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x18(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x18(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x10(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x10(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,-0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD -0x8(%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD (%R12,%RSI,1),%RCX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x40,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
DEC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JNE 76b0 <hypre_IJMatrixSetDiagOffdSizesParCSR+0x80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |