Loop Id: 46 | Module: libparcsr_ls.so | Source: ams.c:3672-3675 | Coverage: 0.29% |
---|
Loop Id: 46 | Module: libparcsr_ls.so | Source: ams.c:3672-3675 | Coverage: 0.29% |
---|
0x12899 VMOVDQU (%RSI,%RCX,1),%YMM7 [2] |
0x1289e KMOVB %K1,%K3 |
0x128a2 VMOVDQU 0x20(%RSI,%RCX,1),%YMM8 [2] |
0x128a8 KMOVB %K1,%K2 |
0x128ac KMOVB %K1,%K4 |
0x128b0 KMOVB %K1,%K7 |
0x128b4 VMOVDQU 0x40(%RSI,%RCX,1),%YMM10 [2] |
0x128ba VMOVDQU 0x60(%RSI,%RCX,1),%YMM12 [2] |
0x128c0 KMOVB %K1,%K6 |
0x128c4 KMOVB %K1,%K5 |
0x128c8 VGATHERQPD (%R8,%YMM7,8),%YMM5{%K3} [6] |
0x128cf VGATHERQPD (%R8,%YMM8,8),%YMM9{%K2} [5] |
0x128d6 VMOVDQU 0x80(%RSI,%RCX,1),%YMM13 [2] |
0x128df VMOVDQU 0xa0(%RSI,%RCX,1),%YMM15 [2] |
0x128e8 KMOVB %K1,%K3 |
0x128ec KMOVB %K1,%K2 |
0x128f0 VFNMADD231PD (%RDI,%RCX,1),%YMM5,%YMM0 [7] |
0x128f6 VGATHERQPD (%R8,%YMM10,8),%YMM11{%K4} [4] |
0x128fd VMOVDQU 0xc0(%RSI,%RCX,1),%YMM6 [2] |
0x12906 VGATHERQPD (%R8,%YMM13,8),%YMM14{%K6} [10] |
0x1290d VGATHERQPD (%R8,%YMM15,8),%YMM7{%K5} [1] |
0x12914 VMOVDQU 0xe0(%RSI,%RCX,1),%YMM5 [2] |
0x1291d VGATHERQPD (%R8,%YMM6,8),%YMM1{%K3} [9] |
0x12924 VFNMADD231PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 [7] |
0x1292b VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM11 [7] |
0x12932 VGATHERQPD (%R8,%YMM12,8),%YMM0{%K7} [3] |
0x12939 VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM11,%YMM0 [7] |
0x12940 VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM0,%YMM14 [7] |
0x1294a VGATHERQPD (%R8,%YMM5,8),%YMM0{%K2} [8] |
0x12951 VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM14,%YMM7 [7] |
0x1295b VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM7,%YMM1 [7] |
0x12965 VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM1,%YMM0 [7] |
0x1296f ADD $0x100,%RCX |
0x12976 CMP %RCX,%R15 |
0x12979 JNE 12899 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3672 - 3675 |
-------------------------------------------------------------------------------- |
3672: for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++) |
3673: { |
3674: ii = A_diag_j[jj]; |
3675: res -= A_diag_data[jj] * Vtemp_data[ii]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 4.63 |
Bottlenecks | |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source | ams.c:3672-3675 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 74.00 |
CQA cycles if no scalar integer | 32.00 - 74.00 |
CQA cycles if FP arith vectorized | 25.14 - 58.14 |
CQA cycles if fully vectorized | 16.00 - 37.00 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 10.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 74 |
FE+BE cycles (UFS) | 32.20 - 192.81 |
Stall cycles (UFS) | 21.77 - 182.38 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.86 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.38 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 8.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 4.63 |
Bottlenecks | |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source | ams.c:3672-3675 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 74.00 |
CQA cycles if no scalar integer | 32.00 - 74.00 |
CQA cycles if FP arith vectorized | 25.14 - 58.14 |
CQA cycles if fully vectorized | 16.00 - 37.00 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 10.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 74 |
FE+BE cycles (UFS) | 32.20 - 192.81 |
Stall cycles (UFS) | 21.77 - 182.38 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.86 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.38 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 8.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Path / |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source file and lines | ams.c:3672-3675 |
Module | libparcsr_ls.so |
nb instructions | 35 |
nb uops | 66 |
loop length | 230 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 13 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-74.00 |
FE+BE cycles | 32.20-192.81 |
Stall cycles | 21.77-182.38 |
RS full (events) | 1.79-2.79 |
LB full (events) | 24.85-184.73 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-74.00 |
Overall L1 | 32.00-74.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RCX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x20(%RSI,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x40(%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VGATHERQPD (%R8,%YMM7,8),%YMM5{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%R8,%YMM8,8),%YMM9{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0xa0(%RSI,%RCX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD231PD (%RDI,%RCX,1),%YMM5,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM10,8),%YMM11{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xc0(%RSI,%RCX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%R8,%YMM13,8),%YMM14{%K6} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%R8,%YMM15,8),%YMM7{%K5} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RCX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%R8,%YMM6,8),%YMM1{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD231PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM12,8),%YMM0{%K7} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM11,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM0,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM5,8),%YMM0{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM14,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM7,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 12899 <hypre_ParCSRRelaxThreads._omp_fn.1+0x209> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source file and lines | ams.c:3672-3675 |
Module | libparcsr_ls.so |
nb instructions | 35 |
nb uops | 66 |
loop length | 230 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 13 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-74.00 |
FE+BE cycles | 32.20-192.81 |
Stall cycles | 21.77-182.38 |
RS full (events) | 1.79-2.79 |
LB full (events) | 24.85-184.73 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-74.00 |
Overall L1 | 32.00-74.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RCX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x20(%RSI,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x40(%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VGATHERQPD (%R8,%YMM7,8),%YMM5{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%R8,%YMM8,8),%YMM9{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0xa0(%RSI,%RCX,1),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K1,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K1,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD231PD (%RDI,%RCX,1),%YMM5,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM10,8),%YMM11{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xc0(%RSI,%RCX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%R8,%YMM13,8),%YMM14{%K6} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%R8,%YMM15,8),%YMM7{%K5} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RCX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%R8,%YMM6,8),%YMM1{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD231PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM12,8),%YMM0{%K7} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM11,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM0,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%R8,%YMM5,8),%YMM0{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM14,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM7,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 12899 <hypre_ParCSRRelaxThreads._omp_fn.1+0x209> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |