Loop Id: 2 | Module: libparcsr_ls.so | Source: ams.c:3532-3534 | Coverage: 0.04% |
---|
Loop Id: 2 | Module: libparcsr_ls.so | Source: ams.c:3532-3534 | Coverage: 0.04% |
---|
0xdff5 MOV (%R14,%RDX,8),%RSI [9] |
0xdff9 VCOMISD (%R12,%RSI,8),%XMM9 [4] |
0xdfff JBE e012 |
0xe001 VMOVSD (%R10,%RDX,8),%XMM1 [15] |
0xe007 VXORPD %XMM8,%XMM1,%XMM14 |
0xe00c VMOVSD %XMM14,(%R10,%RDX,8) [15] |
0xe012 INC %RDX |
0xe015 MOV (%R14,%RDX,8),%RCX [5] |
0xe019 VCOMISD (%R12,%RCX,8),%XMM9 [3] |
0xe01f JBE e032 |
0xe021 VMOVSD (%R10,%RDX,8),%XMM2 [12] |
0xe027 VXORPD %XMM8,%XMM2,%XMM6 |
0xe02c VMOVSD %XMM6,(%R10,%RDX,8) [12] |
0xe032 LEA 0x1(%RDX),%RSI |
0xe036 MOV (%R14,%RSI,8),%RDI [8] |
0xe03a VCOMISD (%R12,%RDI,8),%XMM9 [10] |
0xe040 JBE e053 |
0xe042 VMOVSD (%R10,%RSI,8),%XMM7 [1] |
0xe048 VXORPD %XMM8,%XMM7,%XMM10 |
0xe04d VMOVSD %XMM10,(%R10,%RSI,8) [1] |
0xe053 LEA 0x2(%RDX),%RCX |
0xe057 MOV (%R14,%RCX,8),%RSI [8] |
0xe05b VCOMISD (%R12,%RSI,8),%XMM9 [11] |
0xe061 JBE e074 |
0xe063 VMOVSD (%R10,%RCX,8),%XMM15 [1] |
0xe069 VXORPD %XMM8,%XMM15,%XMM5 |
0xe06e VMOVSD %XMM5,(%R10,%RCX,8) [1] |
0xe074 LEA 0x3(%RDX),%RCX |
0xe078 MOV (%R14,%RCX,8),%RDI [8] |
0xe07c VCOMISD (%R12,%RDI,8),%XMM9 [6] |
0xe082 JBE e095 |
0xe084 VMOVSD (%R10,%RCX,8),%XMM0 [1] |
0xe08a VXORPD %XMM8,%XMM0,%XMM11 |
0xe08f VMOVSD %XMM11,(%R10,%RCX,8) [1] |
0xe095 LEA 0x4(%RDX),%RSI |
0xe099 MOV (%R14,%RSI,8),%RCX [8] |
0xe09d VCOMISD (%R12,%RCX,8),%XMM9 [13] |
0xe0a3 JBE e0b6 |
0xe0a5 VMOVSD (%R10,%RSI,8),%XMM12 [1] |
0xe0ab VXORPD %XMM8,%XMM12,%XMM1 |
0xe0b0 VMOVSD %XMM1,(%R10,%RSI,8) [1] |
0xe0b6 LEA 0x5(%RDX),%RSI |
0xe0ba MOV (%R14,%RSI,8),%RDI [8] |
0xe0be VCOMISD (%R12,%RDI,8),%XMM9 [7] |
0xe0c4 JBE e0d7 |
0xe0c6 VMOVSD (%R10,%RSI,8),%XMM14 [1] |
0xe0cc VXORPD %XMM8,%XMM14,%XMM2 |
0xe0d1 VMOVSD %XMM2,(%R10,%RSI,8) [1] |
0xe0d7 LEA 0x6(%RDX),%RCX |
0xe0db MOV (%R14,%RCX,8),%RSI [8] |
0xe0df VCOMISD (%R12,%RSI,8),%XMM9 [2] |
0xe0e5 JBE e0f8 |
0xe0e7 VMOVSD (%R10,%RCX,8),%XMM6 [1] |
0xe0ed VXORPD %XMM8,%XMM6,%XMM7 |
0xe0f2 VMOVSD %XMM7,(%R10,%RCX,8) [1] |
0xe0f8 ADD $0x7,%RDX |
0xe0fc CMP %RDX,-0x38(%RBP) [14] |
0xe100 JNE dff5 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3532 - 3534 |
-------------------------------------------------------------------------------- |
3532: for (i = ns; i < ne; i++) |
3533: if (A_diag_data[A_diag_I[i]] < 0) |
3534: l1_norm[i] = -l1_norm[i]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.27 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.27 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads._omp_fn.0 |
Source | ams.c:3532-3534 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.83 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 10.83 |
CQA cycles if fully vectorized | 1.35 |
Front-end cycles | 10.83 |
DIV/SQRT cycles | 8.50 |
P0 cycles | 4.00 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 4.00 |
P4 cycles | 4.00 |
P5 cycles | 8.50 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.00 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 11.76 |
Stall cycles (UFS) | 0.69 |
Nb insns | 58.00 |
Nb uops | 65.00 |
Nb loads | 25.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.37 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 25.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 15.63 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.27 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.27 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParCSRComputeL1NormsThreads._omp_fn.0 |
Source | ams.c:3532-3534 |
Source loop unroll info | multi-versionned |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.83 |
CQA cycles if no scalar integer | 8.50 |
CQA cycles if FP arith vectorized | 10.83 |
CQA cycles if fully vectorized | 1.35 |
Front-end cycles | 10.83 |
DIV/SQRT cycles | 8.50 |
P0 cycles | 4.00 |
P1 cycles | 8.33 |
P2 cycles | 8.33 |
P3 cycles | 4.00 |
P4 cycles | 4.00 |
P5 cycles | 8.50 |
P6 cycles | 4.00 |
P7 cycles | 4.00 |
P8 cycles | 4.00 |
P9 cycles | 0.00 |
P10 cycles | 8.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 11.76 |
Stall cycles (UFS) | 0.69 |
Nb insns | 58.00 |
Nb uops | 65.00 |
Nb loads | 25.00 |
Nb stores | 8.00 |
Nb stack references | 1.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.37 |
Bytes prefetched | 0.00 |
Bytes loaded | 200.00 |
Bytes stored | 64.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 25.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 50.00 |
Vector-efficiency ratio all | 15.63 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 18.75 |
Path / |
Function | hypre_ParCSRComputeL1NormsThreads._omp_fn.0 |
Source file and lines | ams.c:3532-3534 |
Module | libparcsr_ls.so |
nb instructions | 58 |
nb uops | 65 |
loop length | 273 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 13 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 10.83 cycles |
front end | 10.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.50 | 4.00 | 8.33 | 8.33 | 4.00 | 4.00 | 8.50 | 4.00 | 4.00 | 4.00 | 0.00 | 8.33 |
cycles | 8.50 | 4.00 | 8.33 | 8.33 | 4.00 | 4.00 | 8.50 | 4.00 | 4.00 | 4.00 | 0.00 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.76 |
Stall cycles | 0.69 |
LM full (events) | 2.13 |
Front-end | 10.83 |
Dispatch | 8.50 |
Overall L1 | 10.83 |
all | 25% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 15% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%R14,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e012 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x722> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RDX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM1,%XMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM14,(%R10,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R14,%RDX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RCX,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e032 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x742> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RDX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM6,(%R10,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e053 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x763> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM7,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM10,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x2(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e074 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x784> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM15,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM5,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e095 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM0,%XMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM11,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RCX,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0b6 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7c6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM12,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM1,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0d7 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM14,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM2,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x6(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0f8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x808> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM6,%XMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM7,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x7,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE dff5 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x705> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParCSRComputeL1NormsThreads._omp_fn.0 |
Source file and lines | ams.c:3532-3534 |
Module | libparcsr_ls.so |
nb instructions | 58 |
nb uops | 65 |
loop length | 273 |
used x86 registers | 8 |
used mmx registers | 0 |
used xmm registers | 13 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 1 |
micro-operation queue | 10.83 cycles |
front end | 10.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 8.50 | 4.00 | 8.33 | 8.33 | 4.00 | 4.00 | 8.50 | 4.00 | 4.00 | 4.00 | 0.00 | 8.33 |
cycles | 8.50 | 4.00 | 8.33 | 8.33 | 4.00 | 4.00 | 8.50 | 4.00 | 4.00 | 4.00 | 0.00 | 8.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 11.76 |
Stall cycles | 0.69 |
LM full (events) | 2.13 |
Front-end | 10.83 |
Dispatch | 8.50 |
Overall L1 | 10.83 |
all | 25% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 15% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 18% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%R14,%RDX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e012 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x722> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RDX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM1,%XMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM14,(%R10,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV (%R14,%RDX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RCX,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e032 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x742> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RDX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM6,(%R10,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e053 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x763> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM7,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM10,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x2(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e074 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x784> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM15,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM5,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x3(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e095 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7a5> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM0,%XMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM11,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x4(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RCX,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0b6 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7c6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM12,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM1,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x5(%RDX),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RSI,8),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RDI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0d7 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x7e7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RSI,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM14,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM2,(%R10,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x6(%RDX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%R14,%RCX,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VCOMISD (%R12,%RSI,8),%XMM9 | 2 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
JBE e0f8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x808> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMOVSD (%R10,%RCX,8),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM8,%XMM6,%XMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVSD %XMM7,(%R10,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD $0x7,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE dff5 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x705> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |