Loop Id: 845 | Module: libparcsr_ls.so | Source: par_multi_interp.c:275-276 | Coverage: 0.04% |
---|
Loop Id: 845 | Module: libparcsr_ls.so | Source: par_multi_interp.c:275-276 | Coverage: 0.04% |
---|
0x7ed49 VMOVDQU (%R10),%YMM12 [2] |
0x7ed4e VMOVDQU 0x20(%R10),%YMM7 [2] |
0x7ed54 ADD $0x100,%R10 |
0x7ed5b VMOVDQU -0xc0(%R10),%YMM10 [1] |
0x7ed64 VPCMPEQQ %YMM4,%YMM12,%YMM13 |
0x7ed69 VPCMPEQQ %YMM4,%YMM7,%YMM2 |
0x7ed6e VPCMPEQQ %YMM3,%YMM12,%YMM15 |
0x7ed73 VPCMPEQQ %YMM3,%YMM7,%YMM5 |
0x7ed78 VPSUBQ %YMM13,%YMM1,%YMM14 |
0x7ed7d VPCMPEQQ %YMM4,%YMM10,%YMM1 |
0x7ed82 VMOVDQU -0xa0(%R10),%YMM13 [1] |
0x7ed8b VPSUBQ %YMM2,%YMM14,%YMM8 |
0x7ed8f VPSUBQ %YMM15,%YMM0,%YMM6 |
0x7ed94 VPCMPEQQ %YMM3,%YMM10,%YMM0 |
0x7ed99 VPCMPEQQ %YMM4,%YMM13,%YMM14 |
0x7ed9e VPSUBQ %YMM5,%YMM6,%YMM9 |
0x7eda2 VPSUBQ %YMM1,%YMM8,%YMM11 |
0x7eda6 VMOVDQU -0x80(%R10),%YMM8 [1] |
0x7edac VMOVDQU -0x60(%R10),%YMM1 [1] |
0x7edb2 VPCMPEQQ %YMM3,%YMM13,%YMM6 |
0x7edb7 VPSUBQ %YMM0,%YMM9,%YMM12 |
0x7edbb VPCMPEQQ %YMM4,%YMM8,%YMM2 |
0x7edc0 VPCMPEQQ %YMM3,%YMM8,%YMM5 |
0x7edc5 VPSUBQ %YMM14,%YMM11,%YMM15 |
0x7edca VMOVDQU -0x40(%R10),%YMM14 [1] |
0x7edd0 VPCMPEQQ %YMM4,%YMM1,%YMM11 |
0x7edd5 VPCMPEQQ %YMM3,%YMM1,%YMM0 |
0x7edda VPSUBQ %YMM6,%YMM12,%YMM7 |
0x7edde VPSUBQ %YMM2,%YMM15,%YMM9 |
0x7ede2 VMOVDQU -0x20(%R10),%YMM2 [1] |
0x7ede8 VPSUBQ %YMM5,%YMM7,%YMM10 |
0x7edec VPCMPEQQ %YMM4,%YMM14,%YMM15 |
0x7edf1 VPCMPEQQ %YMM3,%YMM14,%YMM7 |
0x7edf6 VPSUBQ %YMM11,%YMM9,%YMM12 |
0x7edfb VPSUBQ %YMM0,%YMM10,%YMM13 |
0x7edff VPCMPEQQ %YMM4,%YMM2,%YMM9 |
0x7ee04 VPCMPEQQ %YMM3,%YMM2,%YMM5 |
0x7ee09 VPSUBQ %YMM15,%YMM12,%YMM6 |
0x7ee0e VPSUBQ %YMM7,%YMM13,%YMM8 |
0x7ee12 VPSUBQ %YMM9,%YMM6,%YMM1 |
0x7ee17 VPSUBQ %YMM5,%YMM8,%YMM0 |
0x7ee1b CMP %R13,%R10 |
0x7ee1e JNE 7ed49 |
/home/eoseret/qaas_runs_CPU_9468/171-716-5699/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 275 - 276 |
-------------------------------------------------------------------------------- |
275: if (CF_marker[i] == 1) n_coarse++; |
276: else if (CF_marker[i] == -3) n_SF++; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.52 |
Bottlenecks | P0, P1, P5, |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
Source | par_multi_interp.c:275-276 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.67 |
CQA cycles if no scalar integer | 10.67 |
CQA cycles if FP arith vectorized | 10.67 |
CQA cycles if fully vectorized | 5.33 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 10.67 |
P0 cycles | 10.67 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 0.00 |
P4 cycles | 10.67 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 8 |
FE+BE cycles (UFS) | 10.93 |
Stall cycles (UFS) | 3.47 |
Nb insns | 43.00 |
Nb uops | 42.00 |
Nb loads | 8.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.52 |
Bottlenecks | P0, P1, P5, |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
Source | par_multi_interp.c:275-276 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 10.67 |
CQA cycles if no scalar integer | 10.67 |
CQA cycles if FP arith vectorized | 10.67 |
CQA cycles if fully vectorized | 5.33 |
Front-end cycles | 7.00 |
DIV/SQRT cycles | 10.67 |
P0 cycles | 10.67 |
P1 cycles | 2.67 |
P2 cycles | 2.67 |
P3 cycles | 0.00 |
P4 cycles | 10.67 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 2.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 1 - 8 |
FE+BE cycles (UFS) | 10.93 |
Stall cycles (UFS) | 3.47 |
Nb insns | 43.00 |
Nb uops | 42.00 |
Nb loads | 8.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 256.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 0.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Path / |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
Source file and lines | par_multi_interp.c:275-276 |
Module | libparcsr_ls.so |
nb instructions | 43 |
nb uops | 42 |
loop length | 219 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.67 | 10.67 | 2.67 | 2.67 | 0.00 | 10.67 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.67 |
cycles | 10.67 | 10.67 | 2.67 | 2.67 | 0.00 | 10.67 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-8.00 |
FE+BE cycles | 10.93 |
Stall cycles | 3.47 |
RS full (events) | 9.30 |
Front-end | 7.00 |
Dispatch | 10.67 |
Data deps. | 1.00-8.00 |
Overall L1 | 10.67 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%R10),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x20(%R10),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
ADD $0x100,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU -0xc0(%R10),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM12,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM4,%YMM7,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM7,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM13,%YMM1,%YMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM10,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVDQU -0xa0(%R10),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM2,%YMM14,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM15,%YMM0,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM3,%YMM10,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM4,%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM5,%YMM6,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM1,%YMM8,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x80(%R10),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x60(%R10),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM3,%YMM13,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM0,%YMM9,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM8,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM8,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM14,%YMM11,%YMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x40(%R10),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM1,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM6,%YMM12,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM2,%YMM15,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x20(%R10),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM5,%YMM7,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM14,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM11,%YMM9,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM0,%YMM10,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM2,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM2,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM15,%YMM12,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM7,%YMM13,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM9,%YMM6,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM5,%YMM8,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
CMP %R13,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 7ed49 <hypre_BoomerAMGBuildMultipass._omp_fn.0+0x1a9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
Source file and lines | par_multi_interp.c:275-276 |
Module | libparcsr_ls.so |
nb instructions | 43 |
nb uops | 42 |
loop length | 219 |
used x86 registers | 2 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 16 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 7.00 cycles |
front end | 7.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 10.67 | 10.67 | 2.67 | 2.67 | 0.00 | 10.67 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.67 |
cycles | 10.67 | 10.67 | 2.67 | 2.67 | 0.00 | 10.67 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 2.67 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 1.00-8.00 |
FE+BE cycles | 10.93 |
Stall cycles | 3.47 |
RS full (events) | 9.30 |
Front-end | 7.00 |
Dispatch | 10.67 |
Data deps. | 1.00-8.00 |
Overall L1 | 10.67 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%R10),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x20(%R10),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
ADD $0x100,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDQU -0xc0(%R10),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM12,%YMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM4,%YMM7,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM12,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM7,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM13,%YMM1,%YMM14 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM10,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VMOVDQU -0xa0(%R10),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM2,%YMM14,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM15,%YMM0,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM3,%YMM10,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM4,%YMM13,%YMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM5,%YMM6,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM1,%YMM8,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x80(%R10),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU -0x60(%R10),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM3,%YMM13,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM0,%YMM9,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM8,%YMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM8,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM14,%YMM11,%YMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x40(%R10),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM1,%YMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM6,%YMM12,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM2,%YMM15,%YMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VMOVDQU -0x20(%R10),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VPSUBQ %YMM5,%YMM7,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM14,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM11,%YMM9,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM0,%YMM10,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ %YMM4,%YMM2,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPCMPEQQ %YMM3,%YMM2,%YMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
VPSUBQ %YMM15,%YMM12,%YMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM7,%YMM13,%YMM8 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM9,%YMM6,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPSUBQ %YMM5,%YMM8,%YMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
CMP %R13,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 7ed49 <hypre_BoomerAMGBuildMultipass._omp_fn.0+0x1a9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |