Loop Id: 3603 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.06% |
---|
Loop Id: 3603 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.06% |
---|
0x4e7600 MOV %RCX,-0x30(%RBP) |
0x4e7604 MOV %RAX,%RBX |
0x4e7607 CMP -0x38(%RBP),%R8 |
0x4e760b JGE 4e7a00 |
0x4e7611 MOV %R8,%RSI |
0x4e7614 CMPQ $0,-0x98(%RBP) |
0x4e761c JE 4e7636 |
0x4e761e MOV %RBX,(%RDI,%RSI,8) |
0x4e7622 MOVQ $0,(%R12,%RBX,8) |
0x4e762a MOV -0x50(%RBP),%RAX |
0x4e762e MOV %RSI,(%RAX,%RBX,8) |
0x4e7632 LEA 0x1(%RBX),%RAX |
0x4e7636 CMPQ $0,-0x90(%RBP) |
0x4e763e JE 4e7840 |
0x4e7644 MOV -0x58(%RBP),%RCX |
0x4e7648 MOV (%RCX,%RSI,8),%R10 |
0x4e764c LEA 0x1(%RSI),%R8 |
0x4e7650 CMP 0x8(%RCX,%RSI,8),%R10 |
0x4e7655 JGE 4e7844 |
0x4e765b MOV %R8,-0x48(%RBP) |
0x4e765f MOV -0x30(%RBP),%RCX |
0x4e7663 MOV %RSI,-0xb0(%RBP) |
0x4e766a JMP 4e769c |
(3607) 0x4e7680 MOV %R14,%R10 |
(3607) 0x4e7683 INC %R10 |
(3607) 0x4e7686 MOV -0x58(%RBP),%RDX |
(3607) 0x4e768a MOV -0xb0(%RBP),%RSI |
(3607) 0x4e7691 CMP 0x8(%RDX,%RSI,8),%R10 |
(3607) 0x4e7696 JGE 4e7880 |
(3607) 0x4e769c MOV -0xa0(%RBP),%RDX |
(3607) 0x4e76a3 MOV (%RDX,%R10,8),%R9 |
(3607) 0x4e76a7 MOV -0xa8(%RBP),%RDX |
(3607) 0x4e76ae MOV %R10,%R14 |
(3607) 0x4e76b1 VMOVSD (%RDX,%R10,8),%XMM0 |
(3607) 0x4e76b7 MOV -0x78(%RBP),%RDX |
(3607) 0x4e76bb MOV (%RDX,%R9,8),%R10 |
(3607) 0x4e76bf MOV 0x8(%RDX,%R9,8),%R11 |
(3607) 0x4e76c4 JMP 4e7715 |
(3609) 0x4e7700 VADDSD (%R13,%R8,8),%XMM1,%XMM1 |
(3609) 0x4e7707 VMOVSD %XMM1,(%R13,%R8,8) |
(3609) 0x4e770e MOV -0x40(%RBP),%R15 |
(3609) 0x4e7712 INC %R10 |
(3609) 0x4e7715 CMP %R11,%R10 |
(3609) 0x4e7718 JGE 4e7780 |
(3609) 0x4e771a MOV -0x100(%RBP),%RDX |
(3609) 0x4e7721 MOV (%RDX,%R10,8),%RSI |
(3609) 0x4e7725 LEA (%RSI,%R15,1),%RDX |
(3609) 0x4e7729 MOV (%RDI,%RDX,8),%R8 |
(3609) 0x4e772d MOV -0xf8(%RBP),%R15 |
(3609) 0x4e7734 VMULSD (%R15,%R10,8),%XMM0,%XMM1 |
(3609) 0x4e773a CMP -0x30(%RBP),%R8 |
(3609) 0x4e773e JGE 4e7700 |
(3609) 0x4e7740 MOV %RCX,(%RDI,%RDX,8) |
(3609) 0x4e7744 VMOVSD %XMM1,(%R13,%RCX,8) |
(3609) 0x4e774b MOV -0x88(%RBP),%RDX |
(3609) 0x4e7752 MOV %RSI,(%RDX,%RCX,8) |
(3609) 0x4e7756 INC %RCX |
(3609) 0x4e7759 MOV -0x78(%RBP),%RDX |
(3609) 0x4e775d MOV 0x8(%RDX,%R9,8),%R11 |
(3609) 0x4e7762 JMP 4e770e |
(3607) 0x4e7780 MOV -0x70(%RBP),%RDX |
(3607) 0x4e7784 MOV (%RDX,%R9,8),%R10 |
(3607) 0x4e7788 MOV 0x8(%RDX,%R9,8),%R11 |
(3607) 0x4e778d CMP %R11,%R10 |
(3607) 0x4e7790 JL 4e77ea |
(3607) 0x4e7792 JMP 4e7680 |
(3608) 0x4e77c0 MOV %RAX,(%RDI,%RSI,8) |
(3608) 0x4e77c4 VMOVSD %XMM1,(%R12,%RAX,8) |
(3608) 0x4e77ca MOV -0x50(%RBP),%RDX |
(3608) 0x4e77ce MOV %RSI,(%RDX,%RAX,8) |
(3608) 0x4e77d2 INC %RAX |
(3608) 0x4e77d5 MOV -0x70(%RBP),%RDX |
(3608) 0x4e77d9 MOV 0x8(%RDX,%R9,8),%R11 |
(3608) 0x4e77de INC %R10 |
(3608) 0x4e77e1 CMP %R11,%R10 |
(3608) 0x4e77e4 JGE 4e7680 |
(3608) 0x4e77ea MOV -0xf0(%RBP),%RDX |
(3608) 0x4e77f1 MOV (%RDX,%R10,8),%RSI |
(3608) 0x4e77f5 MOV (%RDI,%RSI,8),%RDX |
(3608) 0x4e77f9 MOV -0xe8(%RBP),%R8 |
(3608) 0x4e7800 VMULSD (%R8,%R10,8),%XMM0,%XMM1 |
(3608) 0x4e7806 CMP %RBX,%RDX |
(3608) 0x4e7809 JL 4e77c0 |
(3608) 0x4e780b VADDSD (%R12,%RDX,8),%XMM1,%XMM1 |
(3608) 0x4e7811 VMOVSD %XMM1,(%R12,%RDX,8) |
(3608) 0x4e7817 INC %R10 |
(3608) 0x4e781a CMP %R11,%R10 |
(3608) 0x4e781d JL 4e77ea |
(3607) 0x4e781f JMP 4e7680 |
0x4e7840 LEA 0x1(%RSI),%R8 |
0x4e7844 MOV -0x30(%RBP),%RCX |
0x4e7848 MOV -0x60(%RBP),%RDX |
0x4e784c MOV (%RDX,%RSI,8),%RSI |
0x4e7850 CMP (%RDX,%R8,8),%RSI |
0x4e7854 JGE 4e7600 |
0x4e785a JMP 4e7896 |
0x4e7880 MOV -0x48(%RBP),%R8 |
0x4e7884 MOV -0x60(%RBP),%RDX |
0x4e7888 MOV (%RDX,%RSI,8),%RSI |
0x4e788c CMP (%RDX,%R8,8),%RSI |
0x4e7890 JGE 4e7600 |
0x4e7896 MOV %R8,-0x48(%RBP) |
0x4e789a JMP 4e78d5 |
(3604) 0x4e78c0 INC %RSI |
(3604) 0x4e78c3 MOV -0x60(%RBP),%RDX |
(3604) 0x4e78c7 MOV -0x48(%RBP),%R8 |
(3604) 0x4e78cb CMP (%RDX,%R8,8),%RSI |
(3604) 0x4e78cf JGE 4e7600 |
(3604) 0x4e78d5 MOV -0xc8(%RBP),%RDX |
(3604) 0x4e78dc MOV (%RDX,%RSI,8),%R8 |
(3604) 0x4e78e0 MOV -0xc0(%RBP),%RDX |
(3604) 0x4e78e7 VMOVSD (%RDX,%RSI,8),%XMM0 |
(3604) 0x4e78ec MOV -0x80(%RBP),%RDX |
(3604) 0x4e78f0 MOV (%RDX,%R8,8),%R9 |
(3604) 0x4e78f4 MOV 0x8(%RDX,%R8,8),%R10 |
(3604) 0x4e78f9 CMP %R10,%R9 |
(3604) 0x4e78fc JL 4e7926 |
(3604) 0x4e78fe JMP 4e795b |
(3606) 0x4e7900 MOV %RAX,(%RDI,%RDX,8) |
(3606) 0x4e7904 VMOVSD %XMM1,(%R12,%RAX,8) |
(3606) 0x4e790a MOV -0x50(%RBP),%R10 |
(3606) 0x4e790e MOV %RDX,(%R10,%RAX,8) |
(3606) 0x4e7912 INC %RAX |
(3606) 0x4e7915 MOV -0x80(%RBP),%RDX |
(3606) 0x4e7919 MOV 0x8(%RDX,%R8,8),%R10 |
(3606) 0x4e791e INC %R9 |
(3606) 0x4e7921 CMP %R10,%R9 |
(3606) 0x4e7924 JGE 4e795b |
(3606) 0x4e7926 MOV -0x110(%RBP),%RDX |
(3606) 0x4e792d MOV (%RDX,%R9,8),%RDX |
(3606) 0x4e7931 MOV (%RDI,%RDX,8),%R11 |
(3606) 0x4e7935 MOV -0x108(%RBP),%R14 |
(3606) 0x4e793c VMULSD (%R14,%R9,8),%XMM0,%XMM1 |
(3606) 0x4e7942 CMP %RBX,%R11 |
(3606) 0x4e7945 JL 4e7900 |
(3606) 0x4e7947 VADDSD (%R12,%R11,8),%XMM1,%XMM1 |
(3606) 0x4e794d VMOVSD %XMM1,(%R12,%R11,8) |
(3606) 0x4e7953 INC %R9 |
(3606) 0x4e7956 CMP %R10,%R9 |
(3606) 0x4e7959 JL 4e7926 |
(3604) 0x4e795b CMPQ $0,-0xb8(%RBP) |
(3604) 0x4e7963 JE 4e78c0 |
(3604) 0x4e7969 MOV -0x68(%RBP),%RDX |
(3604) 0x4e796d MOV (%RDX,%R8,8),%R9 |
(3604) 0x4e7971 MOV 0x8(%RDX,%R8,8),%R10 |
(3604) 0x4e7976 JMP 4e7995 |
(3605) 0x4e7980 VADDSD (%R13,%R15,8),%XMM1,%XMM1 |
(3605) 0x4e7987 VMOVSD %XMM1,(%R13,%R15,8) |
(3605) 0x4e798e MOV -0x40(%RBP),%R15 |
(3605) 0x4e7992 INC %R9 |
(3605) 0x4e7995 CMP %R10,%R9 |
(3605) 0x4e7998 JGE 4e78c0 |
(3605) 0x4e799e MOV -0xd8(%RBP),%RDX |
(3605) 0x4e79a5 MOV (%RDX,%R9,8),%RDX |
(3605) 0x4e79a9 MOV -0xe0(%RBP),%R11 |
(3605) 0x4e79b0 MOV (%R11,%RDX,8),%RDX |
(3605) 0x4e79b4 LEA (%RDX,%R15,1),%R11 |
(3605) 0x4e79b8 MOV (%RDI,%R11,8),%R15 |
(3605) 0x4e79bc MOV -0xd0(%RBP),%R14 |
(3605) 0x4e79c3 VMULSD (%R14,%R9,8),%XMM0,%XMM1 |
(3605) 0x4e79c9 CMP -0x30(%RBP),%R15 |
(3605) 0x4e79cd JGE 4e7980 |
(3605) 0x4e79cf MOV %RCX,(%RDI,%R11,8) |
(3605) 0x4e79d3 VMOVSD %XMM1,(%R13,%RCX,8) |
(3605) 0x4e79da MOV -0x88(%RBP),%R10 |
(3605) 0x4e79e1 MOV %RDX,(%R10,%RCX,8) |
(3605) 0x4e79e5 INC %RCX |
(3605) 0x4e79e8 MOV -0x68(%RBP),%RDX |
(3605) 0x4e79ec MOV 0x8(%RDX,%R8,8),%R10 |
(3605) 0x4e79f1 JMP 4e798e |
/home/eoseret/qaas_runs_CPU_9468/171-112-7443/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.08 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.25 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 0.55 |
Front-end cycles | 6.67 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 3.50 |
P4 cycles | 2.00 |
P5 cycles | 3.00 |
P6 cycles | 3.50 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 2.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.87 |
Stall cycles (UFS) | 0.00 |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | 16.00 |
Nb stores | 7.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.02 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.08 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.25 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.67 |
CQA cycles if no scalar integer | 6.67 |
CQA cycles if FP arith vectorized | 6.67 |
CQA cycles if fully vectorized | 0.55 |
Front-end cycles | 6.67 |
DIV/SQRT cycles | 3.00 |
P0 cycles | 2.00 |
P1 cycles | 5.33 |
P2 cycles | 5.33 |
P3 cycles | 3.50 |
P4 cycles | 2.00 |
P5 cycles | 3.00 |
P6 cycles | 3.50 |
P7 cycles | 3.50 |
P8 cycles | 3.50 |
P9 cycles | 2.00 |
P10 cycles | 5.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.87 |
Stall cycles (UFS) | 0.00 |
Nb insns | 37.00 |
Nb uops | 37.00 |
Nb loads | 16.00 |
Nb stores | 7.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 27.60 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 56.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.02 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.61 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 37 |
nb uops | 37 |
loop length | 164 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 5.33 | 5.33 | 3.50 | 2.00 | 3.00 | 3.50 | 3.50 | 3.50 | 2.00 | 5.33 |
cycles | 3.00 | 2.00 | 5.33 | 5.33 | 3.50 | 2.00 | 3.00 | 3.50 | 3.50 | 3.50 | 2.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.87 |
Stall cycles | 0.00 |
Front-end | 6.67 |
Dispatch | 5.33 |
Overall L1 | 6.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x38(%RBP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7a00 <hypre_ParMatmul.extracted.12+0x6c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0x98(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4e7636 <hypre_ParMatmul.extracted.12+0x2f6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%RDI,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,(%RAX,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x90(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4e7840 <hypre_ParMatmul.extracted.12+0x500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RSI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RSI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RSI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7844 <hypre_ParMatmul.extracted.12+0x504> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4e769c <hypre_ParMatmul.extracted.12+0x35c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RSI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RDX,%R8,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7600 <hypre_ParMatmul.extracted.12+0x2c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4e7896 <hypre_ParMatmul.extracted.12+0x556> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RDX,%R8,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7600 <hypre_ParMatmul.extracted.12+0x2c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4e78d5 <hypre_ParMatmul.extracted.12+0x595> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 37 |
nb uops | 37 |
loop length | 164 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.67 cycles |
front end | 6.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 3.00 | 2.00 | 5.33 | 5.33 | 3.50 | 2.00 | 3.00 | 3.50 | 3.50 | 3.50 | 2.00 | 5.33 |
cycles | 3.00 | 2.00 | 5.33 | 5.33 | 3.50 | 2.00 | 3.00 | 3.50 | 3.50 | 3.50 | 2.00 | 5.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.87 |
Stall cycles | 0.00 |
Front-end | 6.67 |
Dispatch | 5.33 |
Overall L1 | 6.67 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x38(%RBP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7a00 <hypre_ParMatmul.extracted.12+0x6c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0x98(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4e7636 <hypre_ParMatmul.extracted.12+0x2f6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%RDI,%RSI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x50(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,(%RAX,%RBX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0x90(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4e7840 <hypre_ParMatmul.extracted.12+0x500> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x58(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RSI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RSI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RSI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7844 <hypre_ParMatmul.extracted.12+0x504> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,-0xb0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4e769c <hypre_ParMatmul.extracted.12+0x35c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RSI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV -0x30(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RDX,%R8,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7600 <hypre_ParMatmul.extracted.12+0x2c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4e7896 <hypre_ParMatmul.extracted.12+0x556> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x48(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x60(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%RSI,8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RDX,%R8,8),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4e7600 <hypre_ParMatmul.extracted.12+0x2c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4e78d5 <hypre_ParMatmul.extracted.12+0x595> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |