Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.5% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.9 | Module: exec | Source: par_multi_interp.c:1575-1663 [...] | Coverage: 0.5% |
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/home/eoseret/qaas_runs_CPU_9468/171-112-7443/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663 |
-------------------------------------------------------------------------------- |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1584: tmp_marker = NULL; |
1585: if (n_fine) |
1586: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1587: tmp_marker_offd = NULL; |
1588: if (num_cols_offd) |
1589: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1590: for (i=0; i < n_fine; i++) |
1591: { tmp_marker[i] = -1; } |
1592: for (i=0; i < num_cols_offd; i++) |
1593: { tmp_marker_offd[i] = -1; } |
1594: |
1595: /* Compute this thread's range of pass_length */ |
1596: my_thread_num = hypre_GetThreadNum(); |
1597: num_threads = hypre_NumActiveThreads(); |
1598: thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num; |
1599: if (my_thread_num == num_threads-1) |
1600: { thread_stop = pass_pointer[1] + pass_length; } |
1601: else |
1602: { thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); } |
1603: |
1604: /* determine P for points of pass 1, i.e. neighbors of coarse points */ |
1605: for (i=thread_start; i < thread_stop; i++) |
1606: { |
1607: i1 = pass_array[i]; |
1608: sum_C = 0; |
1609: sum_N = 0; |
1610: j_start = P_diag_start[i1]; |
1611: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1612: for (j=j_start; j < j_end; j++) |
1613: { |
1614: k1 = P_diag_pass[1][j]; |
1615: tmp_marker[C_array[k1]] = i1; |
1616: } |
1617: cnt = P_diag_i[i1]; |
1618: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1619: { |
1620: j1 = A_diag_j[j]; |
1621: if (CF_marker[j1] != -3 && |
1622: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1623: sum_N += A_diag_data[j]; |
1624: if (j1 != -1 && tmp_marker[j1] == i1) |
1625: { |
1626: P_diag_data[cnt] = A_diag_data[j]; |
1627: P_diag_j[cnt++] = fine_to_coarse[j1]; |
1628: sum_C += A_diag_data[j]; |
1629: } |
1630: } |
1631: j_start = P_offd_start[i1]; |
1632: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1633: for (j=j_start; j < j_end; j++) |
1634: { |
1635: k1 = P_offd_pass[1][j]; |
1636: tmp_marker_offd[C_array_offd[k1]] = i1; |
1637: } |
1638: cnt_offd = P_offd_i[i1]; |
1639: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1640: { |
1641: if (col_offd_S_to_A) |
1642: j1 = map_A_to_S[A_offd_j[j]]; |
1643: else |
1644: j1 = A_offd_j[j]; |
1645: if (CF_marker_offd[j1] != -3 && |
1646: (num_functions == 1 || dof_func[i1] == dof_func_offd[j1])) |
1647: sum_N += A_offd_data[j]; |
1648: if (j1 != -1 && tmp_marker_offd[j1] == i1) |
1649: { |
1650: P_offd_data[cnt_offd] = A_offd_data[j]; |
1651: P_offd_j[cnt_offd++] = map_S_to_new[j1]; |
1652: sum_C += A_offd_data[j]; |
1653: } |
1654: } |
1655: diagonal = A_diag_data[A_diag_i[i1]]; |
1656: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1657: for (j=P_diag_i[i1]; j < cnt; j++) |
1658: P_diag_data[j] *= alfa; |
1659: for (j=P_offd_i[i1]; j < cnt_offd; j++) |
1660: P_offd_data[j] *= alfa; |
1661: } |
1662: hypre_TFree(tmp_marker); |
1663: hypre_TFree(tmp_marker_offd); |
0x46fd50 PUSH %RBP |
0x46fd51 MOV %RSP,%RBP |
0x46fd54 PUSH %R15 |
0x46fd56 PUSH %R14 |
0x46fd58 PUSH %R13 |
0x46fd5a PUSH %R12 |
0x46fd5c PUSH %RBX |
0x46fd5d AND $-0x20,%RSP |
0x46fd61 SUB $0x100,%RSP |
0x46fd68 MOV 0xf8(%RDI),%RAX |
0x46fd6f MOV 0xe0(%RDI),%RCX |
0x46fd76 MOV 0xd8(%RDI),%RSI |
0x46fd7d MOV 0xd0(%RDI),%R8 |
0x46fd84 MOV 0xc8(%RDI),%R9 |
0x46fd8b MOV 0xc0(%RDI),%R10 |
0x46fd92 MOV %RAX,0xe0(%RSP) |
0x46fd9a MOV 0xb8(%RDI),%R11 |
0x46fda1 MOV 0xb0(%RDI),%R12 |
0x46fda8 MOV %RCX,0x8(%RSP) |
0x46fdad MOV 0xa8(%RDI),%R13 |
0x46fdb4 MOV 0x90(%RDI),%RAX |
0x46fdbb MOV %RSI,0xa0(%RSP) |
0x46fdc3 MOV 0xf0(%RDI),%RDX |
0x46fdca MOV 0xe8(%RDI),%RBX |
0x46fdd1 MOV %R8,0x38(%RSP) |
0x46fdd6 MOV %R9,0x30(%RSP) |
0x46fddb MOV 0xa0(%RDI),%R14 |
0x46fde2 MOV %R10,0x70(%RSP) |
0x46fde7 MOV 0x98(%RDI),%R15 |
0x46fdee MOV %R11,0x68(%RSP) |
0x46fdf3 MOV %R12,0xd8(%RSP) |
0x46fdfb MOV %R13,0x80(%RSP) |
0x46fe03 MOV %RAX,0xc8(%RSP) |
0x46fe0b MOV %RDX,0xa8(%RSP) |
0x46fe13 MOV 0x88(%RDI),%RDX |
0x46fe1a MOV 0x80(%RDI),%RCX |
0x46fe21 MOV 0x78(%RDI),%RSI |
0x46fe25 MOV 0x68(%RDI),%R8 |
0x46fe29 MOV 0x60(%RDI),%R9 |
0x46fe2d MOV %RDX,0x28(%RSP) |
0x46fe32 MOV 0x40(%RDI),%RAX |
0x46fe36 MOV 0x38(%RDI),%RDX |
0x46fe3a MOV %RCX,0x98(%RSP) |
0x46fe42 MOV 0x70(%RDI),%R10 |
0x46fe46 MOV 0x30(%RDI),%RCX |
0x46fe4a MOV %RSI,0x60(%RSP) |
0x46fe4f MOV 0x58(%RDI),%R11 |
0x46fe53 MOV 0x28(%RDI),%RSI |
0x46fe57 MOV %R8,0x90(%RSP) |
0x46fe5f MOV 0x50(%RDI),%R12 |
0x46fe63 MOV 0x20(%RDI),%R8 |
0x46fe67 MOV %R9,0x58(%RSP) |
0x46fe6c MOV 0x48(%RDI),%R13 |
0x46fe70 MOV 0x18(%RDI),%R9 |
0x46fe74 MOV %RAX,0x50(%RSP) |
0x46fe79 MOV %RDX,0xe8(%RSP) |
0x46fe81 MOV 0x10(%RDI),%RAX |
0x46fe85 MOV 0x8(%RDI),%RDX |
0x46fe89 MOV (%RDI),%RDI |
0x46fe8c MOV %RCX,0x20(%RSP) |
0x46fe91 MOV %RSI,0x48(%RSP) |
0x46fe96 MOV %R8,0xf8(%RSP) |
0x46fe9e MOV %R9,0x18(%RSP) |
0x46fea3 MOV %RAX,0xd0(%RSP) |
0x46feab MOV %RDX,0xf0(%RSP) |
0x46feb3 MOV %RDI,0x10(%RSP) |
0x46feb8 TEST %RBX,%RBX |
0x46febb JNE 470a9e |
0x46fec1 TEST %R12,%R12 |
0x46fec4 JNE 470c20 |
0x46feca XOR %EBX,%EBX |
0x46fecc XOR %R12D,%R12D |
0x46fecf MOV %R11,0x88(%RSP) |
0x46fed7 MOV %R10,0xb0(%RSP) |
0x46fedf VMOVSD %XMM1,0xb8(%RSP) |
0x46fee8 CALL 5989f0 <hypre_GetThreadNum> |
0x46feed MOV %RAX,0xc0(%RSP) |
0x46fef5 CALL 5989e0 <hypre_NumActiveThreads> |
0x46fefa MOV 0xc0(%RSP),%R10 |
0x46ff02 MOV 0xd8(%RSP),%R8 |
0x46ff0a MOV %RAX,%R9 |
0x46ff0d MOV 0xe0(%RSP),%RAX |
0x46ff15 MOV 0xe0(%RSP),%RSI |
0x46ff1d MOV %R10,%R11 |
0x46ff20 MOV 0x8(%R8),%RCX |
0x46ff24 VMOVSD 0xb8(%RSP),%XMM11 |
0x46ff2d CQTO |
0x46ff2f IDIV %R9 |
0x46ff32 ADD %RCX,%RSI |
0x46ff35 DEC %R9 |
0x46ff38 MOV %RSI,%R8 |
0x46ff3b IMUL %RAX,%R11 |
0x46ff3f ADD %R11,%RAX |
0x46ff42 LEA (%RCX,%R11,1),%RDI |
0x46ff46 MOV 0x88(%RSP),%R11 |
0x46ff4e ADD %RCX,%RAX |
0x46ff51 CMP %R9,%R10 |
0x46ff54 MOV 0xb0(%RSP),%R10 |
0x46ff5c CMOVNE %RAX,%R8 |
0x46ff60 CMP %RDI,%R8 |
0x46ff63 JLE 47084e |
0x46ff69 MOV 0x80(%RSP),%R9 |
0x46ff71 VMOVQ 0x12edc7(%RIP),%XMM5 |
0x46ff79 VXORPD %XMM4,%XMM4,%XMM4 |
0x46ff7d LEA (%R9,%RDI,8),%RCX |
0x46ff81 LEA (%R9,%R8,8),%RAX |
0x46ff85 MOV %RCX,0xd8(%RSP) |
0x46ff8d MOV %RAX,0x40(%RSP) |
0x46ff92 NOPW (%RAX,%RAX,1) |
(660) 0x46ff98 MOV 0xd8(%RSP),%RDX |
(660) 0x46ffa0 MOV 0x58(%RSP),%RCX |
(660) 0x46ffa5 MOV 0x68(%RSP),%RDI |
(660) 0x46ffaa MOV (%RDX),%RDX |
(660) 0x46ffad LEA (,%RDX,8),%R8 |
(660) 0x46ffb5 MOV (%RDI,%RDX,8),%R9 |
(660) 0x46ffb9 LEA (%RCX,%R8,1),%RAX |
(660) 0x46ffbd LEA 0x8(%R8),%RSI |
(660) 0x46ffc1 MOV (%RAX),%RDI |
(660) 0x46ffc4 MOV %RAX,0xc0(%RSP) |
(660) 0x46ffcc MOV 0x8(%RCX,%R8,1),%RAX |
(660) 0x46ffd1 MOV %RSI,0xe0(%RSP) |
(660) 0x46ffd9 ADD %R9,%RAX |
(660) 0x46ffdc SUB %RDI,%RAX |
(660) 0x46ffdf CMP %RAX,%R9 |
(660) 0x46ffe2 JGE 470129 |
(660) 0x46ffe8 MOV 0x30(%RSP),%RDI |
(660) 0x46ffed MOV 0x8(%RDI),%RSI |
(660) 0x46fff1 LEA (%RSI,%RAX,8),%RDI |
(660) 0x46fff5 LEA (%RSI,%R9,8),%RCX |
(660) 0x46fff9 MOV %RDI,%R9 |
(660) 0x46fffc SUB %RCX,%R9 |
(660) 0x46ffff SUB $0x8,%R9 |
(660) 0x470003 SHR $0x3,%R9 |
(660) 0x470007 INC %R9 |
(660) 0x47000a AND $0x7,%R9D |
(660) 0x47000e JE 4700a6 |
(660) 0x470014 CMP $0x1,%R9 |
(660) 0x470018 JE 470092 |
(660) 0x47001a CMP $0x2,%R9 |
(660) 0x47001e JE 470083 |
(660) 0x470020 CMP $0x3,%R9 |
(660) 0x470024 JE 470074 |
(660) 0x470026 CMP $0x4,%R9 |
(660) 0x47002a JE 470065 |
(660) 0x47002c CMP $0x5,%R9 |
(660) 0x470030 JE 470056 |
(660) 0x470032 CMP $0x6,%R9 |
(660) 0x470036 JE 470047 |
(660) 0x470038 MOV (%RCX),%RAX |
(660) 0x47003b ADD $0x8,%RCX |
(660) 0x47003f MOV (%R15,%RAX,8),%RSI |
(660) 0x470043 MOV %RDX,(%R12,%RSI,8) |
(660) 0x470047 MOV (%RCX),%R9 |
(660) 0x47004a ADD $0x8,%RCX |
(660) 0x47004e MOV (%R15,%R9,8),%RAX |
(660) 0x470052 MOV %RDX,(%R12,%RAX,8) |
(660) 0x470056 MOV (%RCX),%RSI |
(660) 0x470059 ADD $0x8,%RCX |
(660) 0x47005d MOV (%R15,%RSI,8),%R9 |
(660) 0x470061 MOV %RDX,(%R12,%R9,8) |
(660) 0x470065 MOV (%RCX),%RAX |
(660) 0x470068 ADD $0x8,%RCX |
(660) 0x47006c MOV (%R15,%RAX,8),%RSI |
(660) 0x470070 MOV %RDX,(%R12,%RSI,8) |
(660) 0x470074 MOV (%RCX),%R9 |
(660) 0x470077 ADD $0x8,%RCX |
(660) 0x47007b MOV (%R15,%R9,8),%RAX |
(660) 0x47007f MOV %RDX,(%R12,%RAX,8) |
(660) 0x470083 MOV (%RCX),%RSI |
(660) 0x470086 ADD $0x8,%RCX |
(660) 0x47008a MOV (%R15,%RSI,8),%R9 |
(660) 0x47008e MOV %RDX,(%R12,%R9,8) |
(660) 0x470092 MOV (%RCX),%RAX |
(660) 0x470095 ADD $0x8,%RCX |
(660) 0x470099 MOV (%R15,%RAX,8),%RSI |
(660) 0x47009d MOV %RDX,(%R12,%RSI,8) |
(660) 0x4700a1 CMP %RCX,%RDI |
(660) 0x4700a4 JE 47011e |
(660) 0x4700a6 MOV 0xe0(%RSP),%R9 |
(669) 0x4700ae MOV (%RCX),%RAX |
(669) 0x4700b1 ADD $0x40,%RCX |
(669) 0x4700b5 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700b9 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700bd MOV -0x38(%RCX),%RAX |
(669) 0x4700c1 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700c5 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700c9 MOV -0x30(%RCX),%RAX |
(669) 0x4700cd MOV (%R15,%RAX,8),%RSI |
(669) 0x4700d1 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700d5 MOV -0x28(%RCX),%RAX |
(669) 0x4700d9 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700dd MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700e1 MOV -0x20(%RCX),%RAX |
(669) 0x4700e5 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700e9 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700ed MOV -0x18(%RCX),%RAX |
(669) 0x4700f1 MOV (%R15,%RAX,8),%RSI |
(669) 0x4700f5 MOV %RDX,(%R12,%RSI,8) |
(669) 0x4700f9 MOV -0x10(%RCX),%RAX |
(669) 0x4700fd MOV (%R15,%RAX,8),%RSI |
(669) 0x470101 MOV %RDX,(%R12,%RSI,8) |
(669) 0x470105 MOV -0x8(%RCX),%RAX |
(669) 0x470109 MOV (%R15,%RAX,8),%RSI |
(669) 0x47010d MOV %RDX,(%R12,%RSI,8) |
(669) 0x470111 CMP %RCX,%RDI |
(669) 0x470114 JNE 4700ae |
(660) 0x470116 MOV %R9,0xe0(%RSP) |
(660) 0x47011e MOV 0xc0(%RSP),%RCX |
(660) 0x470126 MOV (%RCX),%RDI |
(660) 0x470129 MOV 0x48(%RSP),%RSI |
(660) 0x47012e MOV 0xe0(%RSP),%RCX |
(660) 0x470136 VXORPD %XMM0,%XMM0,%XMM0 |
(660) 0x47013a VMOVSD %XMM0,%XMM0,%XMM2 |
(660) 0x47013e LEA (%RSI,%R8,1),%R9 |
(660) 0x470142 ADD %RCX,%RSI |
(660) 0x470145 MOV (%R9),%RAX |
(660) 0x470148 MOV %R9,0xb0(%RSP) |
(660) 0x470150 MOV %RAX,0xb8(%RSP) |
(660) 0x470158 INC %RAX |
(660) 0x47015b CMP (%RSI),%RAX |
(660) 0x47015e JGE 470237 |
(660) 0x470164 CMPQ $0x1,0xf0(%RSP) |
(660) 0x47016d MOV %RBX,0xb8(%RSP) |
(660) 0x470175 JE 470870 |
(660) 0x47017b MOV %R14,0x88(%RSP) |
(660) 0x470183 MOV 0x20(%RSP),%R9 |
(660) 0x470188 MOV %R10,0x80(%RSP) |
(660) 0x470190 MOV 0xd0(%RSP),%R10 |
(660) 0x470198 MOV %R13,0x78(%RSP) |
(660) 0x47019d MOV 0x10(%RSP),%R13 |
(660) 0x4701a2 NOPW (%RAX,%RAX,1) |
(668) 0x4701a8 MOV (%R9,%RAX,8),%RCX |
(668) 0x4701ac CMPQ $-0x3,(%R13,%RCX,8) |
(668) 0x4701b2 JE 4701cb |
(668) 0x4701b4 MOV (%R10,%RCX,8),%R14 |
(668) 0x4701b8 CMP %R14,(%R10,%R8,1) |
(668) 0x4701bc JNE 4701cb |
(668) 0x4701be MOV 0xf8(%RSP),%RBX |
(668) 0x4701c6 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(668) 0x4701cb CMP $-0x1,%RCX |
(668) 0x4701cf JE 470212 |
(668) 0x4701d1 CMP (%R12,%RCX,8),%RDX |
(668) 0x4701d5 JNE 470212 |
(668) 0x4701d7 MOV 0xf8(%RSP),%R14 |
(668) 0x4701df LEA (,%RDI,8),%RBX |
(668) 0x4701e7 VMOVSD (%R14,%RAX,8),%XMM6 |
(668) 0x4701ed MOV 0xa8(%RSP),%R14 |
(668) 0x4701f5 MOV (%R14,%RCX,8),%RCX |
(668) 0x4701f9 MOV 0x90(%RSP),%R14 |
(668) 0x470201 VMOVSD %XMM6,(%R11,%RDI,8) |
(668) 0x470207 VADDSD %XMM6,%XMM2,%XMM2 |
(668) 0x47020b INC %RDI |
(668) 0x47020e MOV %RCX,(%R14,%RBX,1) |
(668) 0x470212 INC %RAX |
(668) 0x470215 CMP (%RSI),%RAX |
(668) 0x470218 JL 4701a8 |
(660) 0x47021a MOV 0xb8(%RSP),%RBX |
(660) 0x470222 MOV 0x88(%RSP),%R14 |
(660) 0x47022a MOV 0x80(%RSP),%R10 |
(660) 0x470232 MOV 0x78(%RSP),%R13 |
(660) 0x470237 MOV 0x60(%RSP),%R9 |
(660) 0x47023c MOV 0x70(%RSP),%RSI |
(660) 0x470241 MOV %R9,%RAX |
(660) 0x470244 MOV (%RSI,%RDX,8),%RCX |
(660) 0x470248 ADD %R8,%RAX |
(660) 0x47024b MOV (%RAX),%RSI |
(660) 0x47024e MOV %RAX,0xb8(%RSP) |
(660) 0x470256 MOV 0x8(%R9,%R8,1),%RAX |
(660) 0x47025b ADD %RCX,%RAX |
(660) 0x47025e SUB %RSI,%RAX |
(660) 0x470261 CMP %RAX,%RCX |
(660) 0x470264 JGE 4703aa |
(660) 0x47026a MOV 0x38(%RSP),%RSI |
(660) 0x47026f MOV 0x8(%RSI),%R9 |
(660) 0x470273 LEA (%R9,%RAX,8),%RSI |
(660) 0x470277 LEA (%R9,%RCX,8),%RCX |
(660) 0x47027b MOV %RSI,%RAX |
(660) 0x47027e SUB %RCX,%RAX |
(660) 0x470281 SUB $0x8,%RAX |
(660) 0x470285 SHR $0x3,%RAX |
(660) 0x470289 INC %RAX |
(660) 0x47028c AND $0x7,%EAX |
(660) 0x47028f JE 470327 |
(660) 0x470295 CMP $0x1,%RAX |
(660) 0x470299 JE 470313 |
(660) 0x47029b CMP $0x2,%RAX |
(660) 0x47029f JE 470304 |
(660) 0x4702a1 CMP $0x3,%RAX |
(660) 0x4702a5 JE 4702f5 |
(660) 0x4702a7 CMP $0x4,%RAX |
(660) 0x4702ab JE 4702e6 |
(660) 0x4702ad CMP $0x5,%RAX |
(660) 0x4702b1 JE 4702d7 |
(660) 0x4702b3 CMP $0x6,%RAX |
(660) 0x4702b7 JE 4702c8 |
(660) 0x4702b9 MOV (%RCX),%R9 |
(660) 0x4702bc ADD $0x8,%RCX |
(660) 0x4702c0 MOV (%R14,%R9,8),%RAX |
(660) 0x4702c4 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702c8 MOV (%RCX),%R9 |
(660) 0x4702cb ADD $0x8,%RCX |
(660) 0x4702cf MOV (%R14,%R9,8),%RAX |
(660) 0x4702d3 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702d7 MOV (%RCX),%R9 |
(660) 0x4702da ADD $0x8,%RCX |
(660) 0x4702de MOV (%R14,%R9,8),%RAX |
(660) 0x4702e2 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702e6 MOV (%RCX),%R9 |
(660) 0x4702e9 ADD $0x8,%RCX |
(660) 0x4702ed MOV (%R14,%R9,8),%RAX |
(660) 0x4702f1 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x4702f5 MOV (%RCX),%R9 |
(660) 0x4702f8 ADD $0x8,%RCX |
(660) 0x4702fc MOV (%R14,%R9,8),%RAX |
(660) 0x470300 MOV %RDX,(%RBX,%RAX,8) |
(660) 0x470304 MOV (%RCX),%R9 |
(660) 0x470307 ADD $0x8,%RCX |
(660) 0x47030b MOV (%R14,%R9,8),%RAX |
(660) 0x47030f MOV %RDX,(%RBX,%RAX,8) |
(660) 0x470313 MOV (%RCX),%R9 |
(660) 0x470316 ADD $0x8,%RCX |
(660) 0x47031a MOV (%R14,%R9,8),%RAX |
(660) 0x47031e MOV %RDX,(%RBX,%RAX,8) |
(660) 0x470322 CMP %RCX,%RSI |
(660) 0x470325 JE 47039f |
(660) 0x470327 MOV 0xe0(%RSP),%R9 |
(666) 0x47032f MOV (%RCX),%RAX |
(666) 0x470332 ADD $0x40,%RCX |
(666) 0x470336 MOV (%R14,%RAX,8),%RAX |
(666) 0x47033a MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47033e MOV -0x38(%RCX),%RAX |
(666) 0x470342 MOV (%R14,%RAX,8),%RAX |
(666) 0x470346 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47034a MOV -0x30(%RCX),%RAX |
(666) 0x47034e MOV (%R14,%RAX,8),%RAX |
(666) 0x470352 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470356 MOV -0x28(%RCX),%RAX |
(666) 0x47035a MOV (%R14,%RAX,8),%RAX |
(666) 0x47035e MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470362 MOV -0x20(%RCX),%RAX |
(666) 0x470366 MOV (%R14,%RAX,8),%RAX |
(666) 0x47036a MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47036e MOV -0x18(%RCX),%RAX |
(666) 0x470372 MOV (%R14,%RAX,8),%RAX |
(666) 0x470376 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x47037a MOV -0x10(%RCX),%RAX |
(666) 0x47037e MOV (%R14,%RAX,8),%RAX |
(666) 0x470382 MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470386 MOV -0x8(%RCX),%RAX |
(666) 0x47038a MOV (%R14,%RAX,8),%RAX |
(666) 0x47038e MOV %RDX,(%RBX,%RAX,8) |
(666) 0x470392 CMP %RCX,%RSI |
(666) 0x470395 JNE 47032f |
(660) 0x470397 MOV %R9,0xe0(%RSP) |
(660) 0x47039f MOV 0xb8(%RSP),%RCX |
(660) 0x4703a7 MOV (%RCX),%RSI |
(660) 0x4703aa MOV 0x50(%RSP),%RCX |
(660) 0x4703af MOV 0xe0(%RSP),%R9 |
(660) 0x4703b7 MOV (%RCX,%RDX,8),%RAX |
(660) 0x4703bb ADD %RCX,%R9 |
(660) 0x4703be CMP %RAX,(%R9) |
(660) 0x4703c1 JLE 4709f0 |
(660) 0x4703c7 CMPQ $0,0x18(%RSP) |
(660) 0x4703cd JE 470918 |
(660) 0x4703d3 MOV %R11,0x80(%RSP) |
(660) 0x4703db MOV 0x28(%RSP),%R11 |
(660) 0x4703e0 MOV %RDI,0x78(%RSP) |
(660) 0x4703e5 MOV 0x8(%RSP),%RDI |
(660) 0x4703ea MOV %R12,0xe0(%RSP) |
(660) 0x4703f2 MOV %R14,0x88(%RSP) |
(660) 0x4703fa JMP 470469 |
0x4703fc NOPL (%RAX) |
(665) 0x470400 MOV 0xc8(%RSP),%R14 |
(665) 0x470408 MOV 0xd0(%RSP),%R12 |
(665) 0x470410 MOV (%R14,%RCX,8),%R14 |
(665) 0x470414 CMP %R14,(%R12,%R8,1) |
(665) 0x470418 JE 470488 |
(665) 0x47041a CMP $-0x1,%RCX |
(665) 0x47041e JE 470461 |
(665) 0x470420 CMP (%RBX,%RCX,8),%RDX |
(665) 0x470424 JNE 470461 |
(665) 0x470426 MOV 0xe8(%RSP),%R14 |
(665) 0x47042e LEA (,%RSI,8),%R12 |
(665) 0x470436 VMOVSD (%R14,%RAX,8),%XMM7 |
(665) 0x47043c MOV 0xa0(%RSP),%R14 |
(665) 0x470444 MOV (%R14,%RCX,8),%RCX |
(665) 0x470448 MOV 0x98(%RSP),%R14 |
(665) 0x470450 VMOVSD %XMM7,(%R10,%RSI,8) |
(665) 0x470456 VADDSD %XMM7,%XMM2,%XMM2 |
(665) 0x47045a INC %RSI |
(665) 0x47045d MOV %RCX,(%R14,%R12,1) |
(665) 0x470461 INC %RAX |
(665) 0x470464 CMP (%R9),%RAX |
(665) 0x470467 JGE 4704a0 |
(665) 0x470469 MOV (%R13,%RAX,8),%R12 |
(665) 0x47046e MOV (%RDI,%R12,8),%RCX |
(665) 0x470472 CMPQ $-0x3,(%R11,%RCX,8) |
(665) 0x470477 JE 47041a |
(665) 0x470479 CMPQ $0x1,0xf0(%RSP) |
(665) 0x470482 JNE 470400 |
(665) 0x470488 MOV 0xe8(%RSP),%R12 |
(665) 0x470490 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(665) 0x470496 JMP 47041a |
0x470498 NOPL (%RAX,%RAX,1) |
(660) 0x4704a0 MOV 0xe0(%RSP),%R12 |
(660) 0x4704a8 MOV 0x88(%RSP),%R14 |
(660) 0x4704b0 MOV 0x80(%RSP),%R11 |
(660) 0x4704b8 MOV 0x78(%RSP),%RDI |
(660) 0x4704bd MOV 0xb8(%RSP),%RDX |
(660) 0x4704c5 MOV (%RDX),%R8 |
(660) 0x4704c8 MOV 0xb0(%RSP),%RAX |
(660) 0x4704d0 MOV 0xf8(%RSP),%RCX |
(660) 0x4704d8 MOV (%RAX),%R9 |
(660) 0x4704db VMULSD (%RCX,%R9,8),%XMM2,%XMM10 |
(660) 0x4704e1 VCOMISD %XMM4,%XMM10 |
(660) 0x4704e5 JE 4704f0 |
(660) 0x4704e7 VXORPD %XMM5,%XMM0,%XMM1 |
(660) 0x4704eb VDIVSD %XMM10,%XMM1,%XMM11 |
(660) 0x4704f0 MOV 0xc0(%RSP),%RDX |
(660) 0x4704f8 MOV (%RDX),%RCX |
(660) 0x4704fb CMP %RDI,%RCX |
(660) 0x4704fe JGE 47068a |
(660) 0x470504 SUB %RCX,%RDI |
(660) 0x470507 MOV %RCX,0xe0(%RSP) |
(660) 0x47050f LEA -0x1(%RDI),%RAX |
(660) 0x470513 CMP $0x2,%RAX |
(660) 0x470517 JBE 470a8f |
(660) 0x47051d MOV %RDI,%RDX |
(660) 0x470520 LEA (%R11,%RCX,8),%RAX |
(660) 0x470524 VBROADCASTSD %XMM11,%YMM12 |
(660) 0x470529 SHR $0x2,%RDX |
(660) 0x47052d SAL $0x5,%RDX |
(660) 0x470531 LEA (%RDX,%RAX,1),%R9 |
(660) 0x470535 SUB $0x20,%RDX |
(660) 0x470539 SHR $0x5,%RDX |
(660) 0x47053d INC %RDX |
(660) 0x470540 AND $0x7,%EDX |
(660) 0x470543 JE 4705cd |
(660) 0x470549 CMP $0x1,%RDX |
(660) 0x47054d JE 4705bb |
(660) 0x47054f CMP $0x2,%RDX |
(660) 0x470553 JE 4705ae |
(660) 0x470555 CMP $0x3,%RDX |
(660) 0x470559 JE 4705a1 |
(660) 0x47055b CMP $0x4,%RDX |
(660) 0x47055f JE 470594 |
(660) 0x470561 CMP $0x5,%RDX |
(660) 0x470565 JE 470587 |
(660) 0x470567 CMP $0x6,%RDX |
(660) 0x47056b JE 47057a |
(660) 0x47056d VMULPD (%RAX),%YMM12,%YMM13 |
(660) 0x470571 ADD $0x20,%RAX |
(660) 0x470575 VMOVUPD %YMM13,-0x20(%RAX) |
(660) 0x47057a VMULPD (%RAX),%YMM12,%YMM14 |
(660) 0x47057e ADD $0x20,%RAX |
(660) 0x470582 VMOVUPD %YMM14,-0x20(%RAX) |
(660) 0x470587 VMULPD (%RAX),%YMM12,%YMM15 |
(660) 0x47058b ADD $0x20,%RAX |
(660) 0x47058f VMOVUPD %YMM15,-0x20(%RAX) |
(660) 0x470594 VMULPD (%RAX),%YMM12,%YMM0 |
(660) 0x470598 ADD $0x20,%RAX |
(660) 0x47059c VMOVUPD %YMM0,-0x20(%RAX) |
(660) 0x4705a1 VMULPD (%RAX),%YMM12,%YMM3 |
(660) 0x4705a5 ADD $0x20,%RAX |
(660) 0x4705a9 VMOVUPD %YMM3,-0x20(%RAX) |
(660) 0x4705ae VMULPD (%RAX),%YMM12,%YMM2 |
(660) 0x4705b2 ADD $0x20,%RAX |
(660) 0x4705b6 VMOVUPD %YMM2,-0x20(%RAX) |
(660) 0x4705bb VMULPD (%RAX),%YMM12,%YMM6 |
(660) 0x4705bf ADD $0x20,%RAX |
(660) 0x4705c3 VMOVUPD %YMM6,-0x20(%RAX) |
(660) 0x4705c8 CMP %RAX,%R9 |
(660) 0x4705cb JE 47063c |
(662) 0x4705cd VMULPD (%RAX),%YMM12,%YMM7 |
(662) 0x4705d1 ADD $0x100,%RAX |
(662) 0x4705d7 VMULPD -0xe0(%RAX),%YMM12,%YMM8 |
(662) 0x4705df VMULPD -0xc0(%RAX),%YMM12,%YMM9 |
(662) 0x4705e7 VMULPD -0xa0(%RAX),%YMM12,%YMM10 |
(662) 0x4705ef VMULPD -0x80(%RAX),%YMM12,%YMM1 |
(662) 0x4705f4 VMULPD -0x60(%RAX),%YMM12,%YMM13 |
(662) 0x4705f9 VMOVUPD %YMM7,-0x100(%RAX) |
(662) 0x470601 VMULPD -0x40(%RAX),%YMM12,%YMM14 |
(662) 0x470606 VMOVUPD %YMM8,-0xe0(%RAX) |
(662) 0x47060e VMULPD -0x20(%RAX),%YMM12,%YMM15 |
(662) 0x470613 VMOVUPD %YMM9,-0xc0(%RAX) |
(662) 0x47061b VMOVUPD %YMM10,-0xa0(%RAX) |
(662) 0x470623 VMOVUPD %YMM1,-0x80(%RAX) |
(662) 0x470628 VMOVUPD %YMM13,-0x60(%RAX) |
(662) 0x47062d VMOVUPD %YMM14,-0x40(%RAX) |
(662) 0x470632 VMOVUPD %YMM15,-0x20(%RAX) |
(662) 0x470637 CMP %RAX,%R9 |
(662) 0x47063a JNE 4705cd |
(660) 0x47063c TEST $0x3,%DIL |
(660) 0x470640 JE 47068a |
(660) 0x470642 MOV %RDI,%R9 |
(660) 0x470645 AND $-0x4,%R9 |
(660) 0x470649 ADD %R9,%RCX |
(660) 0x47064c SUB %R9,%RDI |
(660) 0x47064f CMP $0x1,%RDI |
(660) 0x470653 JE 47067e |
(660) 0x470655 MOV 0xe0(%RSP),%RAX |
(660) 0x47065d VMOVDDUP %XMM11,%XMM12 |
(660) 0x470662 ADD %R9,%RAX |
(660) 0x470665 LEA (%R11,%RAX,8),%RDX |
(660) 0x470669 VMULPD (%RDX),%XMM12,%XMM0 |
(660) 0x47066d VMOVUPD %XMM0,(%RDX) |
(660) 0x470671 TEST $0x1,%DIL |
(660) 0x470675 JE 47068a |
(660) 0x470677 AND $-0x2,%RDI |
(660) 0x47067b ADD %RDI,%RCX |
(660) 0x47067e LEA (%R11,%RCX,8),%RDI |
(660) 0x470682 VMULSD (%RDI),%XMM11,%XMM3 |
(660) 0x470686 VMOVSD %XMM3,(%RDI) |
(660) 0x47068a CMP %R8,%RSI |
(660) 0x47068d JLE 47082f |
(660) 0x470693 SUB %R8,%RSI |
(660) 0x470696 MOV %R8,%RCX |
(660) 0x470699 LEA -0x1(%RSI),%R9 |
(660) 0x47069d CMP $0x2,%R9 |
(660) 0x4706a1 JBE 470a97 |
(660) 0x4706a7 MOV %RSI,%RDX |
(660) 0x4706aa LEA (%R10,%R8,8),%R9 |
(660) 0x4706ae VBROADCASTSD %XMM11,%YMM6 |
(660) 0x4706b3 SHR $0x2,%RDX |
(660) 0x4706b7 SAL $0x5,%RDX |
(660) 0x4706bb LEA (%RDX,%R9,1),%RDI |
(660) 0x4706bf SUB $0x20,%RDX |
(660) 0x4706c3 SHR $0x5,%RDX |
(660) 0x4706c7 INC %RDX |
(660) 0x4706ca AND $0x7,%EDX |
(660) 0x4706cd JE 470769 |
(660) 0x4706d3 CMP $0x1,%RDX |
(660) 0x4706d7 JE 470751 |
(660) 0x4706d9 CMP $0x2,%RDX |
(660) 0x4706dd JE 470742 |
(660) 0x4706df CMP $0x3,%RDX |
(660) 0x4706e3 JE 470733 |
(660) 0x4706e5 CMP $0x4,%RDX |
(660) 0x4706e9 JE 470724 |
(660) 0x4706eb CMP $0x5,%RDX |
(660) 0x4706ef JE 470715 |
(660) 0x4706f1 CMP $0x6,%RDX |
(660) 0x4706f5 JE 470706 |
(660) 0x4706f7 VMULPD (%R9),%YMM6,%YMM2 |
(660) 0x4706fc ADD $0x20,%R9 |
(660) 0x470700 VMOVUPD %YMM2,-0x20(%R9) |
(660) 0x470706 VMULPD (%R9),%YMM6,%YMM7 |
(660) 0x47070b ADD $0x20,%R9 |
(660) 0x47070f VMOVUPD %YMM7,-0x20(%R9) |
(660) 0x470715 VMULPD (%R9),%YMM6,%YMM8 |
(660) 0x47071a ADD $0x20,%R9 |
(660) 0x47071e VMOVUPD %YMM8,-0x20(%R9) |
(660) 0x470724 VMULPD (%R9),%YMM6,%YMM9 |
(660) 0x470729 ADD $0x20,%R9 |
(660) 0x47072d VMOVUPD %YMM9,-0x20(%R9) |
(660) 0x470733 VMULPD (%R9),%YMM6,%YMM10 |
(660) 0x470738 ADD $0x20,%R9 |
(660) 0x47073c VMOVUPD %YMM10,-0x20(%R9) |
(660) 0x470742 VMULPD (%R9),%YMM6,%YMM1 |
(660) 0x470747 ADD $0x20,%R9 |
(660) 0x47074b VMOVUPD %YMM1,-0x20(%R9) |
(660) 0x470751 VMULPD (%R9),%YMM6,%YMM13 |
(660) 0x470756 ADD $0x20,%R9 |
(660) 0x47075a VMOVUPD %YMM13,-0x20(%R9) |
(660) 0x470760 CMP %R9,%RDI |
(660) 0x470763 JE 4707e9 |
(661) 0x470769 VMULPD (%R9),%YMM6,%YMM14 |
(661) 0x47076e ADD $0x100,%R9 |
(661) 0x470775 VMULPD -0xe0(%R9),%YMM6,%YMM15 |
(661) 0x47077e VMULPD -0xc0(%R9),%YMM6,%YMM12 |
(661) 0x470787 VMULPD -0xa0(%R9),%YMM6,%YMM0 |
(661) 0x470790 VMULPD -0x80(%R9),%YMM6,%YMM3 |
(661) 0x470796 VMULPD -0x60(%R9),%YMM6,%YMM2 |
(661) 0x47079c VMOVUPD %YMM14,-0x100(%R9) |
(661) 0x4707a5 VMULPD -0x40(%R9),%YMM6,%YMM7 |
(661) 0x4707ab VMOVUPD %YMM15,-0xe0(%R9) |
(661) 0x4707b4 VMULPD -0x20(%R9),%YMM6,%YMM8 |
(661) 0x4707ba VMOVUPD %YMM12,-0xc0(%R9) |
(661) 0x4707c3 VMOVUPD %YMM0,-0xa0(%R9) |
(661) 0x4707cc VMOVUPD %YMM3,-0x80(%R9) |
(661) 0x4707d2 VMOVUPD %YMM2,-0x60(%R9) |
(661) 0x4707d8 VMOVUPD %YMM7,-0x40(%R9) |
(661) 0x4707de VMOVUPD %YMM8,-0x20(%R9) |
(661) 0x4707e4 CMP %R9,%RDI |
(661) 0x4707e7 JNE 470769 |
(660) 0x4707e9 TEST $0x3,%SIL |
(660) 0x4707ed JE 47082f |
(660) 0x4707ef MOV %RSI,%RAX |
(660) 0x4707f2 AND $-0x4,%RAX |
(660) 0x4707f6 ADD %RAX,%R8 |
(660) 0x4707f9 SUB %RAX,%RSI |
(660) 0x4707fc CMP $0x1,%RSI |
(660) 0x470800 JE 470823 |
(660) 0x470802 ADD %RCX,%RAX |
(660) 0x470805 VMOVDDUP %XMM11,%XMM6 |
(660) 0x47080a LEA (%R10,%RAX,8),%RCX |
(660) 0x47080e VMULPD (%RCX),%XMM6,%XMM9 |
(660) 0x470812 VMOVUPD %XMM9,(%RCX) |
(660) 0x470816 TEST $0x1,%SIL |
(660) 0x47081a JE 47082f |
(660) 0x47081c AND $-0x2,%RSI |
(660) 0x470820 ADD %RSI,%R8 |
(660) 0x470823 LEA (%R10,%R8,8),%RSI |
(660) 0x470827 VMULSD (%RSI),%XMM11,%XMM10 |
(660) 0x47082b VMOVSD %XMM10,(%RSI) |
(660) 0x47082f ADDQ $0x8,0xd8(%RSP) |
(660) 0x470838 MOV 0xd8(%RSP),%R8 |
(660) 0x470840 CMP %R8,0x40(%RSP) |
(660) 0x470845 JNE 46ff98 |
0x47084b VZEROUPPER |
0x47084e MOV %R12,%RDI |
0x470851 CALL 595a80 <hypre_Free> |
0x470856 LEA -0x28(%RBP),%RSP |
0x47085a MOV %RBX,%RDI |
0x47085d POP %RBX |
0x47085e POP %R12 |
0x470860 POP %R13 |
0x470862 POP %R14 |
0x470864 POP %R15 |
0x470866 POP %RBP |
0x470867 JMP 595a80 |
0x47086c NOPL (%RAX) |
(660) 0x470870 MOV %R10,0x88(%RSP) |
(660) 0x470878 MOV 0x10(%RSP),%R9 |
(660) 0x47087d MOV %R8,0x80(%RSP) |
(660) 0x470885 MOV 0x20(%RSP),%R8 |
(660) 0x47088a NOPW (%RAX,%RAX,1) |
(667) 0x470890 MOV (%R8,%RAX,8),%RCX |
(667) 0x470894 CMPQ $-0x3,(%R9,%RCX,8) |
(667) 0x470899 JE 4708a8 |
(667) 0x47089b MOV 0xf8(%RSP),%RBX |
(667) 0x4708a3 VADDSD (%RBX,%RAX,8),%XMM0,%XMM0 |
(667) 0x4708a8 CMP $-0x1,%RCX |
(667) 0x4708ac JE 4708ef |
(667) 0x4708ae CMP (%R12,%RCX,8),%RDX |
(667) 0x4708b2 JNE 4708ef |
(667) 0x4708b4 MOV 0xf8(%RSP),%R10 |
(667) 0x4708bc LEA (,%RDI,8),%RBX |
(667) 0x4708c4 VMOVSD (%R10,%RAX,8),%XMM3 |
(667) 0x4708ca MOV 0xa8(%RSP),%R10 |
(667) 0x4708d2 MOV (%R10,%RCX,8),%RCX |
(667) 0x4708d6 MOV 0x90(%RSP),%R10 |
(667) 0x4708de VMOVSD %XMM3,(%R11,%RDI,8) |
(667) 0x4708e4 VADDSD %XMM3,%XMM2,%XMM2 |
(667) 0x4708e8 INC %RDI |
(667) 0x4708eb MOV %RCX,(%R10,%RBX,1) |
(667) 0x4708ef INC %RAX |
(667) 0x4708f2 CMP (%RSI),%RAX |
(667) 0x4708f5 JL 470890 |
(660) 0x4708f7 MOV 0xb8(%RSP),%RBX |
(660) 0x4708ff MOV 0x88(%RSP),%R10 |
(660) 0x470907 MOV 0x80(%RSP),%R8 |
(660) 0x47090f JMP 470237 |
0x470914 NOPL (%RAX) |
(660) 0x470918 CMPQ $0x1,0xf0(%RSP) |
(660) 0x470921 JE 4709f8 |
(660) 0x470927 MOV %R12,0xe0(%RSP) |
(660) 0x47092f MOV %R11,0x88(%RSP) |
(660) 0x470937 MOV %RDI,0x80(%RSP) |
(660) 0x47093f MOV 0x28(%RSP),%RDI |
(660) 0x470944 NOPL (%RAX) |
(664) 0x470948 MOV (%R13,%RAX,8),%RCX |
(664) 0x47094d CMPQ $-0x3,(%RDI,%RCX,8) |
(664) 0x470952 JE 47097c |
(664) 0x470954 MOV 0xd0(%RSP),%R11 |
(664) 0x47095c MOV 0xc8(%RSP),%R12 |
(664) 0x470964 MOV (%R11,%R8,1),%R11 |
(664) 0x470968 CMP %R11,(%R12,%RCX,8) |
(664) 0x47096c JNE 47097c |
(664) 0x47096e MOV 0xe8(%RSP),%R12 |
(664) 0x470976 VADDSD (%R12,%RAX,8),%XMM0,%XMM0 |
(664) 0x47097c CMP $-0x1,%RCX |
(664) 0x470980 JE 4709c4 |
(664) 0x470982 CMP (%RBX,%RCX,8),%RDX |
(664) 0x470986 JNE 4709c4 |
(664) 0x470988 MOV 0xe8(%RSP),%R11 |
(664) 0x470990 LEA (,%RSI,8),%R12 |
(664) 0x470998 VMOVSD (%R11,%RAX,8),%XMM9 |
(664) 0x47099e MOV 0xa0(%RSP),%R11 |
(664) 0x4709a6 MOV (%R11,%RCX,8),%RCX |
(664) 0x4709aa MOV 0x98(%RSP),%R11 |
(664) 0x4709b2 VMOVSD %XMM9,(%R10,%RSI,8) |
(664) 0x4709b8 VADDSD %XMM9,%XMM2,%XMM2 |
(664) 0x4709bd INC %RSI |
(664) 0x4709c0 MOV %RCX,(%R11,%R12,1) |
(664) 0x4709c4 INC %RAX |
(664) 0x4709c7 CMP %RAX,(%R9) |
(664) 0x4709ca JG 470948 |
(660) 0x4709d0 MOV 0xe0(%RSP),%R12 |
(660) 0x4709d8 MOV 0x88(%RSP),%R11 |
(660) 0x4709e0 MOV 0x80(%RSP),%RDI |
(660) 0x4709e8 JMP 4704bd |
0x4709ed NOPL (%RAX) |
(660) 0x4709f0 MOV %RSI,%R8 |
(660) 0x4709f3 JMP 4704c8 |
(660) 0x4709f8 MOV %R11,0xe0(%RSP) |
(660) 0x470a00 MOV %RDI,0x88(%RSP) |
(660) 0x470a08 MOV 0x28(%RSP),%RDI |
(660) 0x470a0d NOPL (%RAX) |
(663) 0x470a10 MOV (%R13,%RAX,8),%RCX |
(663) 0x470a15 CMPQ $-0x3,(%RDI,%RCX,8) |
(663) 0x470a1a JE 470a2a |
(663) 0x470a1c MOV 0xe8(%RSP),%R8 |
(663) 0x470a24 VADDSD (%R8,%RAX,8),%XMM0,%XMM0 |
(663) 0x470a2a CMP $-0x1,%RCX |
(663) 0x470a2e JE 470a72 |
(663) 0x470a30 CMP (%RBX,%RCX,8),%RDX |
(663) 0x470a34 JNE 470a72 |
(663) 0x470a36 MOV 0xe8(%RSP),%R11 |
(663) 0x470a3e LEA (,%RSI,8),%R8 |
(663) 0x470a46 VMOVSD (%R11,%RAX,8),%XMM8 |
(663) 0x470a4c MOV 0xa0(%RSP),%R11 |
(663) 0x470a54 MOV (%R11,%RCX,8),%RCX |
(663) 0x470a58 MOV 0x98(%RSP),%R11 |
(663) 0x470a60 VMOVSD %XMM8,(%R10,%RSI,8) |
(663) 0x470a66 VADDSD %XMM8,%XMM2,%XMM2 |
(663) 0x470a6b INC %RSI |
(663) 0x470a6e MOV %RCX,(%R11,%R8,1) |
(663) 0x470a72 INC %RAX |
(663) 0x470a75 CMP %RAX,(%R9) |
(663) 0x470a78 JG 470a10 |
(660) 0x470a7a MOV 0xe0(%RSP),%R11 |
(660) 0x470a82 MOV 0x88(%RSP),%RDI |
(660) 0x470a8a JMP 4704bd |
(660) 0x470a8f XOR %R9D,%R9D |
(660) 0x470a92 JMP 47064c |
(660) 0x470a97 XOR %EAX,%EAX |
(660) 0x470a99 JMP 4707f9 |
0x470a9e MOV $0x8,%ESI |
0x470aa3 MOV %RBX,%RDI |
0x470aa6 MOV %R12,0x78(%RSP) |
0x470aab MOV %R11,0x88(%RSP) |
0x470ab3 MOV %R10,0xb0(%RSP) |
0x470abb VMOVSD %XMM1,0xb8(%RSP) |
0x470ac4 MOV %RBX,0xc0(%RSP) |
0x470acc CALL 5959c0 <hypre_CAlloc> |
0x470ad1 MOV 0x78(%RSP),%RCX |
0x470ad6 MOV 0xc0(%RSP),%RDX |
0x470ade VMOVSD 0xb8(%RSP),%XMM1 |
0x470ae7 MOV 0xb0(%RSP),%R10 |
0x470aef MOV %RAX,%R12 |
0x470af2 TEST %RCX,%RCX |
0x470af5 MOV 0x88(%RSP),%R11 |
0x470afd JNE 470bb6 |
0x470b03 XOR %EBX,%EBX |
0x470b05 TEST %RDX,%RDX |
0x470b08 JLE 46fecf |
0x470b0e SAL $0x3,%RDX |
0x470b12 MOV $0xff,%ESI |
0x470b17 MOV %R12,%RDI |
0x470b1a MOV %RCX,0x88(%RSP) |
0x470b22 MOV %R11,0xb0(%RSP) |
0x470b2a MOV %R10,0xb8(%RSP) |
0x470b32 VMOVSD %XMM1,0xc0(%RSP) |
0x470b3b CALL 4110a0 <memset@plt> |
0x470b40 VMOVSD 0xc0(%RSP),%XMM1 |
0x470b49 MOV 0xb8(%RSP),%R10 |
0x470b51 MOV 0xb0(%RSP),%R11 |
0x470b59 MOV 0x88(%RSP),%RCX |
0x470b61 TEST %RCX,%RCX |
0x470b64 JLE 46fecf |
0x470b6a LEA (,%RCX,8),%RDX |
0x470b72 MOV $0xff,%ESI |
0x470b77 MOV %RBX,%RDI |
0x470b7a MOV %R11,0xb0(%RSP) |
0x470b82 MOV %R10,0xb8(%RSP) |
0x470b8a VMOVSD %XMM1,0xc0(%RSP) |
0x470b93 CALL 4110a0 <memset@plt> |
0x470b98 VMOVSD 0xc0(%RSP),%XMM1 |
0x470ba1 MOV 0xb8(%RSP),%R10 |
0x470ba9 MOV 0xb0(%RSP),%R11 |
0x470bb1 JMP 46fecf |
0x470bb6 MOV %RCX,%RDI |
0x470bb9 MOV $0x8,%ESI |
0x470bbe MOV %R11,0x78(%RSP) |
0x470bc3 MOV %R10,0x88(%RSP) |
0x470bcb MOV %RDX,0xb0(%RSP) |
0x470bd3 MOV %RCX,0xc0(%RSP) |
0x470bdb VMOVSD %XMM1,0xb8(%RSP) |
0x470be4 CALL 5959c0 <hypre_CAlloc> |
0x470be9 MOV 0xb0(%RSP),%RDX |
0x470bf1 MOV 0xc0(%RSP),%RCX |
0x470bf9 VMOVSD 0xb8(%RSP),%XMM1 |
0x470c02 MOV 0x88(%RSP),%R10 |
0x470c0a MOV %RAX,%RBX |
0x470c0d TEST %RDX,%RDX |
0x470c10 MOV 0x78(%RSP),%R11 |
0x470c15 JG 470b0e |
0x470c1b JMP 470b61 |
0x470c20 MOV %R12,%RDI |
0x470c23 MOV $0x8,%ESI |
0x470c28 MOV %R11,0x88(%RSP) |
0x470c30 MOV %R10,0xb0(%RSP) |
0x470c38 MOV %R12,0xc0(%RSP) |
0x470c40 XOR %R12D,%R12D |
0x470c43 VMOVSD %XMM1,0xb8(%RSP) |
0x470c4c CALL 5959c0 <hypre_CAlloc> |
0x470c51 MOV 0xc0(%RSP),%RCX |
0x470c59 VMOVSD 0xb8(%RSP),%XMM1 |
0x470c62 MOV 0xb0(%RSP),%R10 |
0x470c6a MOV 0x88(%RSP),%R11 |
0x470c72 MOV %RAX,%RBX |
0x470c75 JMP 470b61 |
0x470c7a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470a9e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470c20 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989f0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989e0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47084e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x12edc7(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 595a80 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 470bb6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 470b0e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 470b61 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 470b61 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1575-1663 |
Module | exec |
nb instructions | 202 |
nb uops | 215 |
loop length | 1122 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 32 |
micro-operation queue | 35.83 cycles |
front end | 35.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.40 | 6.40 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
cycles | 6.40 | 7.60 | 23.00 | 23.00 | 33.00 | 6.40 | 6.40 | 33.00 | 33.00 | 33.00 | 6.40 | 23.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 34.11-34.15 |
Stall cycles | 0.00 |
Front-end | 35.83 |
Dispatch | 33.00 |
DIV/SQRT | 10.00 |
Overall L1 | 35.83 |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 4% |
all | 7% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 9% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 10% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 11% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x100,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xf8(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf0(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x50(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x20(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RBX,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470a9e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xd4e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
TEST %R12,%R12 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 470c20 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989f0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989e0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x8(%R8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
IMUL %RAX,%R11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R11,1),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47084e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xafe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x80(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x12edc7(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%RDI,8),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R9,%R8,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 595a80 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R12,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x78(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JNE 470bb6 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe66> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RCX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
LEA (,%RCX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xc0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46fecf <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x17f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xb0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
TEST %RDX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
MOV 0x78(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JG 470b0e <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xdbe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 470b61 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %R12,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
XOR %R12D,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM1,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVSD 0xb8(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x88(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 470b61 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xe11> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.9– | 0.5 | 0.06 |
▼Loop 660 - par_multi_interp.c:1605-1660 - exec– | 0.09 | 0.01 |
○Loop 667 - par_multi_interp.c:1618-1628 - exec | 0.41 | 0.04 |
○Loop 668 - par_multi_interp.c:1618-1628 - exec | 0 | 0 |
○Loop 664 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 669 - par_multi_interp.c:1612-1615 - exec | 0 | 0 |
○Loop 666 - par_multi_interp.c:1633-1636 - exec | 0 | 0 |
○Loop 661 - par_multi_interp.c:1659-1660 - exec | 0 | 0 |
○Loop 665 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 663 - par_multi_interp.c:1639-1652 - exec | 0 | 0 |
○Loop 662 - par_multi_interp.c:1657-1658 - exec | 0 | 0 |