Loop Id: 3094 | Module: exec | Source: csr_matvec.c:310-312 | Coverage: 0.1% |
---|
Loop Id: 3094 | Module: exec | Source: csr_matvec.c:310-312 | Coverage: 0.1% |
---|
0x58659f VMOVDQU (%RSI,%RAX,1),%YMM6 [4] |
0x5865a4 KMOVB %K0,%K4 |
0x5865a8 VMOVDQU 0x20(%RSI,%RAX,1),%YMM5 [4] |
0x5865ae KMOVB %K0,%K2 |
0x5865b2 KMOVB %K0,%K1 |
0x5865b6 KMOVB %K0,%K5 |
0x5865ba VMOVDQU 0x40(%RSI,%RAX,1),%YMM10 [4] |
0x5865c0 VMOVDQU 0x60(%RSI,%RAX,1),%YMM7 [4] |
0x5865c6 KMOVB %K0,%K6 |
0x5865ca KMOVB %K0,%K3 |
0x5865ce KMOVB %K0,%K7 |
0x5865d2 VGATHERQPD (%RBX,%YMM6,8),%YMM3{%K4} [3] |
0x5865d9 VGATHERQPD (%RBX,%YMM5,8),%YMM4{%K2} [1] |
0x5865e0 VMOVDQU 0x80(%RSI,%RAX,1),%YMM8 [4] |
0x5865e9 VMOVDQU 0xa0(%RSI,%RAX,1),%YMM0 [4] |
0x5865f2 KMOVB %K0,%K4 |
0x5865f6 VFNMADD231PD (%R10,%RAX,1),%YMM3,%YMM1 [10] |
0x5865fc VGATHERQPD (%RBX,%YMM10,8),%YMM9{%K1} [9] |
0x586603 VMOVDQU 0xc0(%RSI,%RAX,1),%YMM12 [4] |
0x58660c VGATHERQPD (%RBX,%YMM8,8),%YMM14{%K6} [7] |
0x586613 VGATHERQPD (%RBX,%YMM0,8),%YMM11{%K3} [6] |
0x58661a VMOVDQU 0xe0(%RSI,%RAX,1),%YMM2 [4] |
0x586623 VGATHERQPD (%RBX,%YMM12,8),%YMM15{%K7} [5] |
0x58662a VFNMADD231PD 0x20(%R10,%RAX,1),%YMM4,%YMM1 [10] |
0x586631 VFNMADD132PD 0x40(%R10,%RAX,1),%YMM1,%YMM9 [10] |
0x586638 VGATHERQPD (%RBX,%YMM7,8),%YMM1{%K5} [8] |
0x58663f VFNMADD132PD 0x60(%R10,%RAX,1),%YMM9,%YMM1 [10] |
0x586646 VFNMADD132PD 0x80(%R10,%RAX,1),%YMM1,%YMM14 [10] |
0x586650 VGATHERQPD (%RBX,%YMM2,8),%YMM1{%K4} [2] |
0x586657 VFNMADD132PD 0xa0(%R10,%RAX,1),%YMM14,%YMM11 [10] |
0x586661 VFNMADD132PD 0xc0(%R10,%RAX,1),%YMM11,%YMM15 [10] |
0x58666b VFNMADD132PD 0xe0(%R10,%RAX,1),%YMM15,%YMM1 [10] |
0x586675 ADD $0x100,%RAX |
0x58667b CMP %R11,%RAX |
0x58667e JNE 58659f |
/home/eoseret/qaas_runs_CPU_9468/171-112-7443/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 310 - 312 |
-------------------------------------------------------------------------------- |
310: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
311: { |
312: tempx -= A_data[jj] * x_data[A_j[jj]]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 4.63 |
Bottlenecks | |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source | csr_matvec.c:310-312 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 74.00 |
CQA cycles if no scalar integer | 32.00 - 74.00 |
CQA cycles if FP arith vectorized | 25.14 - 58.14 |
CQA cycles if fully vectorized | 16.00 - 37.00 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 10.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 74 |
FE+BE cycles (UFS) | 32.20 - 192.15 |
Stall cycles (UFS) | 21.77 - 181.72 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.86 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.38 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 8.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 4.63 |
Bottlenecks | |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source | csr_matvec.c:310-312 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 74.00 |
CQA cycles if no scalar integer | 32.00 - 74.00 |
CQA cycles if FP arith vectorized | 25.14 - 58.14 |
CQA cycles if fully vectorized | 16.00 - 37.00 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 16.00 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 10.50 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 74 |
FE+BE cycles (UFS) | 32.20 - 192.15 |
Stall cycles (UFS) | 21.77 - 181.72 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.86 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 10.38 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 8.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Path / |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source file and lines | csr_matvec.c:310-312 |
Module | exec |
nb instructions | 35 |
nb uops | 66 |
loop length | 229 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 15 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-74.00 |
FE+BE cycles | 32.20-192.15 |
Stall cycles | 21.77-181.72 |
RS full (events) | 20.31-98.77 |
LB full (events) | 10.70-109.42 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-74.00 |
Overall L1 | 32.00-74.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x20(%RSI,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x40(%RSI,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VGATHERQPD (%RBX,%YMM6,8),%YMM3{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%RBX,%YMM5,8),%YMM4{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0xa0(%RSI,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD231PD (%R10,%RAX,1),%YMM3,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM10,8),%YMM9{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xc0(%RSI,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%RBX,%YMM8,8),%YMM14{%K6} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%RBX,%YMM0,8),%YMM11{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%RBX,%YMM12,8),%YMM15{%K7} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD231PD 0x20(%R10,%RAX,1),%YMM4,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x40(%R10,%RAX,1),%YMM1,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM7,8),%YMM1{%K5} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x60(%R10,%RAX,1),%YMM9,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x80(%R10,%RAX,1),%YMM1,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM2,8),%YMM1{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xa0(%R10,%RAX,1),%YMM14,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xc0(%R10,%RAX,1),%YMM11,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xe0(%R10,%RAX,1),%YMM15,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 58659f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x186f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
Source file and lines | csr_matvec.c:310-312 |
Module | exec |
nb instructions | 35 |
nb uops | 66 |
loop length | 229 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 15 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 16.00 | 13.50 | 16.00 | 16.00 | 0.00 | 10.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-74.00 |
FE+BE cycles | 32.20-192.15 |
Stall cycles | 21.77-181.72 |
RS full (events) | 20.31-98.77 |
LB full (events) | 10.70-109.42 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-74.00 |
Overall L1 | 32.00-74.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RAX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x20(%RSI,%RAX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VMOVDQU 0x40(%RSI,%RAX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RAX,1),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VGATHERQPD (%RBX,%YMM6,8),%YMM3{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%RBX,%YMM5,8),%YMM4{%K2} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RAX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0xa0(%RSI,%RAX,1),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VFNMADD231PD (%R10,%RAX,1),%YMM3,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM10,8),%YMM9{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xc0(%RSI,%RAX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%RBX,%YMM8,8),%YMM14{%K6} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VGATHERQPD (%RBX,%YMM0,8),%YMM11{%K3} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RAX,1),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD (%RBX,%YMM12,8),%YMM15{%K7} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD231PD 0x20(%R10,%RAX,1),%YMM4,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x40(%R10,%RAX,1),%YMM1,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM7,8),%YMM1{%K5} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x60(%R10,%RAX,1),%YMM9,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0x80(%R10,%RAX,1),%YMM1,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD (%RBX,%YMM2,8),%YMM1{%K4} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xa0(%R10,%RAX,1),%YMM14,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xc0(%R10,%RAX,1),%YMM11,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VFNMADD132PD 0xe0(%R10,%RAX,1),%YMM15,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R11,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 58659f <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x186f> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |