Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-112-7443/intel/AMG/build/AMG/AMG/utilities/hypre_qsort.c: 31 - 187 |
-------------------------------------------------------------------------------- |
31: temp = v[i]; |
32: v[i] = v[j]; |
33: v[j] = temp; |
[...] |
175: if (left >= right) |
176: return; |
177: hypre_swap( v, left, (left+right)/2); |
178: last = left; |
179: for (i = left+1; i <= right; i++) |
180: if (v[i] < v[left]) |
181: { |
182: hypre_swap(v, ++last, i); |
183: } |
184: hypre_swap(v, left, last); |
185: hypre_qsort0(v, left, last-1); |
186: hypre_qsort0(v, last+1, right); |
187: } |
0x51beb0 CMP %RDX,%RSI |
0x51beb3 JGE 51c0c8 |
0x51beb9 PUSH %RBP |
0x51beba MOV %RSP,%RBP |
0x51bebd PUSH %R15 |
0x51bebf PUSH %R14 |
0x51bec1 PUSH %R12 |
0x51bec3 PUSH %RBX |
0x51bec4 MOV %RDX,%RBX |
0x51bec7 MOV %RDI,%R14 |
0x51beca LEA 0x20(%RDI),%R15 |
0x51bece MOV %RSI,%R12 |
0x51bed1 JMP 51bf2c |
0x51bed3 NOPW %CS:(%RAX,%RAX,1) |
0x51bee2 NOPW %CS:(%RAX,%RAX,1) |
0x51bef1 NOPW %CS:(%RAX,%RAX,1) |
(4470) 0x51bf00 MOV (%R14,%RSI,8),%RAX |
(4470) 0x51bf04 MOV (%R14,%R12,8),%RCX |
(4470) 0x51bf08 MOV %RCX,(%R14,%RSI,8) |
(4470) 0x51bf0c MOV %RAX,(%R14,%R12,8) |
(4470) 0x51bf10 LEA -0x1(%R12),%RDX |
(4470) 0x51bf15 MOV %R14,%RDI |
(4470) 0x51bf18 CALL 51beb0 <hypre_qsort0> |
(4470) 0x51bf1d INC %R12 |
(4470) 0x51bf20 MOV %R12,%RSI |
(4470) 0x51bf23 CMP %RBX,%R12 |
(4470) 0x51bf26 JGE 51c0c0 |
(4470) 0x51bf2c LEA (%RSI,%RBX,1),%RAX |
(4470) 0x51bf30 MOV %RAX,%RCX |
(4470) 0x51bf33 SHR $0x3f,%RCX |
(4470) 0x51bf37 ADD %RAX,%RCX |
(4470) 0x51bf3a MOV (%R14,%RSI,8),%RAX |
(4470) 0x51bf3e AND $-0x2,%RCX |
(4470) 0x51bf42 MOV (%R14,%RCX,4),%RDX |
(4470) 0x51bf46 MOV %RDX,(%R14,%RSI,8) |
(4470) 0x51bf4a MOV %RAX,(%R14,%RCX,4) |
(4470) 0x51bf4e LEA 0x1(%RSI),%RAX |
(4470) 0x51bf52 CMP %RAX,%RBX |
(4470) 0x51bf55 CMOVG %RBX,%RAX |
(4470) 0x51bf59 MOV %RAX,%RCX |
(4470) 0x51bf5c SUB %RSI,%RCX |
(4470) 0x51bf5f CMP $0x4,%RCX |
(4470) 0x51bf63 JAE 51bfc0 |
(4470) 0x51bf65 MOV %RCX,%RDX |
(4470) 0x51bf68 AND $-0x4,%RDX |
(4470) 0x51bf6c CMP %RCX,%RDX |
(4470) 0x51bf6f JAE 51bf00 |
(4470) 0x51bf71 ADD %RSI,%RDX |
(4470) 0x51bf74 JMP 51bf8c |
0x51bf76 NOPW %CS:(%RAX,%RAX,1) |
(4471) 0x51bf80 INC %RDX |
(4471) 0x51bf83 CMP %RDX,%RAX |
(4471) 0x51bf86 JE 51bf00 |
(4471) 0x51bf8c MOV 0x8(%R14,%RDX,8),%RCX |
(4471) 0x51bf91 CMP (%R14,%RSI,8),%RCX |
(4471) 0x51bf95 JGE 51bf80 |
(4471) 0x51bf97 MOV 0x8(%R14,%R12,8),%RDI |
(4471) 0x51bf9c MOV %RCX,0x8(%R14,%R12,8) |
(4471) 0x51bfa1 INC %R12 |
(4471) 0x51bfa4 MOV %RDI,0x8(%R14,%RDX,8) |
(4471) 0x51bfa9 JMP 51bf80 |
0x51bfab NOPW %CS:(%RAX,%RAX,1) |
0x51bfba NOPW (%RAX,%RAX,1) |
(4470) 0x51bfc0 MOV %RCX,%RDX |
(4470) 0x51bfc3 SHR $0x2,%RDX |
(4470) 0x51bfc7 LEA (%R15,%RSI,8),%RDI |
(4470) 0x51bfcb MOV %RSI,%R12 |
(4470) 0x51bfce JMP 51c00d |
0x51bfd0 NOPW %CS:(%RAX,%RAX,1) |
0x51bfdf NOPW %CS:(%RAX,%RAX,1) |
0x51bfee NOPW %CS:(%RAX,%RAX,1) |
0x51bffd NOPL (%RAX) |
(4472) 0x51c000 ADD $0x20,%RDI |
(4472) 0x51c004 DEC %RDX |
(4472) 0x51c007 JE 51bf65 |
(4472) 0x51c00d MOV -0x18(%RDI),%R9 |
(4472) 0x51c011 MOV (%R14,%RSI,8),%R8 |
(4472) 0x51c015 CMP %R8,%R9 |
(4472) 0x51c018 JL 51c040 |
(4472) 0x51c01a MOV -0x10(%RDI),%R9 |
(4472) 0x51c01e CMP %R8,%R9 |
(4472) 0x51c021 JL 51c05e |
(4472) 0x51c023 MOV -0x8(%RDI),%R9 |
(4472) 0x51c027 CMP %R8,%R9 |
(4472) 0x51c02a JL 51c07c |
(4472) 0x51c02c MOV (%RDI),%R9 |
(4472) 0x51c02f CMP %R8,%R9 |
(4472) 0x51c032 JGE 51c000 |
(4472) 0x51c034 JMP 51c09d |
0x51c036 NOPW %CS:(%RAX,%RAX,1) |
(4472) 0x51c040 MOV 0x8(%R14,%R12,8),%R8 |
(4472) 0x51c045 MOV %R9,0x8(%R14,%R12,8) |
(4472) 0x51c04a INC %R12 |
(4472) 0x51c04d MOV %R8,-0x18(%RDI) |
(4472) 0x51c051 MOV (%R14,%RSI,8),%R8 |
(4472) 0x51c055 MOV -0x10(%RDI),%R9 |
(4472) 0x51c059 CMP %R8,%R9 |
(4472) 0x51c05c JGE 51c023 |
(4472) 0x51c05e MOV 0x8(%R14,%R12,8),%R8 |
(4472) 0x51c063 MOV %R9,0x8(%R14,%R12,8) |
(4472) 0x51c068 INC %R12 |
(4472) 0x51c06b MOV %R8,-0x10(%RDI) |
(4472) 0x51c06f MOV (%R14,%RSI,8),%R8 |
(4472) 0x51c073 MOV -0x8(%RDI),%R9 |
(4472) 0x51c077 CMP %R8,%R9 |
(4472) 0x51c07a JGE 51c02c |
(4472) 0x51c07c MOV 0x8(%R14,%R12,8),%R8 |
(4472) 0x51c081 MOV %R9,0x8(%R14,%R12,8) |
(4472) 0x51c086 INC %R12 |
(4472) 0x51c089 MOV %R8,-0x8(%RDI) |
(4472) 0x51c08d MOV (%R14,%RSI,8),%R8 |
(4472) 0x51c091 MOV (%RDI),%R9 |
(4472) 0x51c094 CMP %R8,%R9 |
(4472) 0x51c097 JGE 51c000 |
(4472) 0x51c09d MOV 0x8(%R14,%R12,8),%R8 |
(4472) 0x51c0a2 MOV %R9,0x8(%R14,%R12,8) |
(4472) 0x51c0a7 INC %R12 |
(4472) 0x51c0aa MOV %R8,(%RDI) |
(4472) 0x51c0ad JMP 51c000 |
0x51c0b2 NOPW %CS:(%RAX,%RAX,1) |
0x51c0c0 POP %RBX |
0x51c0c1 POP %R12 |
0x51c0c3 POP %R14 |
0x51c0c5 POP %R15 |
0x51c0c7 POP %RBP |
0x51c0c8 RET |
0x51c0c9 NOPL (%RAX) |
Path / |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 32 |
nb uops | 32 |
loop length | 199 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 5.33 cycles |
front end | 5.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.43-5.45 |
Stall cycles | 0.00 |
Front-end | 5.33 |
Dispatch | 2.50 |
Overall L1 | 5.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 51c0c8 <hypre_qsort0+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 51bf2c <hypre_qsort0+0x7c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 32 |
nb uops | 32 |
loop length | 199 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 5.33 cycles |
front end | 5.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 5.43-5.45 |
Stall cycles | 0.00 |
Front-end | 5.33 |
Dispatch | 2.50 |
Overall L1 | 5.33 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 51c0c8 <hypre_qsort0+0x218> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 51bf2c <hypre_qsort0+0x7c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort0– | 0.01 | 0 |
▼Loop 4470 - hypre_qsort.c:31-186 - exec– | 0 | 0.01 |
○Loop 4472 - hypre_qsort.c:31-182 - exec | 0.01 | 0.04 |
○Loop 4471 - hypre_qsort.c:31-182 - exec | 0 | 0 |