Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 2.49% |
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Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 2.49% |
---|
/home/eoseret/qaas_runs_CPU_9468/171-112-7443/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1746: tmp_marker = NULL; |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
1755: tmp_array_offd = NULL; |
1756: if (new_num_cols_offd > n_coarse_offd) |
1757: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1758: else |
1759: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);} |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x46e650 PUSH %RBP |
0x46e651 MOV %RSP,%RBP |
0x46e654 PUSH %R15 |
0x46e656 PUSH %R14 |
0x46e658 PUSH %R13 |
0x46e65a PUSH %R12 |
0x46e65c PUSH %RBX |
0x46e65d AND $-0x20,%RSP |
0x46e661 SUB $0x160,%RSP |
0x46e668 MOV 0x148(%RDI),%RAX |
0x46e66f MOV 0x138(%RDI),%RDX |
0x46e676 MOV 0x130(%RDI),%RCX |
0x46e67d MOV 0x128(%RDI),%RBX |
0x46e684 MOV 0x108(%RDI),%R9 |
0x46e68b MOV 0x100(%RDI),%R10 |
0x46e692 MOV %RAX,0x148(%RSP) |
0x46e69a MOV 0xf8(%RDI),%R11 |
0x46e6a1 MOV 0xf0(%RDI),%R12 |
0x46e6a8 MOV %RDX,0x88(%RSP) |
0x46e6b0 MOV 0xe8(%RDI),%R13 |
0x46e6b7 MOV 0xe0(%RDI),%R14 |
0x46e6be MOV %RCX,0x138(%RSP) |
0x46e6c6 MOV 0x110(%RDI),%RSI |
0x46e6cd MOV 0x140(%RDI),%R8 |
0x46e6d4 MOV %RBX,0x130(%RSP) |
0x46e6dc MOV %R9,0xe8(%RSP) |
0x46e6e4 MOV 0x120(%RDI),%RDX |
0x46e6eb MOV %R10,0x100(%RSP) |
0x46e6f3 MOV 0x118(%RDI),%RCX |
0x46e6fa MOV %R11,0x18(%RSP) |
0x46e6ff MOV %R12,0x8(%RSP) |
0x46e704 MOV %R13,0x48(%RSP) |
0x46e709 MOV %R14,0x40(%RSP) |
0x46e70e MOV %RSI,0x158(%RSP) |
0x46e716 MOV 0xd8(%RDI),%R15 |
0x46e71d MOV 0xd0(%RDI),%RAX |
0x46e724 MOV 0xc8(%RDI),%RBX |
0x46e72b MOV 0xc0(%RDI),%R9 |
0x46e732 MOV 0xb8(%RDI),%R10 |
0x46e739 MOV %R15,0x80(%RSP) |
0x46e741 MOV 0x68(%RDI),%R15 |
0x46e745 MOV 0xb0(%RDI),%R11 |
0x46e74c MOV %RAX,0x78(%RSP) |
0x46e751 MOV 0xa8(%RDI),%R12 |
0x46e758 MOV 0x98(%RDI),%R13 |
0x46e75f MOV %RBX,0xf8(%RSP) |
0x46e767 MOV 0x80(%RDI),%R14 |
0x46e76e MOV 0x60(%RDI),%RAX |
0x46e772 MOV %R9,0xb0(%RSP) |
0x46e77a MOV 0x58(%RDI),%RBX |
0x46e77e MOV 0x50(%RDI),%R9 |
0x46e782 MOV %R15,0x128(%RSP) |
0x46e78a MOV 0x48(%RDI),%R15 |
0x46e78e MOV %R10,0xf0(%RSP) |
0x46e796 MOV %R11,0x38(%RSP) |
0x46e79b MOV 0xa0(%RDI),%R10 |
0x46e7a2 MOV %R12,0x10(%RSP) |
0x46e7a7 MOV 0x90(%RDI),%R11 |
0x46e7ae MOV %R13,0xd8(%RSP) |
0x46e7b6 MOV 0x78(%RDI),%R12 |
0x46e7ba MOV %R14,0xd0(%RSP) |
0x46e7c2 MOV 0x88(%RDI),%R13 |
0x46e7c9 MOV %RAX,0x70(%RSP) |
0x46e7ce MOV 0x70(%RDI),%R14 |
0x46e7d2 MOV %RBX,0x120(%RSP) |
0x46e7da MOV %R9,0x68(%RSP) |
0x46e7df MOV %R15,0x30(%RSP) |
0x46e7e4 MOV 0x40(%RDI),%RAX |
0x46e7e8 MOV 0x38(%RDI),%RBX |
0x46e7ec MOV 0x30(%RDI),%R9 |
0x46e7f0 MOV 0x28(%RDI),%R15 |
0x46e7f4 MOV %RAX,0x60(%RSP) |
0x46e7f9 MOV %RBX,0x28(%RSP) |
0x46e7fe MOV 0x20(%RDI),%RAX |
0x46e802 MOV 0x18(%RDI),%RBX |
0x46e806 MOV %R9,0x20(%RSP) |
0x46e80b MOV %R15,0x58(%RSP) |
0x46e810 MOV 0x10(%RDI),%R9 |
0x46e814 MOV 0x8(%RDI),%R15 |
0x46e818 MOV (%RDI),%RDI |
0x46e81b MOV %RAX,0xc8(%RSP) |
0x46e823 MOV %RBX,0xa8(%RSP) |
0x46e82b MOV %R9,0x108(%RSP) |
0x46e833 MOV %R15,0x140(%RSP) |
0x46e83b MOV %RDI,0x110(%RSP) |
0x46e843 TEST %RSI,%RSI |
0x46e846 JNE 46fcce |
0x46e84c MOVQ $0,0x150(%RSP) |
0x46e858 TEST %R14,%R14 |
0x46e85b JNE 46fc52 |
0x46e861 MOVQ $0,0x118(%RSP) |
0x46e86d TEST %RCX,%RCX |
0x46e870 JNE 46fbeb |
0x46e876 XOR %R15D,%R15D |
0x46e879 CMP %RDX,%R8 |
0x46e87c JLE 46fbc5 |
0x46e882 MOV %R11,0xb8(%RSP) |
0x46e88a MOV $0x8,%ESI |
0x46e88f MOV %R8,%RDI |
0x46e892 MOV %R10,0xc0(%RSP) |
0x46e89a VMOVSD %XMM1,0xe0(%RSP) |
0x46e8a3 CALL 5959c0 <hypre_CAlloc> |
0x46e8a8 CMPQ $0,0x158(%RSP) |
0x46e8b1 VMOVSD 0xe0(%RSP),%XMM1 |
0x46e8ba MOV %RAX,%RBX |
0x46e8bd MOV 0xc0(%RSP),%RSI |
0x46e8c5 MOV 0xb8(%RSP),%RAX |
0x46e8cd JLE 46e91f |
0x46e8cf MOV 0x158(%RSP),%RDX |
0x46e8d7 MOV 0x150(%RSP),%RDI |
0x46e8df MOV %RSI,0xc0(%RSP) |
0x46e8e7 MOV $0xff,%ESI |
0x46e8ec VMOVSD %XMM1,0xe0(%RSP) |
0x46e8f5 SAL $0x3,%RDX |
0x46e8f9 MOV %RAX,0xb8(%RSP) |
0x46e901 CALL 4110a0 <memset@plt> |
0x46e906 VMOVSD 0xe0(%RSP),%XMM1 |
0x46e90f MOV 0xc0(%RSP),%RSI |
0x46e917 MOV 0xb8(%RSP),%RAX |
0x46e91f TEST %R14,%R14 |
0x46e922 JLE 46e970 |
0x46e924 MOV 0x118(%RSP),%RDI |
0x46e92c MOV %RSI,0xe0(%RSP) |
0x46e934 LEA (,%R14,8),%RDX |
0x46e93c MOV $0xff,%ESI |
0x46e941 VMOVSD %XMM1,0x158(%RSP) |
0x46e94a MOV %RAX,0xc0(%RSP) |
0x46e952 CALL 4110a0 <memset@plt> |
0x46e957 VMOVSD 0x158(%RSP),%XMM1 |
0x46e960 MOV 0xe0(%RSP),%RSI |
0x46e968 MOV 0xc0(%RSP),%RAX |
0x46e970 MOV %RSI,0xc0(%RSP) |
0x46e978 VMOVSD %XMM1,0x158(%RSP) |
0x46e981 MOV %RAX,0xb8(%RSP) |
0x46e989 CALL 5989f0 <hypre_GetThreadNum> |
0x46e98e MOV %RAX,%R14 |
0x46e991 CALL 5989e0 <hypre_NumActiveThreads> |
0x46e996 MOV 0xe8(%RSP),%R8 |
0x46e99e MOV 0xf8(%RSP),%RDX |
0x46e9a6 MOV %R14,%R10 |
0x46e9a9 MOV %RAX,%R9 |
0x46e9ac MOV 0x148(%RSP),%RAX |
0x46e9b4 MOV 0x148(%RSP),%R11 |
0x46e9bc MOV (%RDX,%R8,8),%RCX |
0x46e9c0 LEA (,%R8,8),%RDI |
0x46e9c8 VMOVSD 0x158(%RSP),%XMM12 |
0x46e9d1 CQTO |
0x46e9d3 MOV %RDI,0xe0(%RSP) |
0x46e9db IDIV %R9 |
0x46e9de ADD %RCX,%R11 |
0x46e9e1 DEC %R9 |
0x46e9e4 MOV %R11,%R8 |
0x46e9e7 MOV 0xb8(%RSP),%R11 |
0x46e9ef IMUL %RAX,%R10 |
0x46e9f3 ADD %R10,%RAX |
0x46e9f6 LEA (%RCX,%R10,1),%RSI |
0x46e9fa MOV 0xc0(%RSP),%R10 |
0x46ea02 ADD %RCX,%RAX |
0x46ea05 CMP %R9,%R14 |
0x46ea08 CMOVNE %RAX,%R8 |
0x46ea0c CMP %RSI,%R8 |
0x46ea0f JLE 46f85e |
0x46ea15 MOV 0xb0(%RSP),%R14 |
0x46ea1d VMOVQ 0x13031b(%RIP),%XMM4 |
0x46ea25 VXORPD %XMM3,%XMM3,%XMM3 |
0x46ea29 LEA (%R14,%R8,8),%RDI |
0x46ea2d LEA (%R14,%RSI,8),%R9 |
0x46ea31 MOV 0xe8(%RSP),%R14 |
0x46ea39 MOV %RDI,0x50(%RSP) |
0x46ea3e MOV %R9,0xf8(%RSP) |
0x46ea46 MOV %R15,%R9 |
0x46ea49 MOV 0xa8(%RSP),%R15 |
0x46ea51 DEC %R14 |
0x46ea54 NOPL (%RAX) |
(648) 0x46ea58 MOV 0xf8(%RSP),%RCX |
(648) 0x46ea60 MOV 0xd0(%RSP),%R8 |
(648) 0x46ea68 MOV 0x78(%RSP),%RDX |
(648) 0x46ea6d MOV (%RCX),%RDI |
(648) 0x46ea70 LEA (,%RDI,8),%RAX |
(648) 0x46ea78 MOV (%RDX,%RDI,8),%RDX |
(648) 0x46ea7c LEA 0x8(%RAX),%RCX |
(648) 0x46ea80 MOV %RAX,0x148(%RSP) |
(648) 0x46ea88 ADD %R8,%RAX |
(648) 0x46ea8b LEA (%R8,%RCX,1),%RSI |
(648) 0x46ea8f MOV %RAX,0xb8(%RSP) |
(648) 0x46ea97 MOV (%RAX),%RAX |
(648) 0x46ea9a MOV (%RSI),%R8 |
(648) 0x46ea9d MOV %RSI,0xc0(%RSP) |
(648) 0x46eaa5 ADD %RDX,%R8 |
(648) 0x46eaa8 SUB %RAX,%R8 |
(648) 0x46eaab CMP %R8,%RDX |
(648) 0x46eaae JGE 46ecb3 |
(648) 0x46eab4 MOV %RAX,%RSI |
(648) 0x46eab7 SUB %RDX,%RSI |
(648) 0x46eaba SUB %RAX,%RDX |
(648) 0x46eabd MOV %RDX,0x158(%RSP) |
(648) 0x46eac5 ADD %R8,%RSI |
(648) 0x46eac8 MOV 0xe0(%RSP),%RDX |
(648) 0x46ead0 MOV 0x40(%RSP),%R8 |
(648) 0x46ead5 MOV (%R8,%RDX,1),%R8 |
(648) 0x46ead9 MOV 0x158(%RSP),%RDX |
(648) 0x46eae1 LEA (%R8,%RDX,8),%RDX |
(648) 0x46eae5 MOV %RSI,%R8 |
(648) 0x46eae8 SUB %RAX,%R8 |
(648) 0x46eaeb AND $0x7,%R8D |
(648) 0x46eaef JE 46ebd2 |
(648) 0x46eaf5 CMP $0x1,%R8 |
(648) 0x46eaf9 JE 46ebb1 |
(648) 0x46eaff CMP $0x2,%R8 |
(648) 0x46eb03 JE 46eb99 |
(648) 0x46eb09 CMP $0x3,%R8 |
(648) 0x46eb0d JE 46eb81 |
(648) 0x46eb0f CMP $0x4,%R8 |
(648) 0x46eb13 JE 46eb69 |
(648) 0x46eb15 CMP $0x5,%R8 |
(648) 0x46eb19 JE 46eb51 |
(648) 0x46eb1b CMP $0x6,%R8 |
(648) 0x46eb1f JE 46eb39 |
(648) 0x46eb21 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb25 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb29 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb31 INC %RAX |
(648) 0x46eb34 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb39 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb3d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb41 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb49 INC %RAX |
(648) 0x46eb4c MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb51 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb55 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb59 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb61 INC %RAX |
(648) 0x46eb64 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb69 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb6d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb71 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb79 INC %RAX |
(648) 0x46eb7c MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb81 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb85 MOV %RAX,(%R9,%R8,8) |
(648) 0x46eb89 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eb91 INC %RAX |
(648) 0x46eb94 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46eb99 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46eb9d MOV %RAX,(%R9,%R8,8) |
(648) 0x46eba1 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46eba9 INC %RAX |
(648) 0x46ebac MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46ebb1 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ebb5 MOV %RAX,(%R9,%R8,8) |
(648) 0x46ebb9 MOVQ $0,(%R12,%RAX,8) |
(648) 0x46ebc1 INC %RAX |
(648) 0x46ebc4 MOV %R8,-0x8(%R13,%RAX,8) |
(648) 0x46ebc9 CMP %RSI,%RAX |
(648) 0x46ebcc JE 46ecb3 |
(648) 0x46ebd2 MOV %RBX,0x158(%RSP) |
(659) 0x46ebda MOV (%RDX,%RAX,8),%RBX |
(659) 0x46ebde LEA 0x1(%RAX),%R8 |
(659) 0x46ebe2 MOV %RAX,(%R9,%RBX,8) |
(659) 0x46ebe6 MOVQ $0,(%R12,%RAX,8) |
(659) 0x46ebee MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ebf3 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ebf7 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ebfb MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec03 LEA 0x2(%RAX),%R8 |
(659) 0x46ec07 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec0c MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec10 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec14 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec1c LEA 0x3(%RAX),%R8 |
(659) 0x46ec20 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec25 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec29 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec2d MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec35 LEA 0x4(%RAX),%R8 |
(659) 0x46ec39 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec3e MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec42 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec46 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec4e LEA 0x5(%RAX),%R8 |
(659) 0x46ec52 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec57 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec5b MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec5f MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec67 LEA 0x6(%RAX),%R8 |
(659) 0x46ec6b MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec70 MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec74 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec78 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec80 LEA 0x7(%RAX),%R8 |
(659) 0x46ec84 ADD $0x8,%RAX |
(659) 0x46ec88 MOV %RBX,-0x8(%R13,%R8,8) |
(659) 0x46ec8d MOV (%RDX,%R8,8),%RBX |
(659) 0x46ec91 MOV %R8,(%R9,%RBX,8) |
(659) 0x46ec95 MOVQ $0,(%R12,%R8,8) |
(659) 0x46ec9d MOV %RBX,-0x8(%R13,%RAX,8) |
(659) 0x46eca2 CMP %RSI,%RAX |
(659) 0x46eca5 JNE 46ebda |
(648) 0x46ecab MOV 0x158(%RSP),%RBX |
(648) 0x46ecb3 MOV 0x80(%RSP),%RAX |
(648) 0x46ecbb MOV 0x148(%RSP),%R8 |
(648) 0x46ecc3 MOV (%RAX,%RDI,8),%RDX |
(648) 0x46ecc7 MOV 0xd8(%RSP),%RAX |
(648) 0x46eccf LEA (%RAX,%RCX,1),%RSI |
(648) 0x46ecd3 ADD %R8,%RAX |
(648) 0x46ecd6 MOV (%RSI),%R8 |
(648) 0x46ecd9 MOV %RAX,0xa8(%RSP) |
(648) 0x46ece1 MOV (%RAX),%RAX |
(648) 0x46ece4 MOV %RSI,0xb0(%RSP) |
(648) 0x46ecec ADD %RDX,%R8 |
(648) 0x46ecef SUB %RAX,%R8 |
(648) 0x46ecf2 CMP %R8,%RDX |
(648) 0x46ecf5 JGE 46eefa |
(648) 0x46ecfb MOV %RAX,%RSI |
(648) 0x46ecfe SUB %RDX,%RSI |
(648) 0x46ed01 SUB %RAX,%RDX |
(648) 0x46ed04 MOV %RDX,0x158(%RSP) |
(648) 0x46ed0c ADD %R8,%RSI |
(648) 0x46ed0f MOV 0xe0(%RSP),%RDX |
(648) 0x46ed17 MOV 0x48(%RSP),%R8 |
(648) 0x46ed1c MOV (%R8,%RDX,1),%R8 |
(648) 0x46ed20 MOV 0x158(%RSP),%RDX |
(648) 0x46ed28 LEA (%R8,%RDX,8),%RDX |
(648) 0x46ed2c MOV %RSI,%R8 |
(648) 0x46ed2f SUB %RAX,%R8 |
(648) 0x46ed32 AND $0x7,%R8D |
(648) 0x46ed36 JE 46ee19 |
(648) 0x46ed3c CMP $0x1,%R8 |
(648) 0x46ed40 JE 46edf8 |
(648) 0x46ed46 CMP $0x2,%R8 |
(648) 0x46ed4a JE 46ede0 |
(648) 0x46ed50 CMP $0x3,%R8 |
(648) 0x46ed54 JE 46edc8 |
(648) 0x46ed56 CMP $0x4,%R8 |
(648) 0x46ed5a JE 46edb0 |
(648) 0x46ed5c CMP $0x5,%R8 |
(648) 0x46ed60 JE 46ed98 |
(648) 0x46ed62 CMP $0x6,%R8 |
(648) 0x46ed66 JE 46ed80 |
(648) 0x46ed68 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed6c MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed70 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed78 INC %RAX |
(648) 0x46ed7b MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed80 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed84 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ed88 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ed90 INC %RAX |
(648) 0x46ed93 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ed98 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ed9c MOV %RAX,(%RBX,%R8,8) |
(648) 0x46eda0 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46eda8 INC %RAX |
(648) 0x46edab MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46edb0 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46edb4 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46edb8 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46edc0 INC %RAX |
(648) 0x46edc3 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46edc8 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46edcc MOV %RAX,(%RBX,%R8,8) |
(648) 0x46edd0 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46edd8 INC %RAX |
(648) 0x46eddb MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ede0 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46ede4 MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ede8 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46edf0 INC %RAX |
(648) 0x46edf3 MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46edf8 MOV (%RDX,%RAX,8),%R8 |
(648) 0x46edfc MOV %RAX,(%RBX,%R8,8) |
(648) 0x46ee00 MOVQ $0,(%R11,%RAX,8) |
(648) 0x46ee08 INC %RAX |
(648) 0x46ee0b MOV %R8,-0x8(%R10,%RAX,8) |
(648) 0x46ee10 CMP %RSI,%RAX |
(648) 0x46ee13 JE 46eefa |
(648) 0x46ee19 MOV %R9,0x158(%RSP) |
(658) 0x46ee21 MOV (%RDX,%RAX,8),%R9 |
(658) 0x46ee25 LEA 0x1(%RAX),%R8 |
(658) 0x46ee29 MOV %RAX,(%RBX,%R9,8) |
(658) 0x46ee2d MOVQ $0,(%R11,%RAX,8) |
(658) 0x46ee35 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee3a MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee3e MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee42 MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee4a LEA 0x2(%RAX),%R8 |
(658) 0x46ee4e MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee53 MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee57 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee5b MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee63 LEA 0x3(%RAX),%R8 |
(658) 0x46ee67 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee6c MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee70 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee74 MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee7c LEA 0x4(%RAX),%R8 |
(658) 0x46ee80 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee85 MOV (%RDX,%R8,8),%R9 |
(658) 0x46ee89 MOV %R8,(%RBX,%R9,8) |
(658) 0x46ee8d MOVQ $0,(%R11,%R8,8) |
(658) 0x46ee95 LEA 0x5(%RAX),%R8 |
(658) 0x46ee99 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46ee9e MOV (%RDX,%R8,8),%R9 |
(658) 0x46eea2 MOV %R8,(%RBX,%R9,8) |
(658) 0x46eea6 MOVQ $0,(%R11,%R8,8) |
(658) 0x46eeae LEA 0x6(%RAX),%R8 |
(658) 0x46eeb2 MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46eeb7 MOV (%RDX,%R8,8),%R9 |
(658) 0x46eebb MOV %R8,(%RBX,%R9,8) |
(658) 0x46eebf MOVQ $0,(%R11,%R8,8) |
(658) 0x46eec7 LEA 0x7(%RAX),%R8 |
(658) 0x46eecb ADD $0x8,%RAX |
(658) 0x46eecf MOV %R9,-0x8(%R10,%R8,8) |
(658) 0x46eed4 MOV (%RDX,%R8,8),%R9 |
(658) 0x46eed8 MOV %R8,(%RBX,%R9,8) |
(658) 0x46eedc MOVQ $0,(%R11,%R8,8) |
(658) 0x46eee4 MOV %R9,-0x8(%R10,%RAX,8) |
(658) 0x46eee9 CMP %RSI,%RAX |
(658) 0x46eeec JNE 46ee21 |
(648) 0x46eef2 MOV 0x158(%RSP),%R9 |
(648) 0x46eefa MOV 0x68(%RSP),%RSI |
(648) 0x46eeff LEA (%RSI,%RCX,1),%R8 |
(648) 0x46ef03 MOV (%RSI,%RDI,8),%RAX |
(648) 0x46ef07 MOV (%R8),%RSI |
(648) 0x46ef0a CMP %RSI,%RAX |
(648) 0x46ef0d JGE 46ef4e |
(648) 0x46ef0f MOV %RCX,0x158(%RSP) |
(648) 0x46ef17 NOPW (%RAX,%RAX,1) |
(657) 0x46ef20 MOV 0x120(%RSP),%RCX |
(657) 0x46ef28 MOV (%RCX,%RAX,8),%RDX |
(657) 0x46ef2c MOV 0x130(%RSP),%RCX |
(657) 0x46ef34 CMP (%RCX,%RDX,8),%R14 |
(657) 0x46ef38 JE 46f080 |
(657) 0x46ef3e INC %RAX |
(657) 0x46ef41 CMP %RSI,%RAX |
(657) 0x46ef44 JL 46ef20 |
(648) 0x46ef46 MOV 0x158(%RSP),%RCX |
(648) 0x46ef4e MOV 0x70(%RSP),%R8 |
(648) 0x46ef53 ADD %R8,%RCX |
(648) 0x46ef56 MOV (%R8,%RDI,8),%RAX |
(648) 0x46ef5a MOV (%RCX),%RSI |
(648) 0x46ef5d CMP %RSI,%RAX |
(648) 0x46ef60 JGE 46ef8e |
(648) 0x46ef62 NOPW (%RAX,%RAX,1) |
(656) 0x46ef68 MOV 0x128(%RSP),%RDX |
(656) 0x46ef70 MOV 0x138(%RSP),%R8 |
(656) 0x46ef78 MOV (%RDX,%RAX,8),%RDX |
(656) 0x46ef7c CMP (%R8,%RDX,8),%R14 |
(656) 0x46ef80 JE 46f0a0 |
(656) 0x46ef86 INC %RAX |
(656) 0x46ef89 CMP %RSI,%RAX |
(656) 0x46ef8c JL 46ef68 |
(648) 0x46ef8e MOV 0x58(%RSP),%RCX |
(648) 0x46ef93 MOV 0x148(%RSP),%RDX |
(648) 0x46ef9b MOV (%RCX,%RDI,8),%R8 |
(648) 0x46ef9f MOV 0x8(%RCX,%RDX,1),%RDX |
(648) 0x46efa4 LEA 0x1(%R8),%RAX |
(648) 0x46efa8 CMP %RDX,%RAX |
(648) 0x46efab JGE 46fb8c |
(648) 0x46efb1 MOV 0x20(%RSP),%RCX |
(648) 0x46efb6 SAL $0x3,%RAX |
(648) 0x46efba VXORPD %XMM0,%XMM0,%XMM0 |
(648) 0x46efbe MOV %R15,0xa0(%RSP) |
(648) 0x46efc6 MOV %R8,0x98(%RSP) |
(648) 0x46efce VMOVSD %XMM0,%XMM0,%XMM2 |
(648) 0x46efd2 LEA (%RCX,%RAX,1),%RSI |
(648) 0x46efd6 LEA (%RCX,%RDX,8),%RDX |
(648) 0x46efda MOV %RSI,0xe8(%RSP) |
(648) 0x46efe2 MOV 0xc8(%RSP),%RSI |
(648) 0x46efea MOV %RDX,0x158(%RSP) |
(648) 0x46eff2 ADD %RSI,%RAX |
(648) 0x46eff5 MOV 0xe8(%RSP),%RSI |
(648) 0x46effd MOV %R14,0xe8(%RSP) |
(648) 0x46f005 JMP 46f040 |
0x46f007 NOPW (%RAX,%RAX,1) |
(653) 0x46f010 MOV 0x108(%RSP),%RDX |
(653) 0x46f018 MOV 0x148(%RSP),%R8 |
(653) 0x46f020 MOV (%RDX,%RCX,8),%RCX |
(653) 0x46f024 CMP %RCX,(%RDX,%R8,1) |
(653) 0x46f028 JE 46f073 |
(653) 0x46f02a ADD $0x8,%RSI |
(653) 0x46f02e ADD $0x8,%RAX |
(653) 0x46f032 CMP %RSI,0x158(%RSP) |
(653) 0x46f03a JE 46f3c0 |
(653) 0x46f040 MOV (%RSI),%RCX |
(653) 0x46f043 MOV 0x150(%RSP),%R15 |
(653) 0x46f04b LEA (,%RCX,8),%R8 |
(653) 0x46f053 CMP (%R15,%RCX,8),%RDI |
(653) 0x46f057 JE 46f0c0 |
(653) 0x46f059 MOV 0x110(%RSP),%R14 |
(653) 0x46f061 CMPQ $-0x3,(%R14,%RCX,8) |
(653) 0x46f066 JE 46f02a |
(653) 0x46f068 CMPQ $0x1,0x140(%RSP) |
(653) 0x46f071 JNE 46f010 |
(653) 0x46f073 VADDSD (%RAX),%XMM0,%XMM0 |
(653) 0x46f077 JMP 46f02a |
0x46f079 NOPL (%RAX) |
(657) 0x46f080 MOV 0x150(%RSP),%RSI |
(657) 0x46f088 INC %RAX |
(657) 0x46f08b MOV %RDI,(%RSI,%RDX,8) |
(657) 0x46f08f MOV (%R8),%RSI |
(657) 0x46f092 CMP %RAX,%RSI |
(657) 0x46f095 JG 46ef20 |
(648) 0x46f09b JMP 46ef46 |
(656) 0x46f0a0 MOV 0x118(%RSP),%RSI |
(656) 0x46f0a8 INC %RAX |
(656) 0x46f0ab MOV %RDI,(%RSI,%RDX,8) |
(656) 0x46f0af MOV (%RCX),%RSI |
(656) 0x46f0b2 CMP %RAX,%RSI |
(656) 0x46f0b5 JG 46ef68 |
(648) 0x46f0bb JMP 46ef8e |
(653) 0x46f0c0 MOV 0xd0(%RSP),%R15 |
(653) 0x46f0c8 MOV (%R15,%RCX,8),%RDX |
(653) 0x46f0cc MOV 0x8(%R15,%R8,1),%R15 |
(653) 0x46f0d1 CMP %R15,%RDX |
(653) 0x46f0d4 JGE 46f243 |
(653) 0x46f0da MOV %R15,%R14 |
(653) 0x46f0dd SUB %RDX,%R14 |
(653) 0x46f0e0 AND $0x3,%R14D |
(653) 0x46f0e4 JE 46f187 |
(653) 0x46f0ea CMP $0x1,%R14 |
(653) 0x46f0ee JE 46f150 |
(653) 0x46f0f0 CMP $0x2,%R14 |
(653) 0x46f0f4 JE 46f122 |
(653) 0x46f0f6 VMOVSD (%RAX),%XMM5 |
(653) 0x46f0fa MOV (%R13,%RDX,8),%R14 |
(653) 0x46f0ff VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
(653) 0x46f105 MOV (%R9,%R14,8),%R14 |
(653) 0x46f109 INC %RDX |
(653) 0x46f10c LEA (%R12,%R14,8),%R14 |
(653) 0x46f110 VADDSD (%R14),%XMM6,%XMM7 |
(653) 0x46f115 VADDSD %XMM6,%XMM2,%XMM2 |
(653) 0x46f119 VADDSD %XMM6,%XMM0,%XMM0 |
(653) 0x46f11d VMOVSD %XMM7,(%R14) |
(653) 0x46f122 VMOVSD (%RAX),%XMM8 |
(653) 0x46f126 MOV (%R13,%RDX,8),%R14 |
(653) 0x46f12b VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
(653) 0x46f131 MOV (%R9,%R14,8),%R14 |
(653) 0x46f135 INC %RDX |
(653) 0x46f138 LEA (%R12,%R14,8),%R14 |
(653) 0x46f13c VADDSD (%R14),%XMM9,%XMM10 |
(653) 0x46f141 VADDSD %XMM9,%XMM2,%XMM2 |
(653) 0x46f146 VADDSD %XMM9,%XMM0,%XMM0 |
(653) 0x46f14b VMOVSD %XMM10,(%R14) |
(653) 0x46f150 VMOVSD (%RAX),%XMM11 |
(653) 0x46f154 MOV (%R13,%RDX,8),%R14 |
(653) 0x46f159 VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
(653) 0x46f15f MOV (%R9,%R14,8),%R14 |
(653) 0x46f163 INC %RDX |
(653) 0x46f166 LEA (%R12,%R14,8),%R14 |
(653) 0x46f16a VADDSD (%R14),%XMM12,%XMM13 |
(653) 0x46f16f VADDSD %XMM12,%XMM2,%XMM2 |
(653) 0x46f174 VADDSD %XMM12,%XMM0,%XMM0 |
(653) 0x46f179 VMOVSD %XMM13,(%R14) |
(653) 0x46f17e CMP %R15,%RDX |
(653) 0x46f181 JE 46f243 |
(655) 0x46f187 VMOVSD (%RAX),%XMM14 |
(655) 0x46f18b MOV (%R13,%RDX,8),%R14 |
(655) 0x46f190 VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(655) 0x46f196 MOV (%R9,%R14,8),%R14 |
(655) 0x46f19a LEA (%R12,%R14,8),%R14 |
(655) 0x46f19e VADDSD (%R14),%XMM15,%XMM1 |
(655) 0x46f1a3 VADDSD %XMM15,%XMM2,%XMM6 |
(655) 0x46f1a8 VADDSD %XMM15,%XMM0,%XMM7 |
(655) 0x46f1ad VMOVSD %XMM1,(%R14) |
(655) 0x46f1b2 MOV 0x8(%R13,%RDX,8),%R14 |
(655) 0x46f1b7 VMOVSD (%RAX),%XMM5 |
(655) 0x46f1bb MOV (%R9,%R14,8),%R14 |
(655) 0x46f1bf VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(655) 0x46f1c6 LEA (%R12,%R14,8),%R14 |
(655) 0x46f1ca VADDSD (%R14),%XMM8,%XMM9 |
(655) 0x46f1cf VADDSD %XMM8,%XMM6,%XMM10 |
(655) 0x46f1d4 VADDSD %XMM8,%XMM7,%XMM11 |
(655) 0x46f1d9 VMOVSD %XMM9,(%R14) |
(655) 0x46f1de MOV 0x10(%R13,%RDX,8),%R14 |
(655) 0x46f1e3 VMOVSD (%RAX),%XMM12 |
(655) 0x46f1e7 MOV (%R9,%R14,8),%R14 |
(655) 0x46f1eb VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(655) 0x46f1f2 LEA (%R12,%R14,8),%R14 |
(655) 0x46f1f6 VADDSD (%R14),%XMM13,%XMM2 |
(655) 0x46f1fb VADDSD %XMM13,%XMM10,%XMM14 |
(655) 0x46f200 VADDSD %XMM13,%XMM11,%XMM0 |
(655) 0x46f205 VMOVSD %XMM2,(%R14) |
(655) 0x46f20a MOV 0x18(%R13,%RDX,8),%R14 |
(655) 0x46f20f VMOVSD (%RAX),%XMM15 |
(655) 0x46f213 MOV (%R9,%R14,8),%R14 |
(655) 0x46f217 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(655) 0x46f21e ADD $0x4,%RDX |
(655) 0x46f222 LEA (%R12,%R14,8),%R14 |
(655) 0x46f226 VADDSD (%R14),%XMM12,%XMM1 |
(655) 0x46f22b VADDSD %XMM12,%XMM14,%XMM2 |
(655) 0x46f230 VADDSD %XMM12,%XMM0,%XMM0 |
(655) 0x46f235 VMOVSD %XMM1,(%R14) |
(655) 0x46f23a CMP %R15,%RDX |
(655) 0x46f23d JNE 46f187 |
(653) 0x46f243 MOV 0xd8(%RSP),%R15 |
(653) 0x46f24b MOV (%R15,%RCX,8),%RDX |
(653) 0x46f24f MOV 0x8(%R15,%R8,1),%R8 |
(653) 0x46f254 CMP %R8,%RDX |
(653) 0x46f257 JGE 46f02a |
(653) 0x46f25d MOV %R8,%RCX |
(653) 0x46f260 SUB %RDX,%RCX |
(653) 0x46f263 AND $0x3,%ECX |
(653) 0x46f266 JE 46f300 |
(653) 0x46f26c CMP $0x1,%RCX |
(653) 0x46f270 JE 46f2cc |
(653) 0x46f272 CMP $0x2,%RCX |
(653) 0x46f276 JE 46f2a1 |
(653) 0x46f278 VMOVSD (%RAX),%XMM6 |
(653) 0x46f27c MOV (%R10,%RDX,8),%R14 |
(653) 0x46f280 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
(653) 0x46f286 MOV (%RBX,%R14,8),%R15 |
(653) 0x46f28a INC %RDX |
(653) 0x46f28d LEA (%R11,%R15,8),%RCX |
(653) 0x46f291 VADDSD (%RCX),%XMM7,%XMM5 |
(653) 0x46f295 VADDSD %XMM7,%XMM2,%XMM2 |
(653) 0x46f299 VADDSD %XMM7,%XMM0,%XMM0 |
(653) 0x46f29d VMOVSD %XMM5,(%RCX) |
(653) 0x46f2a1 VMOVSD (%RAX),%XMM8 |
(653) 0x46f2a5 MOV (%R10,%RDX,8),%R14 |
(653) 0x46f2a9 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
(653) 0x46f2af MOV (%RBX,%R14,8),%R15 |
(653) 0x46f2b3 INC %RDX |
(653) 0x46f2b6 LEA (%R11,%R15,8),%RCX |
(653) 0x46f2ba VADDSD (%RCX),%XMM9,%XMM10 |
(653) 0x46f2be VADDSD %XMM9,%XMM2,%XMM2 |
(653) 0x46f2c3 VADDSD %XMM9,%XMM0,%XMM0 |
(653) 0x46f2c8 VMOVSD %XMM10,(%RCX) |
(653) 0x46f2cc VMOVSD (%RAX),%XMM11 |
(653) 0x46f2d0 MOV (%R10,%RDX,8),%R14 |
(653) 0x46f2d4 VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
(653) 0x46f2da MOV (%RBX,%R14,8),%R15 |
(653) 0x46f2de INC %RDX |
(653) 0x46f2e1 LEA (%R11,%R15,8),%RCX |
(653) 0x46f2e5 VADDSD (%RCX),%XMM12,%XMM13 |
(653) 0x46f2e9 VADDSD %XMM12,%XMM2,%XMM2 |
(653) 0x46f2ee VADDSD %XMM12,%XMM0,%XMM0 |
(653) 0x46f2f3 VMOVSD %XMM13,(%RCX) |
(653) 0x46f2f7 CMP %R8,%RDX |
(653) 0x46f2fa JE 46f02a |
(654) 0x46f300 VMOVSD (%RAX),%XMM12 |
(654) 0x46f304 MOV (%R10,%RDX,8),%R14 |
(654) 0x46f308 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(654) 0x46f30e MOV (%RBX,%R14,8),%R15 |
(654) 0x46f312 MOV 0x8(%R10,%RDX,8),%R14 |
(654) 0x46f317 LEA (%R11,%R15,8),%RCX |
(654) 0x46f31b MOV (%RBX,%R14,8),%R15 |
(654) 0x46f31f MOV 0x10(%R10,%RDX,8),%R14 |
(654) 0x46f324 VADDSD (%RCX),%XMM14,%XMM15 |
(654) 0x46f328 VADDSD %XMM14,%XMM2,%XMM2 |
(654) 0x46f32d VADDSD %XMM14,%XMM0,%XMM0 |
(654) 0x46f332 VMOVSD %XMM15,(%RCX) |
(654) 0x46f336 LEA (%R11,%R15,8),%RCX |
(654) 0x46f33a MOV (%RBX,%R14,8),%R15 |
(654) 0x46f33e MOV 0x18(%R10,%RDX,8),%R14 |
(654) 0x46f343 VMOVSD (%RAX),%XMM1 |
(654) 0x46f347 VMULSD 0x8(%R11,%RDX,8),%XMM1,%XMM6 |
(654) 0x46f34e VADDSD (%RCX),%XMM6,%XMM7 |
(654) 0x46f352 VADDSD %XMM6,%XMM2,%XMM8 |
(654) 0x46f356 VADDSD %XMM6,%XMM0,%XMM9 |
(654) 0x46f35a VMOVSD %XMM7,(%RCX) |
(654) 0x46f35e LEA (%R11,%R15,8),%RCX |
(654) 0x46f362 MOV (%RBX,%R14,8),%R15 |
(654) 0x46f366 VMOVSD (%RAX),%XMM5 |
(654) 0x46f36a VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(654) 0x46f371 VADDSD (%RCX),%XMM10,%XMM11 |
(654) 0x46f375 VADDSD %XMM10,%XMM8,%XMM13 |
(654) 0x46f37a VADDSD %XMM10,%XMM9,%XMM14 |
(654) 0x46f37f VMOVSD %XMM11,(%RCX) |
(654) 0x46f383 LEA (%R11,%R15,8),%RCX |
(654) 0x46f387 VMOVSD (%RAX),%XMM12 |
(654) 0x46f38b VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(654) 0x46f392 ADD $0x4,%RDX |
(654) 0x46f396 VADDSD (%RCX),%XMM12,%XMM15 |
(654) 0x46f39a VADDSD %XMM12,%XMM13,%XMM2 |
(654) 0x46f39f VADDSD %XMM12,%XMM14,%XMM0 |
(654) 0x46f3a4 VMOVSD %XMM15,(%RCX) |
(654) 0x46f3a8 CMP %R8,%RDX |
(654) 0x46f3ab JNE 46f300 |
(653) 0x46f3b1 JMP 46f02a |
0x46f3b6 NOPW %CS:(%RAX,%RAX,1) |
(648) 0x46f3c0 MOV 0xa0(%RSP),%R15 |
(648) 0x46f3c8 MOV 0x98(%RSP),%R8 |
(648) 0x46f3d0 MOV 0xe8(%RSP),%R14 |
(648) 0x46f3d8 MOV 0x60(%RSP),%RCX |
(648) 0x46f3dd MOV 0x148(%RSP),%RAX |
(648) 0x46f3e5 MOV (%RCX,%RDI,8),%RDX |
(648) 0x46f3e9 MOV 0x8(%RCX,%RAX,1),%RCX |
(648) 0x46f3ee CMP %RCX,%RDX |
(648) 0x46f3f1 JGE 46f4f3 |
(648) 0x46f3f7 MOV 0x30(%RSP),%RAX |
(648) 0x46f3fc SAL $0x3,%RDX |
(648) 0x46f400 MOV %R10,0xa0(%RSP) |
(648) 0x46f408 MOV %R13,0x98(%RSP) |
(648) 0x46f410 LEA (%RAX,%RDX,1),%RSI |
(648) 0x46f414 MOV %R8,0x90(%RSP) |
(648) 0x46f41c MOV %RSI,0x158(%RSP) |
(648) 0x46f424 MOV 0x28(%RSP),%RSI |
(648) 0x46f429 ADD %RSI,%RDX |
(648) 0x46f42c LEA (%RAX,%RCX,8),%RSI |
(648) 0x46f430 MOV %R14,%RAX |
(648) 0x46f433 MOV 0x38(%RSP),%R14 |
(648) 0x46f438 JMP 46f47c |
0x46f43a NOPW (%RAX,%RAX,1) |
(651) 0x46f440 MOV 0x108(%RSP),%R10 |
(651) 0x46f448 MOV 0x148(%RSP),%R13 |
(651) 0x46f450 MOV 0xf0(%RSP),%RCX |
(651) 0x46f458 MOV (%R10,%R13,1),%R10 |
(651) 0x46f45c CMP %R10,(%RCX,%R8,1) |
(651) 0x46f460 JE 46f4cf |
(651) 0x46f462 ADDQ $0x8,0x158(%RSP) |
(651) 0x46f46b ADD $0x8,%RDX |
(651) 0x46f46f MOV 0x158(%RSP),%RCX |
(651) 0x46f477 CMP %RSI,%RCX |
(651) 0x46f47a JE 46f4d8 |
(651) 0x46f47c MOV 0x158(%RSP),%R13 |
(651) 0x46f484 MOV (%R13),%RCX |
(651) 0x46f488 TEST %R15,%R15 |
(651) 0x46f48b JE 46f499 |
(651) 0x46f48d MOV 0x100(%RSP),%R10 |
(651) 0x46f495 MOV (%R10,%RCX,8),%RCX |
(651) 0x46f499 LEA (,%RCX,8),%R8 |
(651) 0x46f4a1 TEST %RCX,%RCX |
(651) 0x46f4a4 JS 46f4b9 |
(651) 0x46f4a6 MOV 0x118(%RSP),%R13 |
(651) 0x46f4ae CMP (%R13,%RCX,8),%RDI |
(651) 0x46f4b3 JE 46f8a0 |
(651) 0x46f4b9 CMPQ $-0x3,(%R14,%R8,1) |
(651) 0x46f4be JE 46f462 |
(651) 0x46f4c0 CMPQ $0x1,0x140(%RSP) |
(651) 0x46f4c9 JNE 46f440 |
(651) 0x46f4cf VADDSD (%RDX),%XMM0,%XMM0 |
(651) 0x46f4d3 JMP 46f462 |
0x46f4d5 NOPL (%RAX) |
(648) 0x46f4d8 MOV 0xa0(%RSP),%R10 |
(648) 0x46f4e0 MOV 0x98(%RSP),%R13 |
(648) 0x46f4e8 MOV %RAX,%R14 |
(648) 0x46f4eb MOV 0x90(%RSP),%R8 |
(648) 0x46f4f3 MOV 0xc8(%RSP),%RDI |
(648) 0x46f4fb VMULSD (%RDI,%R8,8),%XMM2,%XMM9 |
(648) 0x46f501 VCOMISD %XMM3,%XMM9 |
(648) 0x46f505 JE 46f510 |
(648) 0x46f507 VXORPD %XMM4,%XMM0,%XMM10 |
(648) 0x46f50b VDIVSD %XMM9,%XMM10,%XMM12 |
(648) 0x46f510 MOV 0xb8(%RSP),%R8 |
(648) 0x46f518 MOV 0xc0(%RSP),%RAX |
(648) 0x46f520 MOV (%R8),%RSI |
(648) 0x46f523 MOV (%RAX),%RCX |
(648) 0x46f526 CMP %RCX,%RSI |
(648) 0x46f529 JGE 46f6a6 |
(648) 0x46f52f SUB %RSI,%RCX |
(648) 0x46f532 MOV %RSI,%RDI |
(648) 0x46f535 LEA -0x1(%RCX),%RDX |
(648) 0x46f539 CMP $0x2,%RDX |
(648) 0x46f53d JBE 46fb99 |
(648) 0x46f543 MOV %RCX,%RDX |
(648) 0x46f546 LEA (%R12,%RSI,8),%RAX |
(648) 0x46f54a VBROADCASTSD %XMM12,%YMM5 |
(648) 0x46f54f SHR $0x2,%RDX |
(648) 0x46f553 SAL $0x5,%RDX |
(648) 0x46f557 LEA (%RDX,%RAX,1),%R8 |
(648) 0x46f55b SUB $0x20,%RDX |
(648) 0x46f55f SHR $0x5,%RDX |
(648) 0x46f563 INC %RDX |
(648) 0x46f566 AND $0x7,%EDX |
(648) 0x46f569 JE 46f5f3 |
(648) 0x46f56f CMP $0x1,%RDX |
(648) 0x46f573 JE 46f5e1 |
(648) 0x46f575 CMP $0x2,%RDX |
(648) 0x46f579 JE 46f5d4 |
(648) 0x46f57b CMP $0x3,%RDX |
(648) 0x46f57f JE 46f5c7 |
(648) 0x46f581 CMP $0x4,%RDX |
(648) 0x46f585 JE 46f5ba |
(648) 0x46f587 CMP $0x5,%RDX |
(648) 0x46f58b JE 46f5ad |
(648) 0x46f58d CMP $0x6,%RDX |
(648) 0x46f591 JE 46f5a0 |
(648) 0x46f593 VMULPD (%RAX),%YMM5,%YMM11 |
(648) 0x46f597 ADD $0x20,%RAX |
(648) 0x46f59b VMOVUPD %YMM11,-0x20(%RAX) |
(648) 0x46f5a0 VMULPD (%RAX),%YMM5,%YMM13 |
(648) 0x46f5a4 ADD $0x20,%RAX |
(648) 0x46f5a8 VMOVUPD %YMM13,-0x20(%RAX) |
(648) 0x46f5ad VMULPD (%RAX),%YMM5,%YMM14 |
(648) 0x46f5b1 ADD $0x20,%RAX |
(648) 0x46f5b5 VMOVUPD %YMM14,-0x20(%RAX) |
(648) 0x46f5ba VMULPD (%RAX),%YMM5,%YMM15 |
(648) 0x46f5be ADD $0x20,%RAX |
(648) 0x46f5c2 VMOVUPD %YMM15,-0x20(%RAX) |
(648) 0x46f5c7 VMULPD (%RAX),%YMM5,%YMM1 |
(648) 0x46f5cb ADD $0x20,%RAX |
(648) 0x46f5cf VMOVUPD %YMM1,-0x20(%RAX) |
(648) 0x46f5d4 VMULPD (%RAX),%YMM5,%YMM6 |
(648) 0x46f5d8 ADD $0x20,%RAX |
(648) 0x46f5dc VMOVUPD %YMM6,-0x20(%RAX) |
(648) 0x46f5e1 VMULPD (%RAX),%YMM5,%YMM7 |
(648) 0x46f5e5 ADD $0x20,%RAX |
(648) 0x46f5e9 VMOVUPD %YMM7,-0x20(%RAX) |
(648) 0x46f5ee CMP %R8,%RAX |
(648) 0x46f5f1 JE 46f662 |
(650) 0x46f5f3 VMULPD (%RAX),%YMM5,%YMM2 |
(650) 0x46f5f7 ADD $0x100,%RAX |
(650) 0x46f5fd VMULPD -0xe0(%RAX),%YMM5,%YMM0 |
(650) 0x46f605 VMULPD -0xc0(%RAX),%YMM5,%YMM8 |
(650) 0x46f60d VMULPD -0xa0(%RAX),%YMM5,%YMM9 |
(650) 0x46f615 VMULPD -0x80(%RAX),%YMM5,%YMM10 |
(650) 0x46f61a VMULPD -0x60(%RAX),%YMM5,%YMM11 |
(650) 0x46f61f VMOVUPD %YMM2,-0x100(%RAX) |
(650) 0x46f627 VMULPD -0x40(%RAX),%YMM5,%YMM13 |
(650) 0x46f62c VMOVUPD %YMM0,-0xe0(%RAX) |
(650) 0x46f634 VMULPD -0x20(%RAX),%YMM5,%YMM14 |
(650) 0x46f639 VMOVUPD %YMM8,-0xc0(%RAX) |
(650) 0x46f641 VMOVUPD %YMM9,-0xa0(%RAX) |
(650) 0x46f649 VMOVUPD %YMM10,-0x80(%RAX) |
(650) 0x46f64e VMOVUPD %YMM11,-0x60(%RAX) |
(650) 0x46f653 VMOVUPD %YMM13,-0x40(%RAX) |
(650) 0x46f658 VMOVUPD %YMM14,-0x20(%RAX) |
(650) 0x46f65d CMP %R8,%RAX |
(650) 0x46f660 JNE 46f5f3 |
(648) 0x46f662 MOV %RCX,%R8 |
(648) 0x46f665 AND $-0x4,%R8 |
(648) 0x46f669 ADD %R8,%RSI |
(648) 0x46f66c TEST $0x3,%CL |
(648) 0x46f66f JE 46f6a6 |
(648) 0x46f671 SUB %R8,%RCX |
(648) 0x46f674 CMP $0x1,%RCX |
(648) 0x46f678 JE 46f69a |
(648) 0x46f67a ADD %RDI,%R8 |
(648) 0x46f67d VMOVDDUP %XMM12,%XMM5 |
(648) 0x46f682 LEA (%R12,%R8,8),%RDI |
(648) 0x46f686 VMULPD (%RDI),%XMM5,%XMM15 |
(648) 0x46f68a VMOVUPD %XMM15,(%RDI) |
(648) 0x46f68e TEST $0x1,%CL |
(648) 0x46f691 JE 46f6a6 |
(648) 0x46f693 AND $-0x2,%RCX |
(648) 0x46f697 ADD %RCX,%RSI |
(648) 0x46f69a LEA (%R12,%RSI,8),%RSI |
(648) 0x46f69e VMULSD (%RSI),%XMM12,%XMM1 |
(648) 0x46f6a2 VMOVSD %XMM1,(%RSI) |
(648) 0x46f6a6 MOV 0xa8(%RSP),%RCX |
(648) 0x46f6ae MOV 0xb0(%RSP),%RAX |
(648) 0x46f6b6 MOV (%RCX),%RSI |
(648) 0x46f6b9 MOV (%RAX),%RCX |
(648) 0x46f6bc CMP %RSI,%RCX |
(648) 0x46f6bf JLE 46f83c |
(648) 0x46f6c5 SUB %RSI,%RCX |
(648) 0x46f6c8 MOV %RSI,%RDI |
(648) 0x46f6cb LEA -0x1(%RCX),%RDX |
(648) 0x46f6cf CMP $0x2,%RDX |
(648) 0x46f6d3 JBE 46fba1 |
(648) 0x46f6d9 MOV %RCX,%RDX |
(648) 0x46f6dc LEA (%R11,%RSI,8),%RAX |
(648) 0x46f6e0 VBROADCASTSD %XMM12,%YMM6 |
(648) 0x46f6e5 SHR $0x2,%RDX |
(648) 0x46f6e9 SAL $0x5,%RDX |
(648) 0x46f6ed LEA (%RDX,%RAX,1),%R8 |
(648) 0x46f6f1 SUB $0x20,%RDX |
(648) 0x46f6f5 SHR $0x5,%RDX |
(648) 0x46f6f9 INC %RDX |
(648) 0x46f6fc AND $0x7,%EDX |
(648) 0x46f6ff JE 46f789 |
(648) 0x46f705 CMP $0x1,%RDX |
(648) 0x46f709 JE 46f777 |
(648) 0x46f70b CMP $0x2,%RDX |
(648) 0x46f70f JE 46f76a |
(648) 0x46f711 CMP $0x3,%RDX |
(648) 0x46f715 JE 46f75d |
(648) 0x46f717 CMP $0x4,%RDX |
(648) 0x46f71b JE 46f750 |
(648) 0x46f71d CMP $0x5,%RDX |
(648) 0x46f721 JE 46f743 |
(648) 0x46f723 CMP $0x6,%RDX |
(648) 0x46f727 JE 46f736 |
(648) 0x46f729 VMULPD (%RAX),%YMM6,%YMM7 |
(648) 0x46f72d ADD $0x20,%RAX |
(648) 0x46f731 VMOVUPD %YMM7,-0x20(%RAX) |
(648) 0x46f736 VMULPD (%RAX),%YMM6,%YMM2 |
(648) 0x46f73a ADD $0x20,%RAX |
(648) 0x46f73e VMOVUPD %YMM2,-0x20(%RAX) |
(648) 0x46f743 VMULPD (%RAX),%YMM6,%YMM0 |
(648) 0x46f747 ADD $0x20,%RAX |
(648) 0x46f74b VMOVUPD %YMM0,-0x20(%RAX) |
(648) 0x46f750 VMULPD (%RAX),%YMM6,%YMM8 |
(648) 0x46f754 ADD $0x20,%RAX |
(648) 0x46f758 VMOVUPD %YMM8,-0x20(%RAX) |
(648) 0x46f75d VMULPD (%RAX),%YMM6,%YMM9 |
(648) 0x46f761 ADD $0x20,%RAX |
(648) 0x46f765 VMOVUPD %YMM9,-0x20(%RAX) |
(648) 0x46f76a VMULPD (%RAX),%YMM6,%YMM10 |
(648) 0x46f76e ADD $0x20,%RAX |
(648) 0x46f772 VMOVUPD %YMM10,-0x20(%RAX) |
(648) 0x46f777 VMULPD (%RAX),%YMM6,%YMM11 |
(648) 0x46f77b ADD $0x20,%RAX |
(648) 0x46f77f VMOVUPD %YMM11,-0x20(%RAX) |
(648) 0x46f784 CMP %R8,%RAX |
(648) 0x46f787 JE 46f7f8 |
(649) 0x46f789 VMULPD (%RAX),%YMM6,%YMM13 |
(649) 0x46f78d ADD $0x100,%RAX |
(649) 0x46f793 VMULPD -0xe0(%RAX),%YMM6,%YMM14 |
(649) 0x46f79b VMULPD -0xc0(%RAX),%YMM6,%YMM5 |
(649) 0x46f7a3 VMULPD -0xa0(%RAX),%YMM6,%YMM15 |
(649) 0x46f7ab VMULPD -0x80(%RAX),%YMM6,%YMM1 |
(649) 0x46f7b0 VMULPD -0x60(%RAX),%YMM6,%YMM7 |
(649) 0x46f7b5 VMOVUPD %YMM13,-0x100(%RAX) |
(649) 0x46f7bd VMULPD -0x40(%RAX),%YMM6,%YMM2 |
(649) 0x46f7c2 VMOVUPD %YMM14,-0xe0(%RAX) |
(649) 0x46f7ca VMULPD -0x20(%RAX),%YMM6,%YMM0 |
(649) 0x46f7cf VMOVUPD %YMM5,-0xc0(%RAX) |
(649) 0x46f7d7 VMOVUPD %YMM15,-0xa0(%RAX) |
(649) 0x46f7df VMOVUPD %YMM1,-0x80(%RAX) |
(649) 0x46f7e4 VMOVUPD %YMM7,-0x60(%RAX) |
(649) 0x46f7e9 VMOVUPD %YMM2,-0x40(%RAX) |
(649) 0x46f7ee VMOVUPD %YMM0,-0x20(%RAX) |
(649) 0x46f7f3 CMP %R8,%RAX |
(649) 0x46f7f6 JNE 46f789 |
(648) 0x46f7f8 MOV %RCX,%R8 |
(648) 0x46f7fb AND $-0x4,%R8 |
(648) 0x46f7ff ADD %R8,%RSI |
(648) 0x46f802 TEST $0x3,%CL |
(648) 0x46f805 JE 46f83c |
(648) 0x46f807 SUB %R8,%RCX |
(648) 0x46f80a CMP $0x1,%RCX |
(648) 0x46f80e JE 46f830 |
(648) 0x46f810 ADD %RDI,%R8 |
(648) 0x46f813 VMOVDDUP %XMM12,%XMM6 |
(648) 0x46f818 LEA (%R11,%R8,8),%RDI |
(648) 0x46f81c VMULPD (%RDI),%XMM6,%XMM8 |
(648) 0x46f820 VMOVUPD %XMM8,(%RDI) |
(648) 0x46f824 TEST $0x1,%CL |
(648) 0x46f827 JE 46f83c |
(648) 0x46f829 AND $-0x2,%RCX |
(648) 0x46f82d ADD %RCX,%RSI |
(648) 0x46f830 LEA (%R11,%RSI,8),%RSI |
(648) 0x46f834 VMULSD (%RSI),%XMM12,%XMM9 |
(648) 0x46f838 VMOVSD %XMM9,(%RSI) |
(648) 0x46f83c ADDQ $0x8,0xf8(%RSP) |
(648) 0x46f845 MOV 0xf8(%RSP),%RCX |
(648) 0x46f84d CMP %RCX,0x50(%RSP) |
(648) 0x46f852 JNE 46ea58 |
0x46f858 MOV %R9,%R15 |
0x46f85b VZEROUPPER |
0x46f85e MOV 0x150(%RSP),%RDI |
0x46f866 CALL 595a80 <hypre_Free> |
0x46f86b MOV 0x118(%RSP),%RDI |
0x46f873 CALL 595a80 <hypre_Free> |
0x46f878 MOV %R15,%RDI |
0x46f87b CALL 595a80 <hypre_Free> |
0x46f880 LEA -0x28(%RBP),%RSP |
0x46f884 MOV %RBX,%RDI |
0x46f887 POP %RBX |
0x46f888 POP %R12 |
0x46f88a POP %R13 |
0x46f88c POP %R14 |
0x46f88e POP %R15 |
0x46f890 POP %RBP |
0x46f891 JMP 595a80 |
0x46f896 NOPW %CS:(%RAX,%RAX,1) |
(651) 0x46f8a0 MOV 0x10(%RSP),%RCX |
(651) 0x46f8a5 MOV 0x18(%RSP),%R13 |
(651) 0x46f8aa MOV (%RCX,%R8,1),%RCX |
(651) 0x46f8ae MOV 0x8(%R13,%R8,1),%R10 |
(651) 0x46f8b3 ADD %RCX,%R10 |
(651) 0x46f8b6 MOV %R10,0xe8(%RSP) |
(651) 0x46f8be CMP %R10,%RCX |
(651) 0x46f8c1 JGE 46f462 |
(651) 0x46f8c7 MOV 0x8(%RSP),%R8 |
(651) 0x46f8cc MOV 0xe0(%RSP),%R13 |
(651) 0x46f8d4 SUB %RCX,%R10 |
(651) 0x46f8d7 MOV (%R8,%R13,1),%R8 |
(651) 0x46f8db AND $0x3,%R10D |
(651) 0x46f8df JE 46f9c4 |
(651) 0x46f8e5 CMP $0x1,%R10 |
(651) 0x46f8e9 JE 46f975 |
(651) 0x46f8ef CMP $0x2,%R10 |
(651) 0x46f8f3 JE 46f934 |
(651) 0x46f8f5 VMOVSD (%RDX),%XMM1 |
(651) 0x46f8f9 MOV 0x88(%RSP),%R13 |
(651) 0x46f901 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f905 VMULSD (%R13,%RCX,8),%XMM1,%XMM6 |
(651) 0x46f90c TEST %R10,%R10 |
(651) 0x46f90f JS 46fba9 |
(651) 0x46f915 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f919 LEA (%R11,%R10,8),%R13 |
(651) 0x46f91d VADDSD (%R13),%XMM6,%XMM7 |
(651) 0x46f923 VMOVSD %XMM7,(%R13) |
(651) 0x46f929 VADDSD %XMM6,%XMM2,%XMM2 |
(651) 0x46f92d VADDSD %XMM6,%XMM0,%XMM0 |
(651) 0x46f931 INC %RCX |
(651) 0x46f934 VMOVSD (%RDX),%XMM9 |
(651) 0x46f938 MOV 0x88(%RSP),%R13 |
(651) 0x46f940 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f944 VMULSD (%R13,%RCX,8),%XMM9,%XMM10 |
(651) 0x46f94b TEST %R10,%R10 |
(651) 0x46f94e JS 46fb70 |
(651) 0x46f954 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f958 LEA (%R11,%R10,8),%R13 |
(651) 0x46f95c VADDSD (%R13),%XMM10,%XMM5 |
(651) 0x46f962 VMOVSD %XMM5,(%R13) |
(651) 0x46f968 VADDSD %XMM10,%XMM2,%XMM2 |
(651) 0x46f96d VADDSD %XMM10,%XMM0,%XMM0 |
(651) 0x46f972 INC %RCX |
(651) 0x46f975 VMOVSD (%RDX),%XMM13 |
(651) 0x46f979 MOV 0x88(%RSP),%R13 |
(651) 0x46f981 MOV (%R8,%RCX,8),%R10 |
(651) 0x46f985 VMULSD (%R13,%RCX,8),%XMM13,%XMM12 |
(651) 0x46f98c TEST %R10,%R10 |
(651) 0x46f98f JS 46fb40 |
(651) 0x46f995 MOV (%RBX,%R10,8),%R10 |
(651) 0x46f999 LEA (%R11,%R10,8),%R13 |
(651) 0x46f99d VADDSD (%R13),%XMM12,%XMM14 |
(651) 0x46f9a3 VMOVSD %XMM14,(%R13) |
(651) 0x46f9a9 INC %RCX |
(651) 0x46f9ac VADDSD %XMM12,%XMM2,%XMM2 |
(651) 0x46f9b1 VADDSD %XMM12,%XMM0,%XMM0 |
(651) 0x46f9b6 CMP %RCX,0xe8(%RSP) |
(651) 0x46f9be JE 46f462 |
(651) 0x46f9c4 MOV %R14,(%RSP) |
(651) 0x46f9c8 MOV 0x88(%RSP),%R13 |
(651) 0x46f9d0 JMP 46fa76 |
0x46f9d5 NOPL (%RAX) |
(652) 0x46f9d8 MOV (%RBX,%R10,8),%R14 |
(652) 0x46f9dc LEA (%R11,%R14,8),%R10 |
(652) 0x46f9e0 VADDSD (%R10),%XMM9,%XMM10 |
(652) 0x46f9e5 VMOVSD %XMM10,(%R10) |
(652) 0x46f9ea LEA 0x1(%RCX),%R14 |
(652) 0x46f9ee VMOVSD (%RDX),%XMM14 |
(652) 0x46f9f2 VADDSD %XMM9,%XMM2,%XMM11 |
(652) 0x46f9f7 MOV (%R8,%R14,8),%R10 |
(652) 0x46f9fb VADDSD %XMM9,%XMM0,%XMM13 |
(652) 0x46fa00 VMULSD (%R13,%R14,8),%XMM14,%XMM15 |
(652) 0x46fa07 TEST %R10,%R10 |
(652) 0x46fa0a JS 46fb20 |
(652) 0x46fa10 MOV (%RBX,%R10,8),%R14 |
(652) 0x46fa14 LEA (%R11,%R14,8),%R10 |
(652) 0x46fa18 VADDSD (%R10),%XMM15,%XMM12 |
(652) 0x46fa1d VMOVSD %XMM12,(%R10) |
(652) 0x46fa22 LEA 0x2(%RCX),%R14 |
(652) 0x46fa26 VMOVSD (%RDX),%XMM2 |
(652) 0x46fa2a VADDSD %XMM15,%XMM11,%XMM6 |
(652) 0x46fa2f MOV (%R8,%R14,8),%R10 |
(652) 0x46fa33 VADDSD %XMM15,%XMM13,%XMM7 |
(652) 0x46fa38 VMULSD (%R13,%R14,8),%XMM2,%XMM12 |
(652) 0x46fa3f TEST %R10,%R10 |
(652) 0x46fa42 JS 46fb00 |
(652) 0x46fa48 MOV (%RBX,%R10,8),%R14 |
(652) 0x46fa4c LEA (%R11,%R14,8),%R10 |
(652) 0x46fa50 VADDSD (%R10),%XMM12,%XMM0 |
(652) 0x46fa55 VMOVSD %XMM0,(%R10) |
(652) 0x46fa5a ADD $0x3,%RCX |
(652) 0x46fa5e VADDSD %XMM12,%XMM6,%XMM2 |
(652) 0x46fa63 VADDSD %XMM12,%XMM7,%XMM0 |
(652) 0x46fa68 CMP %RCX,0xe8(%RSP) |
(652) 0x46fa70 JE 46fb60 |
(652) 0x46fa76 VMOVSD (%RDX),%XMM12 |
(652) 0x46fa7a MOV (%R8,%RCX,8),%R14 |
(652) 0x46fa7e VMULSD (%R13,%RCX,8),%XMM12,%XMM1 |
(652) 0x46fa85 TEST %R14,%R14 |
(652) 0x46fa88 JS 46fae0 |
(652) 0x46fa8a MOV (%RBX,%R14,8),%R10 |
(652) 0x46fa8e LEA (%R11,%R10,8),%R14 |
(652) 0x46fa92 VADDSD (%R14),%XMM1,%XMM6 |
(652) 0x46fa97 VMOVSD %XMM6,(%R14) |
(652) 0x46fa9c INC %RCX |
(652) 0x46fa9f VMOVSD (%RDX),%XMM8 |
(652) 0x46faa3 VADDSD %XMM1,%XMM2,%XMM2 |
(652) 0x46faa7 VADDSD %XMM1,%XMM0,%XMM0 |
(652) 0x46faab MOV (%R8,%RCX,8),%R10 |
(652) 0x46faaf VMULSD (%R13,%RCX,8),%XMM8,%XMM9 |
(652) 0x46fab6 TEST %R10,%R10 |
(652) 0x46fab9 JNS 46f9d8 |
(652) 0x46fabf NOT %R10 |
(652) 0x46fac2 MOV (%R9,%R10,8),%R14 |
(652) 0x46fac6 LEA (%R12,%R14,8),%R10 |
(652) 0x46faca VADDSD (%R10),%XMM9,%XMM5 |
(652) 0x46facf VMOVSD %XMM5,(%R10) |
(652) 0x46fad4 JMP 46f9ea |
0x46fad9 NOPL (%RAX) |
(652) 0x46fae0 NOT %R14 |
(652) 0x46fae3 MOV (%R9,%R14,8),%R10 |
(652) 0x46fae7 LEA (%R12,%R10,8),%R14 |
(652) 0x46faeb VADDSD (%R14),%XMM1,%XMM7 |
(652) 0x46faf0 VMOVSD %XMM7,(%R14) |
(652) 0x46faf5 JMP 46fa9c |
0x46faf7 NOPW (%RAX,%RAX,1) |
(652) 0x46fb00 NOT %R10 |
(652) 0x46fb03 MOV (%R9,%R10,8),%R14 |
(652) 0x46fb07 LEA (%R12,%R14,8),%R10 |
(652) 0x46fb0b VADDSD (%R10),%XMM12,%XMM8 |
(652) 0x46fb10 VMOVSD %XMM8,(%R10) |
(652) 0x46fb15 JMP 46fa5a |
0x46fb1a NOPW (%RAX,%RAX,1) |
(652) 0x46fb20 NOT %R10 |
(652) 0x46fb23 MOV (%R9,%R10,8),%R14 |
(652) 0x46fb27 LEA (%R12,%R14,8),%R10 |
(652) 0x46fb2b VADDSD (%R10),%XMM15,%XMM1 |
(652) 0x46fb30 VMOVSD %XMM1,(%R10) |
(652) 0x46fb35 JMP 46fa22 |
0x46fb3a NOPW (%RAX,%RAX,1) |
(651) 0x46fb40 NOT %R10 |
(651) 0x46fb43 MOV (%R9,%R10,8),%R10 |
(651) 0x46fb47 LEA (%R12,%R10,8),%R13 |
(651) 0x46fb4b VADDSD (%R13),%XMM12,%XMM15 |
(651) 0x46fb51 VMOVSD %XMM15,(%R13) |
(651) 0x46fb57 JMP 46f9a9 |
0x46fb5c NOPL (%RAX) |
(651) 0x46fb60 MOV (%RSP),%R14 |
(651) 0x46fb64 JMP 46f462 |
0x46fb69 NOPL (%RAX) |
(651) 0x46fb70 NOT %R10 |
(651) 0x46fb73 MOV (%R9,%R10,8),%R10 |
(651) 0x46fb77 LEA (%R12,%R10,8),%R13 |
(651) 0x46fb7b VADDSD (%R13),%XMM10,%XMM11 |
(651) 0x46fb81 VMOVSD %XMM11,(%R13) |
(651) 0x46fb87 JMP 46f968 |
(648) 0x46fb8c VXORPD %XMM0,%XMM0,%XMM0 |
(648) 0x46fb90 VMOVSD %XMM0,%XMM0,%XMM2 |
(648) 0x46fb94 JMP 46f3d8 |
(648) 0x46fb99 XOR %R8D,%R8D |
(648) 0x46fb9c JMP 46f671 |
(648) 0x46fba1 XOR %R8D,%R8D |
(648) 0x46fba4 JMP 46f807 |
(651) 0x46fba9 NOT %R10 |
(651) 0x46fbac MOV (%R9,%R10,8),%R10 |
(651) 0x46fbb0 LEA (%R12,%R10,8),%R13 |
(651) 0x46fbb4 VADDSD (%R13),%XMM6,%XMM8 |
(651) 0x46fbba VMOVSD %XMM8,(%R13) |
(651) 0x46fbc0 JMP 46f929 |
0x46fbc5 MOV %R11,0xb8(%RSP) |
0x46fbcd MOV $0x8,%ESI |
0x46fbd2 MOV %RDX,%RDI |
0x46fbd5 MOV %R10,0xc0(%RSP) |
0x46fbdd VMOVSD %XMM1,0xe0(%RSP) |
0x46fbe6 JMP 46e8a3 |
0x46fbeb MOV $0x8,%ESI |
0x46fbf0 MOV %RCX,%RDI |
0x46fbf3 MOV %R11,0x98(%RSP) |
0x46fbfb MOV %R10,0xa0(%RSP) |
0x46fc03 MOV %RDX,0xb8(%RSP) |
0x46fc0b MOV %R8,0xc0(%RSP) |
0x46fc13 VMOVSD %XMM1,0xe0(%RSP) |
0x46fc1c CALL 5959c0 <hypre_CAlloc> |
0x46fc21 VMOVSD 0xe0(%RSP),%XMM1 |
0x46fc2a MOV 0xc0(%RSP),%R8 |
0x46fc32 MOV 0xb8(%RSP),%RDX |
0x46fc3a MOV 0xa0(%RSP),%R10 |
0x46fc42 MOV %RAX,%R15 |
0x46fc45 MOV 0x98(%RSP),%R11 |
0x46fc4d JMP 46e879 |
0x46fc52 MOV $0x8,%ESI |
0x46fc57 MOV %R14,%RDI |
0x46fc5a MOV %R11,0x90(%RSP) |
0x46fc62 MOV %R10,0x98(%RSP) |
0x46fc6a MOV %RCX,0xa0(%RSP) |
0x46fc72 MOV %RDX,0xb8(%RSP) |
0x46fc7a MOV %R8,0xc0(%RSP) |
0x46fc82 VMOVSD %XMM1,0xe0(%RSP) |
0x46fc8b CALL 5959c0 <hypre_CAlloc> |
0x46fc90 VMOVSD 0xe0(%RSP),%XMM1 |
0x46fc99 MOV 0xc0(%RSP),%R8 |
0x46fca1 MOV 0xb8(%RSP),%RDX |
0x46fca9 MOV 0xa0(%RSP),%RCX |
0x46fcb1 MOV %RAX,0x118(%RSP) |
0x46fcb9 MOV 0x98(%RSP),%R10 |
0x46fcc1 MOV 0x90(%RSP),%R11 |
0x46fcc9 JMP 46e86d |
0x46fcce MOV %RSI,%RDI |
0x46fcd1 MOV $0x8,%ESI |
0x46fcd6 MOV %R11,0x98(%RSP) |
0x46fcde MOV %R10,0xa0(%RSP) |
0x46fce6 MOV %RCX,0xb8(%RSP) |
0x46fcee MOV %RDX,0xc0(%RSP) |
0x46fcf6 MOV %R8,0xe0(%RSP) |
0x46fcfe VMOVSD %XMM1,0x118(%RSP) |
0x46fd07 CALL 5959c0 <hypre_CAlloc> |
0x46fd0c VMOVSD 0x118(%RSP),%XMM1 |
0x46fd15 MOV 0xe0(%RSP),%R8 |
0x46fd1d MOV 0xc0(%RSP),%RDX |
0x46fd25 MOV 0xb8(%RSP),%RCX |
0x46fd2d MOV %RAX,0x150(%RSP) |
0x46fd35 MOV 0xa0(%RSP),%R10 |
0x46fd3d MOV 0x98(%RSP),%R11 |
0x46fd45 JMP 46e858 |
0x46fd4a NOPW (%RAX,%RAX,1) |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1576 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
cycles | 6.80 | 8.00 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.09 |
Stall cycles | 0.93 |
RS full (events) | 4.18 |
Front-end | 46.00 |
Dispatch | 45.00 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x160,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fcce <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x167e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc52 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1602> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fbeb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x159b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fbc5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1575> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x158(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 46e91f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46e970 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x320> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989f0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5989e0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x158(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46f85e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x120e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x13031b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xa8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 595a80 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e8a3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x253> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e879 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e86d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x21d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x118(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e858 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x208> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1576 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
cycles | 6.80 | 8.00 | 30.67 | 30.67 | 45.00 | 6.80 | 6.80 | 45.00 | 45.00 | 45.00 | 6.80 | 30.67 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.09 |
Stall cycles | 0.93 |
RS full (events) | 4.18 |
Front-end | 46.00 |
Dispatch | 45.00 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 5% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 11% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x20,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x160,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x18(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x10(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x20(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fcce <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x167e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fc52 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1602> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 46fbeb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x159b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46fbc5 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1575> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x158(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 46e91f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2cf> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 46e970 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x320> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x158(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5989f0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5989e0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0xe8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x158(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46f85e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x120e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xb0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x13031b(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xa8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R9,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x150(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x118(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 595a80 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 595a80 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e8a3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x253> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e879 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0xe0(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xa0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x98(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x90(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e86d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x21d> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM1,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5959c0 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x118(%RSP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e858 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x208> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.10– | 2.49 | 0.3 |
▼Loop 648 - par_multi_interp.c:1774-1876 - exec– | 0.33 | 0.03 |
▼Loop 653 - par_multi_interp.c:1811-1837 - exec– | 1.41 | 0.13 |
○Loop 654 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 655 - par_multi_interp.c:1816-1822 - exec | 0 | 0 |
○Loop 657 - par_multi_interp.c:1799-1803 - exec | 0.74 | 0.07 |
▼Loop 651 - par_multi_interp.c:1840-1867 - exec– | 0.01 | 0 |
○Loop 652 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 656 - par_multi_interp.c:1805-1809 - exec | 0 | 0 |
○Loop 658 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 649 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 650 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |
○Loop 659 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |