Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 2.67% |
---|
Function: hypre_BoomerAMGBuildMultipass._omp_fn.10 | Module: exec | Source: par_multi_interp.c:1737-1881 [...] | Coverage: 2.67% |
---|
/scratch_na/users/xoserete/qaas_runs/171-587-0261/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881 |
-------------------------------------------------------------------------------- |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1746: tmp_marker = NULL; |
1747: if (n_fine) |
1748: { tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); } |
1749: tmp_marker_offd = NULL; |
1750: if (num_cols_offd) |
1751: { tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1752: tmp_array = NULL; |
1753: if (n_coarse) |
1754: { tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); } |
1755: tmp_array_offd = NULL; |
1756: if (new_num_cols_offd > n_coarse_offd) |
1757: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1758: else |
1759: { tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);} |
1760: for (i=0; i < n_fine; i++) |
1761: { tmp_marker[i] = -1; } |
1762: for (i=0; i < num_cols_offd; i++) |
1763: { tmp_marker_offd[i] = -1; } |
1764: |
1765: /* Compute this thread's range of pass_length */ |
1766: my_thread_num = hypre_GetThreadNum(); |
1767: num_threads = hypre_NumActiveThreads(); |
1768: thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num; |
1769: if (my_thread_num == num_threads-1) |
1770: { thread_stop = pass_pointer[pass] + pass_length; } |
1771: else |
1772: { thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); } |
1773: |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
1877: } |
1878: hypre_TFree(tmp_marker); |
1879: hypre_TFree(tmp_marker_offd); |
1880: hypre_TFree(tmp_array); |
1881: hypre_TFree(tmp_array_offd); |
0x472bf0 PUSH %RBP |
0x472bf1 MOV %RSP,%RBP |
0x472bf4 PUSH %R15 |
0x472bf6 PUSH %R14 |
0x472bf8 PUSH %R13 |
0x472bfa PUSH %R12 |
0x472bfc PUSH %RBX |
0x472bfd AND $-0x40,%RSP |
0x472c01 SUB $0x180,%RSP |
0x472c08 MOV 0x148(%RDI),%RAX |
0x472c0f MOV 0x138(%RDI),%RDX |
0x472c16 MOV 0x130(%RDI),%RCX |
0x472c1d MOV 0x128(%RDI),%RBX |
0x472c24 MOV 0x108(%RDI),%R9 |
0x472c2b MOV 0x100(%RDI),%R10 |
0x472c32 MOV %RAX,0x168(%RSP) |
0x472c3a MOV 0xf8(%RDI),%R11 |
0x472c41 MOV 0xf0(%RDI),%R12 |
0x472c48 MOV %RDX,0xa8(%RSP) |
0x472c50 MOV 0xe8(%RDI),%R13 |
0x472c57 MOV 0xe0(%RDI),%R14 |
0x472c5e MOV %RCX,0x158(%RSP) |
0x472c66 MOV 0x110(%RDI),%RSI |
0x472c6d MOV 0x140(%RDI),%R8 |
0x472c74 MOV %RBX,0x150(%RSP) |
0x472c7c MOV %R9,0x130(%RSP) |
0x472c84 MOV 0x120(%RDI),%RDX |
0x472c8b MOV %R10,0x118(%RSP) |
0x472c93 MOV 0x118(%RDI),%RCX |
0x472c9a MOV %R11,0x38(%RSP) |
0x472c9f MOV %R12,0x28(%RSP) |
0x472ca4 MOV %R13,0x68(%RSP) |
0x472ca9 MOV %R14,0x60(%RSP) |
0x472cae MOV %RSI,0x178(%RSP) |
0x472cb6 MOV 0xd8(%RDI),%R15 |
0x472cbd MOV 0xd0(%RDI),%RAX |
0x472cc4 MOV 0xc8(%RDI),%RBX |
0x472ccb MOV 0xc0(%RDI),%R9 |
0x472cd2 MOV 0xb8(%RDI),%R10 |
0x472cd9 MOV %R15,0xa0(%RSP) |
0x472ce1 MOV 0x68(%RDI),%R15 |
0x472ce5 MOV 0xb0(%RDI),%R11 |
0x472cec MOV %RAX,0x98(%RSP) |
0x472cf4 MOV 0xa8(%RDI),%R12 |
0x472cfb MOV 0x98(%RDI),%R13 |
0x472d02 MOV %RBX,0x110(%RSP) |
0x472d0a MOV 0x80(%RDI),%R14 |
0x472d11 MOV 0x60(%RDI),%RAX |
0x472d15 MOV %R9,0xd0(%RSP) |
0x472d1d MOV 0x58(%RDI),%RBX |
0x472d21 MOV 0x50(%RDI),%R9 |
0x472d25 MOV %R15,0x148(%RSP) |
0x472d2d MOV 0x48(%RDI),%R15 |
0x472d31 MOV %R10,0x108(%RSP) |
0x472d39 MOV %R11,0x58(%RSP) |
0x472d3e MOV 0xa0(%RDI),%R10 |
0x472d45 MOV %R12,0x30(%RSP) |
0x472d4a MOV 0x90(%RDI),%R11 |
0x472d51 MOV %R13,0xf8(%RSP) |
0x472d59 MOV 0x78(%RDI),%R12 |
0x472d5d MOV %R14,0xf0(%RSP) |
0x472d65 MOV 0x88(%RDI),%R13 |
0x472d6c MOV %RAX,0x90(%RSP) |
0x472d74 MOV 0x70(%RDI),%R14 |
0x472d78 MOV %RBX,0x140(%RSP) |
0x472d80 MOV %R9,0x88(%RSP) |
0x472d88 MOV %R15,0x50(%RSP) |
0x472d8d MOV 0x40(%RDI),%RAX |
0x472d91 MOV 0x38(%RDI),%RBX |
0x472d95 MOV 0x30(%RDI),%R9 |
0x472d99 MOV 0x28(%RDI),%R15 |
0x472d9d MOV %RAX,0x80(%RSP) |
0x472da5 MOV %RBX,0x48(%RSP) |
0x472daa MOV 0x20(%RDI),%RAX |
0x472dae MOV 0x18(%RDI),%RBX |
0x472db2 MOV %R9,0x40(%RSP) |
0x472db7 MOV %R15,0x78(%RSP) |
0x472dbc MOV 0x10(%RDI),%R9 |
0x472dc0 MOV 0x8(%RDI),%R15 |
0x472dc4 MOV (%RDI),%RDI |
0x472dc7 MOV %RAX,0xe8(%RSP) |
0x472dcf MOV %RBX,0xc8(%RSP) |
0x472dd7 MOV %R9,0x120(%RSP) |
0x472ddf MOV %R15,0x160(%RSP) |
0x472de7 MOV %RDI,0x128(%RSP) |
0x472def TEST %RSI,%RSI |
0x472df2 JNE 474397 |
0x472df8 MOVQ $0,0x170(%RSP) |
0x472e04 TEST %R14,%R14 |
0x472e07 JNE 47431b |
0x472e0d MOVQ $0,0x138(%RSP) |
0x472e19 TEST %RCX,%RCX |
0x472e1c JNE 4742b4 |
0x472e22 XOR %R15D,%R15D |
0x472e25 CMP %RDX,%R8 |
0x472e28 JLE 47428e |
0x472e2e MOV %R11,0xd8(%RSP) |
0x472e36 MOV $0x8,%ESI |
0x472e3b MOV %R8,%RDI |
0x472e3e MOV %R10,0xe0(%RSP) |
0x472e46 VMOVSD %XMM2,0x100(%RSP) |
0x472e4f CALL 5b0890 <hypre_CAlloc> |
0x472e54 CMPQ $0,0x178(%RSP) |
0x472e5d VMOVSD 0x100(%RSP),%XMM2 |
0x472e66 MOV %RAX,%RBX |
0x472e69 MOV 0xe0(%RSP),%RSI |
0x472e71 MOV 0xd8(%RSP),%RAX |
0x472e79 JLE 472ecb |
0x472e7b MOV 0x178(%RSP),%RDX |
0x472e83 MOV 0x170(%RSP),%RDI |
0x472e8b MOV %RSI,0xe0(%RSP) |
0x472e93 MOV $0xff,%ESI |
0x472e98 VMOVSD %XMM2,0x100(%RSP) |
0x472ea1 SAL $0x3,%RDX |
0x472ea5 MOV %RAX,0xd8(%RSP) |
0x472ead CALL 4110a0 <memset@plt> |
0x472eb2 VMOVSD 0x100(%RSP),%XMM2 |
0x472ebb MOV 0xe0(%RSP),%RSI |
0x472ec3 MOV 0xd8(%RSP),%RAX |
0x472ecb TEST %R14,%R14 |
0x472ece JLE 472f1c |
0x472ed0 MOV 0x138(%RSP),%RDI |
0x472ed8 MOV %RSI,0x100(%RSP) |
0x472ee0 LEA (,%R14,8),%RDX |
0x472ee8 MOV $0xff,%ESI |
0x472eed VMOVSD %XMM2,0x178(%RSP) |
0x472ef6 MOV %RAX,0xe0(%RSP) |
0x472efe CALL 4110a0 <memset@plt> |
0x472f03 VMOVSD 0x178(%RSP),%XMM2 |
0x472f0c MOV 0x100(%RSP),%RSI |
0x472f14 MOV 0xe0(%RSP),%RAX |
0x472f1c MOV %RSI,0xe0(%RSP) |
0x472f24 VMOVSD %XMM2,0x178(%RSP) |
0x472f2d MOV %RAX,0xd8(%RSP) |
0x472f35 CALL 5b39c0 <hypre_GetThreadNum> |
0x472f3a MOV %RAX,%R14 |
0x472f3d CALL 5b39b0 <hypre_NumActiveThreads> |
0x472f42 MOV 0x130(%RSP),%R8 |
0x472f4a MOV 0x110(%RSP),%RDX |
0x472f52 MOV %R14,%R10 |
0x472f55 MOV %RAX,%R9 |
0x472f58 MOV 0x168(%RSP),%RAX |
0x472f60 MOV 0x168(%RSP),%R11 |
0x472f68 MOV (%RDX,%R8,8),%RCX |
0x472f6c LEA (,%R8,8),%RDI |
0x472f74 VMOVSD 0x178(%RSP),%XMM12 |
0x472f7d CQTO |
0x472f7f MOV %RDI,0x100(%RSP) |
0x472f87 IDIV %R9 |
0x472f8a ADD %RCX,%R11 |
0x472f8d DEC %R9 |
0x472f90 MOV %R11,%R8 |
0x472f93 MOV 0xd8(%RSP),%R11 |
0x472f9b IMUL %RAX,%R10 |
0x472f9f ADD %R10,%RAX |
0x472fa2 LEA (%RCX,%R10,1),%RSI |
0x472fa6 MOV 0xe0(%RSP),%R10 |
0x472fae ADD %RCX,%RAX |
0x472fb1 CMP %R9,%R14 |
0x472fb4 CMOVNE %RAX,%R8 |
0x472fb8 CMP %RSI,%R8 |
0x472fbb JLE 473efc |
0x472fc1 MOV 0xd0(%RSP),%R14 |
0x472fc9 VMOVQ 0x146e6f(%RIP),%XMM4 |
0x472fd1 VXORPD %XMM3,%XMM3,%XMM3 |
0x472fd5 LEA (%R14,%RSI,8),%R9 |
0x472fd9 LEA (%R14,%R8,8),%RDI |
0x472fdd MOV 0x130(%RSP),%R14 |
0x472fe5 MOV %R15,0x130(%RSP) |
0x472fed MOV %R9,0x110(%RSP) |
0x472ff5 MOV 0xc8(%RSP),%R15 |
0x472ffd MOV %RDI,0x70(%RSP) |
0x473002 DEC %R14 |
0x473005 NOPL (%RAX) |
(647) 0x473008 MOV 0x110(%RSP),%RCX |
(647) 0x473010 MOV 0xf0(%RSP),%R8 |
(647) 0x473018 MOV 0x98(%RSP),%RDX |
(647) 0x473020 MOV (%RCX),%RDI |
(647) 0x473023 LEA (,%RDI,8),%RAX |
(647) 0x47302b MOV (%RDX,%RDI,8),%RDX |
(647) 0x47302f LEA 0x8(%RAX),%RCX |
(647) 0x473033 MOV %RAX,0x168(%RSP) |
(647) 0x47303b ADD %R8,%RAX |
(647) 0x47303e LEA (%R8,%RCX,1),%RSI |
(647) 0x473042 MOV %RAX,0xd8(%RSP) |
(647) 0x47304a MOV (%RAX),%RAX |
(647) 0x47304d MOV (%RSI),%R9 |
(647) 0x473050 MOV %RSI,0xe0(%RSP) |
(647) 0x473058 ADD %RDX,%R9 |
(647) 0x47305b SUB %RAX,%R9 |
(647) 0x47305e CMP %R9,%RDX |
(647) 0x473061 JGE 473295 |
(647) 0x473067 MOV %RAX,%RSI |
(647) 0x47306a MOV 0x60(%RSP),%R8 |
(647) 0x47306f SUB %RDX,%RSI |
(647) 0x473072 SUB %RAX,%RDX |
(647) 0x473075 ADD %R9,%RSI |
(647) 0x473078 MOV 0x100(%RSP),%R9 |
(647) 0x473080 MOV (%R8,%R9,1),%R8 |
(647) 0x473084 MOV %RSI,%R9 |
(647) 0x473087 SUB %RAX,%R9 |
(647) 0x47308a LEA (%R8,%RDX,8),%RDX |
(647) 0x47308e AND $0x7,%R9D |
(647) 0x473092 JE 47423a |
(647) 0x473098 CMP $0x1,%R9 |
(647) 0x47309c JE 473188 |
(647) 0x4730a2 CMP $0x2,%R9 |
(647) 0x4730a6 JE 473168 |
(647) 0x4730ac CMP $0x3,%R9 |
(647) 0x4730b0 JE 473148 |
(647) 0x4730b6 CMP $0x4,%R9 |
(647) 0x4730ba JE 473128 |
(647) 0x4730bc CMP $0x5,%R9 |
(647) 0x4730c0 JE 473108 |
(647) 0x4730c2 CMP $0x6,%R9 |
(647) 0x4730c6 JE 4730e8 |
(647) 0x4730c8 MOV (%RDX,%RAX,8),%R8 |
(647) 0x4730cc MOV 0x130(%RSP),%R9 |
(647) 0x4730d4 MOV %RAX,(%R9,%R8,8) |
(647) 0x4730d8 MOVQ $0,(%R12,%RAX,8) |
(647) 0x4730e0 INC %RAX |
(647) 0x4730e3 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x4730e8 MOV (%RDX,%RAX,8),%R8 |
(647) 0x4730ec MOV 0x130(%RSP),%R9 |
(647) 0x4730f4 MOV %RAX,(%R9,%R8,8) |
(647) 0x4730f8 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473100 INC %RAX |
(647) 0x473103 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473108 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47310c MOV 0x130(%RSP),%R9 |
(647) 0x473114 MOV %RAX,(%R9,%R8,8) |
(647) 0x473118 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473120 INC %RAX |
(647) 0x473123 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473128 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47312c MOV 0x130(%RSP),%R9 |
(647) 0x473134 MOV %RAX,(%R9,%R8,8) |
(647) 0x473138 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473140 INC %RAX |
(647) 0x473143 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473148 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47314c MOV 0x130(%RSP),%R9 |
(647) 0x473154 MOV %RAX,(%R9,%R8,8) |
(647) 0x473158 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473160 INC %RAX |
(647) 0x473163 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473168 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47316c MOV 0x130(%RSP),%R9 |
(647) 0x473174 MOV %RAX,(%R9,%R8,8) |
(647) 0x473178 MOVQ $0,(%R12,%RAX,8) |
(647) 0x473180 INC %RAX |
(647) 0x473183 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x473188 MOV (%RDX,%RAX,8),%R8 |
(647) 0x47318c MOV 0x130(%RSP),%R9 |
(647) 0x473194 MOV %RAX,(%R9,%R8,8) |
(647) 0x473198 MOVQ $0,(%R12,%RAX,8) |
(647) 0x4731a0 INC %RAX |
(647) 0x4731a3 MOV %R8,-0x8(%R13,%RAX,8) |
(647) 0x4731a8 CMP %RAX,%RSI |
(647) 0x4731ab JE 473295 |
(647) 0x4731b1 MOV %RBX,0x178(%RSP) |
(647) 0x4731b9 MOV %R9,%R8 |
(658) 0x4731bc MOV (%RDX,%RAX,8),%RBX |
(658) 0x4731c0 LEA 0x1(%RAX),%R9 |
(658) 0x4731c4 MOV %RAX,(%R8,%RBX,8) |
(658) 0x4731c8 MOVQ $0,(%R12,%RAX,8) |
(658) 0x4731d0 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x4731d5 MOV (%RDX,%R9,8),%RBX |
(658) 0x4731d9 MOV %R9,(%R8,%RBX,8) |
(658) 0x4731dd MOVQ $0,(%R12,%R9,8) |
(658) 0x4731e5 LEA 0x2(%RAX),%R9 |
(658) 0x4731e9 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x4731ee MOV (%RDX,%R9,8),%RBX |
(658) 0x4731f2 MOV %R9,(%R8,%RBX,8) |
(658) 0x4731f6 MOVQ $0,(%R12,%R9,8) |
(658) 0x4731fe LEA 0x3(%RAX),%R9 |
(658) 0x473202 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473207 MOV (%RDX,%R9,8),%RBX |
(658) 0x47320b MOV %R9,(%R8,%RBX,8) |
(658) 0x47320f MOVQ $0,(%R12,%R9,8) |
(658) 0x473217 LEA 0x4(%RAX),%R9 |
(658) 0x47321b MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473220 MOV (%RDX,%R9,8),%RBX |
(658) 0x473224 MOV %R9,(%R8,%RBX,8) |
(658) 0x473228 MOVQ $0,(%R12,%R9,8) |
(658) 0x473230 LEA 0x5(%RAX),%R9 |
(658) 0x473234 MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473239 MOV (%RDX,%R9,8),%RBX |
(658) 0x47323d MOV %R9,(%R8,%RBX,8) |
(658) 0x473241 MOVQ $0,(%R12,%R9,8) |
(658) 0x473249 LEA 0x6(%RAX),%R9 |
(658) 0x47324d MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x473252 MOV (%RDX,%R9,8),%RBX |
(658) 0x473256 MOV %R9,(%R8,%RBX,8) |
(658) 0x47325a MOVQ $0,(%R12,%R9,8) |
(658) 0x473262 LEA 0x7(%RAX),%R9 |
(658) 0x473266 ADD $0x8,%RAX |
(658) 0x47326a MOV %RBX,-0x8(%R13,%R9,8) |
(658) 0x47326f MOV (%RDX,%R9,8),%RBX |
(658) 0x473273 MOV %R9,(%R8,%RBX,8) |
(658) 0x473277 MOVQ $0,(%R12,%R9,8) |
(658) 0x47327f MOV %RBX,-0x8(%R13,%RAX,8) |
(658) 0x473284 CMP %RAX,%RSI |
(658) 0x473287 JNE 4731bc |
(647) 0x47328d MOV 0x178(%RSP),%RBX |
(647) 0x473295 MOV 0xf8(%RSP),%R8 |
(647) 0x47329d MOV 0x168(%RSP),%R9 |
(647) 0x4732a5 MOV 0xa0(%RSP),%RAX |
(647) 0x4732ad LEA (%R8,%RCX,1),%RSI |
(647) 0x4732b1 ADD %R9,%R8 |
(647) 0x4732b4 MOV (%RAX,%RDI,8),%RDX |
(647) 0x4732b8 MOV (%R8),%RAX |
(647) 0x4732bb MOV %R8,0xc8(%RSP) |
(647) 0x4732c3 MOV (%RSI),%R8 |
(647) 0x4732c6 MOV %RSI,0xd0(%RSP) |
(647) 0x4732ce ADD %RDX,%R8 |
(647) 0x4732d1 SUB %RAX,%R8 |
(647) 0x4732d4 CMP %R8,%RDX |
(647) 0x4732d7 JGE 4734bc |
(647) 0x4732dd MOV %RAX,%RSI |
(647) 0x4732e0 MOV 0x100(%RSP),%R9 |
(647) 0x4732e8 SUB %RDX,%RSI |
(647) 0x4732eb SUB %RAX,%RDX |
(647) 0x4732ee ADD %R8,%RSI |
(647) 0x4732f1 MOV 0x68(%RSP),%R8 |
(647) 0x4732f6 MOV (%R8,%R9,1),%R8 |
(647) 0x4732fa MOV %RSI,%R9 |
(647) 0x4732fd SUB %RAX,%R9 |
(647) 0x473300 LEA (%R8,%RDX,8),%RDX |
(647) 0x473304 AND $0x7,%R9D |
(647) 0x473308 JE 4733eb |
(647) 0x47330e CMP $0x1,%R9 |
(647) 0x473312 JE 4733ca |
(647) 0x473318 CMP $0x2,%R9 |
(647) 0x47331c JE 4733b2 |
(647) 0x473322 CMP $0x3,%R9 |
(647) 0x473326 JE 47339a |
(647) 0x473328 CMP $0x4,%R9 |
(647) 0x47332c JE 473382 |
(647) 0x47332e CMP $0x5,%R9 |
(647) 0x473332 JE 47336a |
(647) 0x473334 CMP $0x6,%R9 |
(647) 0x473338 JE 473352 |
(647) 0x47333a MOV (%RDX,%RAX,8),%R8 |
(647) 0x47333e MOV %RAX,(%RBX,%R8,8) |
(647) 0x473342 MOVQ $0,(%R11,%RAX,8) |
(647) 0x47334a INC %RAX |
(647) 0x47334d MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x473352 MOV (%RDX,%RAX,8),%R9 |
(647) 0x473356 MOV %RAX,(%RBX,%R9,8) |
(647) 0x47335a MOVQ $0,(%R11,%RAX,8) |
(647) 0x473362 INC %RAX |
(647) 0x473365 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x47336a MOV (%RDX,%RAX,8),%R8 |
(647) 0x47336e MOV %RAX,(%RBX,%R8,8) |
(647) 0x473372 MOVQ $0,(%R11,%RAX,8) |
(647) 0x47337a INC %RAX |
(647) 0x47337d MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x473382 MOV (%RDX,%RAX,8),%R9 |
(647) 0x473386 MOV %RAX,(%RBX,%R9,8) |
(647) 0x47338a MOVQ $0,(%R11,%RAX,8) |
(647) 0x473392 INC %RAX |
(647) 0x473395 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x47339a MOV (%RDX,%RAX,8),%R8 |
(647) 0x47339e MOV %RAX,(%RBX,%R8,8) |
(647) 0x4733a2 MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733aa INC %RAX |
(647) 0x4733ad MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x4733b2 MOV (%RDX,%RAX,8),%R9 |
(647) 0x4733b6 MOV %RAX,(%RBX,%R9,8) |
(647) 0x4733ba MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733c2 INC %RAX |
(647) 0x4733c5 MOV %R9,-0x8(%R10,%RAX,8) |
(647) 0x4733ca MOV (%RDX,%RAX,8),%R8 |
(647) 0x4733ce MOV %RAX,(%RBX,%R8,8) |
(647) 0x4733d2 MOVQ $0,(%R11,%RAX,8) |
(647) 0x4733da INC %RAX |
(647) 0x4733dd MOV %R8,-0x8(%R10,%RAX,8) |
(647) 0x4733e2 CMP %RAX,%RSI |
(647) 0x4733e5 JE 4734bc |
(657) 0x4733eb MOV (%RDX,%RAX,8),%R9 |
(657) 0x4733ef LEA 0x1(%RAX),%R8 |
(657) 0x4733f3 MOV %RAX,(%RBX,%R9,8) |
(657) 0x4733f7 MOVQ $0,(%R11,%RAX,8) |
(657) 0x4733ff MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x473404 MOV (%RDX,%R8,8),%R9 |
(657) 0x473408 MOV %R8,(%RBX,%R9,8) |
(657) 0x47340c MOVQ $0,(%R11,%R8,8) |
(657) 0x473414 LEA 0x2(%RAX),%R8 |
(657) 0x473418 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x47341d MOV (%RDX,%R8,8),%R9 |
(657) 0x473421 MOV %R8,(%RBX,%R9,8) |
(657) 0x473425 MOVQ $0,(%R11,%R8,8) |
(657) 0x47342d LEA 0x3(%RAX),%R8 |
(657) 0x473431 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x473436 MOV (%RDX,%R8,8),%R9 |
(657) 0x47343a MOV %R8,(%RBX,%R9,8) |
(657) 0x47343e MOVQ $0,(%R11,%R8,8) |
(657) 0x473446 LEA 0x4(%RAX),%R8 |
(657) 0x47344a MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x47344f MOV (%RDX,%R8,8),%R9 |
(657) 0x473453 MOV %R8,(%RBX,%R9,8) |
(657) 0x473457 MOVQ $0,(%R11,%R8,8) |
(657) 0x47345f LEA 0x5(%RAX),%R8 |
(657) 0x473463 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x473468 MOV (%RDX,%R8,8),%R9 |
(657) 0x47346c MOV %R8,(%RBX,%R9,8) |
(657) 0x473470 MOVQ $0,(%R11,%R8,8) |
(657) 0x473478 LEA 0x6(%RAX),%R8 |
(657) 0x47347c MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x473481 MOV (%RDX,%R8,8),%R9 |
(657) 0x473485 MOV %R8,(%RBX,%R9,8) |
(657) 0x473489 MOVQ $0,(%R11,%R8,8) |
(657) 0x473491 LEA 0x7(%RAX),%R8 |
(657) 0x473495 ADD $0x8,%RAX |
(657) 0x473499 MOV %R9,-0x8(%R10,%R8,8) |
(657) 0x47349e MOV (%RDX,%R8,8),%R9 |
(657) 0x4734a2 MOV %R8,(%RBX,%R9,8) |
(657) 0x4734a6 MOVQ $0,(%R11,%R8,8) |
(657) 0x4734ae MOV %R9,-0x8(%R10,%RAX,8) |
(657) 0x4734b3 CMP %RAX,%RSI |
(657) 0x4734b6 JNE 4733eb |
(647) 0x4734bc MOV 0x88(%RSP),%RSI |
(647) 0x4734c4 LEA (%RSI,%RCX,1),%R8 |
(647) 0x4734c8 MOV (%RSI,%RDI,8),%RAX |
(647) 0x4734cc MOV (%R8),%RSI |
(647) 0x4734cf CMP %RSI,%RAX |
(647) 0x4734d2 JGE 4734fe |
(647) 0x4734d4 NOPL (%RAX) |
(656) 0x4734d8 MOV 0x140(%RSP),%RDX |
(656) 0x4734e0 MOV 0x150(%RSP),%R9 |
(656) 0x4734e8 MOV (%RDX,%RAX,8),%RDX |
(656) 0x4734ec CMP (%R9,%RDX,8),%R14 |
(656) 0x4734f0 JE 473760 |
(656) 0x4734f6 INC %RAX |
(656) 0x4734f9 CMP %RSI,%RAX |
(656) 0x4734fc JL 4734d8 |
(647) 0x4734fe MOV 0x90(%RSP),%R8 |
(647) 0x473506 ADD %R8,%RCX |
(647) 0x473509 MOV (%R8,%RDI,8),%RAX |
(647) 0x47350d MOV (%RCX),%RSI |
(647) 0x473510 CMP %RSI,%RAX |
(647) 0x473513 JGE 47353e |
(647) 0x473515 NOPL (%RAX) |
(655) 0x473518 MOV 0x148(%RSP),%RDX |
(655) 0x473520 MOV 0x158(%RSP),%R9 |
(655) 0x473528 MOV (%RDX,%RAX,8),%R8 |
(655) 0x47352c CMP (%R9,%R8,8),%R14 |
(655) 0x473530 JE 473740 |
(655) 0x473536 INC %RAX |
(655) 0x473539 CMP %RSI,%RAX |
(655) 0x47353c JL 473518 |
(647) 0x47353e MOV 0x78(%RSP),%RCX |
(647) 0x473543 MOV 0x168(%RSP),%RDX |
(647) 0x47354b MOV (%RCX,%RDI,8),%R8 |
(647) 0x47354f MOV 0x8(%RCX,%RDX,1),%RDX |
(647) 0x473554 LEA 0x1(%R8),%RAX |
(647) 0x473558 CMP %RDX,%RAX |
(647) 0x47355b JGE 47424f |
(647) 0x473561 MOV 0x40(%RSP),%RCX |
(647) 0x473566 MOV 0xe8(%RSP),%R9 |
(647) 0x47356e SAL $0x3,%RAX |
(647) 0x473572 VXORPD %XMM0,%XMM0,%XMM0 |
(647) 0x473576 MOV %R15,0xc0(%RSP) |
(647) 0x47357e VMOVSD %XMM0,%XMM0,%XMM1 |
(647) 0x473582 MOV 0x130(%RSP),%R15 |
(647) 0x47358a LEA (%RCX,%RAX,1),%RSI |
(647) 0x47358e MOV %R8,0xb8(%RSP) |
(647) 0x473596 ADD %R9,%RAX |
(647) 0x473599 LEA (%RCX,%RDX,8),%R9 |
(647) 0x47359d MOV %R14,0xb0(%RSP) |
(647) 0x4735a5 JMP 4735d7 |
0x4735a7 NOPW (%RAX,%RAX,1) |
(652) 0x4735b0 MOV 0x120(%RSP),%R8 |
(652) 0x4735b8 MOV 0x168(%RSP),%R14 |
(652) 0x4735c0 MOV (%R8,%RCX,8),%RCX |
(652) 0x4735c4 CMP %RCX,(%R8,%R14,1) |
(652) 0x4735c8 JE 47360e |
(652) 0x4735ca ADD $0x8,%RSI |
(652) 0x4735ce ADD $0x8,%RAX |
(652) 0x4735d2 CMP %RSI,%R9 |
(652) 0x4735d5 JE 47361f |
(652) 0x4735d7 MOV (%RSI),%RCX |
(652) 0x4735da MOV 0x170(%RSP),%R14 |
(652) 0x4735e2 LEA (,%RCX,8),%R8 |
(652) 0x4735ea CMP (%R14,%RCX,8),%RDI |
(652) 0x4735ee JE 473780 |
(652) 0x4735f4 MOV 0x128(%RSP),%RDX |
(652) 0x4735fc CMPQ $-0x3,(%RDX,%RCX,8) |
(652) 0x473601 JE 4735ca |
(652) 0x473603 CMPQ $0x1,0x160(%RSP) |
(652) 0x47360c JNE 4735b0 |
(652) 0x47360e ADD $0x8,%RSI |
(652) 0x473612 VADDSD (%RAX),%XMM0,%XMM0 |
(652) 0x473616 ADD $0x8,%RAX |
(652) 0x47361a CMP %RSI,%R9 |
(652) 0x47361d JNE 4735d7 |
(647) 0x47361f MOV 0xc0(%RSP),%R15 |
(647) 0x473627 MOV 0xb8(%RSP),%R8 |
(647) 0x47362f MOV 0xb0(%RSP),%R14 |
(647) 0x473637 MOV 0x80(%RSP),%RCX |
(647) 0x47363f MOV 0x168(%RSP),%RAX |
(647) 0x473647 MOV (%RCX,%RDI,8),%RDX |
(647) 0x47364b MOV 0x8(%RCX,%RAX,1),%RCX |
(647) 0x473650 CMP %RCX,%RDX |
(647) 0x473653 JGE 473ab3 |
(647) 0x473659 MOV 0x50(%RSP),%RSI |
(647) 0x47365e SAL $0x3,%RDX |
(647) 0x473662 MOV 0x48(%RSP),%R9 |
(647) 0x473667 MOV %R13,0xb8(%RSP) |
(647) 0x47366f MOV %R10,0xc0(%RSP) |
(647) 0x473677 MOV 0x58(%RSP),%R13 |
(647) 0x47367c LEA (%RSI,%RDX,1),%RAX |
(647) 0x473680 MOV %R14,0xb0(%RSP) |
(647) 0x473688 ADD %R9,%RDX |
(647) 0x47368b LEA (%RSI,%RCX,8),%RSI |
(647) 0x47368f MOV %RAX,0x178(%RSP) |
(647) 0x473697 MOV %R8,%RAX |
(647) 0x47369a JMP 4736e0 |
0x47369c NOPL (%RAX) |
(650) 0x4736a0 MOV 0x120(%RSP),%R10 |
(650) 0x4736a8 MOV 0x168(%RSP),%R14 |
(650) 0x4736b0 MOV 0x108(%RSP),%RCX |
(650) 0x4736b8 MOV (%R10,%R14,1),%R9 |
(650) 0x4736bc CMP %R9,(%RCX,%R8,1) |
(650) 0x4736c0 JE 473732 |
(650) 0x4736c2 ADDQ $0x8,0x178(%RSP) |
(650) 0x4736cb ADD $0x8,%RDX |
(650) 0x4736cf MOV 0x178(%RSP),%RCX |
(650) 0x4736d7 CMP %RSI,%RCX |
(650) 0x4736da JE 473a98 |
(650) 0x4736e0 MOV 0x178(%RSP),%R10 |
(650) 0x4736e8 MOV (%R10),%RCX |
(650) 0x4736eb TEST %R15,%R15 |
(650) 0x4736ee JE 4736fc |
(650) 0x4736f0 MOV 0x118(%RSP),%R14 |
(650) 0x4736f8 MOV (%R14,%RCX,8),%RCX |
(650) 0x4736fc LEA (,%RCX,8),%R8 |
(650) 0x473704 TEST %RCX,%RCX |
(650) 0x473707 JS 47371b |
(650) 0x473709 MOV 0x138(%RSP),%R9 |
(650) 0x473711 CMP (%R9,%RCX,8),%RDI |
(650) 0x473715 JE 473f38 |
(650) 0x47371b CMPQ $-0x3,(%R13,%R8,1) |
(650) 0x473721 JE 4736c2 |
(650) 0x473723 CMPQ $0x1,0x160(%RSP) |
(650) 0x47372c JNE 4736a0 |
(650) 0x473732 VADDSD (%RDX),%XMM0,%XMM0 |
(650) 0x473736 JMP 4736c2 |
0x473738 NOPL (%RAX,%RAX,1) |
(655) 0x473740 MOV 0x138(%RSP),%RSI |
(655) 0x473748 INC %RAX |
(655) 0x47374b MOV %RDI,(%RSI,%R8,8) |
(655) 0x47374f MOV (%RCX),%RSI |
(655) 0x473752 CMP %RAX,%RSI |
(655) 0x473755 JG 473518 |
(647) 0x47375b JMP 47353e |
(656) 0x473760 MOV 0x170(%RSP),%RSI |
(656) 0x473768 INC %RAX |
(656) 0x47376b MOV %RDI,(%RSI,%RDX,8) |
(656) 0x47376f MOV (%R8),%RSI |
(656) 0x473772 CMP %RAX,%RSI |
(656) 0x473775 JG 4734d8 |
(647) 0x47377b JMP 4734fe |
(652) 0x473780 MOV 0xf0(%RSP),%R14 |
(652) 0x473788 MOV (%R14,%RCX,8),%RDX |
(652) 0x47378c MOV 0x8(%R14,%R8,1),%R14 |
(652) 0x473791 MOV %R14,0x178(%RSP) |
(652) 0x473799 CMP %R14,%RDX |
(652) 0x47379c JGE 473918 |
(652) 0x4737a2 SUB %RDX,%R14 |
(652) 0x4737a5 AND $0x3,%R14D |
(652) 0x4737a9 JE 473854 |
(652) 0x4737af CMP $0x1,%R14 |
(652) 0x4737b3 JE 473815 |
(652) 0x4737b5 CMP $0x2,%R14 |
(652) 0x4737b9 JE 4737e7 |
(652) 0x4737bb VMOVSD (%RAX),%XMM5 |
(652) 0x4737bf MOV (%R13,%RDX,8),%R14 |
(652) 0x4737c4 VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
(652) 0x4737ca MOV (%R15,%R14,8),%R14 |
(652) 0x4737ce INC %RDX |
(652) 0x4737d1 LEA (%R12,%R14,8),%R14 |
(652) 0x4737d5 VADDSD (%R14),%XMM6,%XMM7 |
(652) 0x4737da VADDSD %XMM6,%XMM1,%XMM1 |
(652) 0x4737de VADDSD %XMM6,%XMM0,%XMM0 |
(652) 0x4737e2 VMOVSD %XMM7,(%R14) |
(652) 0x4737e7 VMOVSD (%RAX),%XMM8 |
(652) 0x4737eb MOV (%R13,%RDX,8),%R14 |
(652) 0x4737f0 VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
(652) 0x4737f6 MOV (%R15,%R14,8),%R14 |
(652) 0x4737fa INC %RDX |
(652) 0x4737fd LEA (%R12,%R14,8),%R14 |
(652) 0x473801 VADDSD (%R14),%XMM9,%XMM10 |
(652) 0x473806 VADDSD %XMM9,%XMM1,%XMM1 |
(652) 0x47380b VADDSD %XMM9,%XMM0,%XMM0 |
(652) 0x473810 VMOVSD %XMM10,(%R14) |
(652) 0x473815 VMOVSD (%RAX),%XMM11 |
(652) 0x473819 MOV (%R13,%RDX,8),%R14 |
(652) 0x47381e VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
(652) 0x473824 MOV (%R15,%R14,8),%R14 |
(652) 0x473828 INC %RDX |
(652) 0x47382b LEA (%R12,%R14,8),%R14 |
(652) 0x47382f VADDSD (%R14),%XMM12,%XMM13 |
(652) 0x473834 VADDSD %XMM12,%XMM1,%XMM1 |
(652) 0x473839 VADDSD %XMM12,%XMM0,%XMM0 |
(652) 0x47383e VMOVSD %XMM13,(%R14) |
(652) 0x473843 MOV 0x178(%RSP),%R14 |
(652) 0x47384b CMP %R14,%RDX |
(652) 0x47384e JE 473918 |
(654) 0x473854 VMOVSD (%RAX),%XMM14 |
(654) 0x473858 MOV (%R13,%RDX,8),%R14 |
(654) 0x47385d VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(654) 0x473863 MOV (%R15,%R14,8),%R14 |
(654) 0x473867 LEA (%R12,%R14,8),%R14 |
(654) 0x47386b VADDSD (%R14),%XMM15,%XMM2 |
(654) 0x473870 VADDSD %XMM15,%XMM1,%XMM6 |
(654) 0x473875 VADDSD %XMM15,%XMM0,%XMM7 |
(654) 0x47387a VMOVSD %XMM2,(%R14) |
(654) 0x47387f MOV 0x8(%R13,%RDX,8),%R14 |
(654) 0x473884 VMOVSD (%RAX),%XMM5 |
(654) 0x473888 MOV (%R15,%R14,8),%R14 |
(654) 0x47388c VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(654) 0x473893 LEA (%R12,%R14,8),%R14 |
(654) 0x473897 VADDSD (%R14),%XMM8,%XMM9 |
(654) 0x47389c VADDSD %XMM8,%XMM6,%XMM10 |
(654) 0x4738a1 VADDSD %XMM8,%XMM7,%XMM11 |
(654) 0x4738a6 VMOVSD %XMM9,(%R14) |
(654) 0x4738ab MOV 0x10(%R13,%RDX,8),%R14 |
(654) 0x4738b0 VMOVSD (%RAX),%XMM12 |
(654) 0x4738b4 MOV (%R15,%R14,8),%R14 |
(654) 0x4738b8 VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(654) 0x4738bf LEA (%R12,%R14,8),%R14 |
(654) 0x4738c3 VADDSD (%R14),%XMM13,%XMM1 |
(654) 0x4738c8 VADDSD %XMM13,%XMM10,%XMM14 |
(654) 0x4738cd VADDSD %XMM13,%XMM11,%XMM0 |
(654) 0x4738d2 VMOVSD %XMM1,(%R14) |
(654) 0x4738d7 MOV 0x18(%R13,%RDX,8),%R14 |
(654) 0x4738dc VMOVSD (%RAX),%XMM15 |
(654) 0x4738e0 MOV (%R15,%R14,8),%R14 |
(654) 0x4738e4 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(654) 0x4738eb ADD $0x4,%RDX |
(654) 0x4738ef LEA (%R12,%R14,8),%R14 |
(654) 0x4738f3 VADDSD (%R14),%XMM12,%XMM2 |
(654) 0x4738f8 VADDSD %XMM12,%XMM14,%XMM1 |
(654) 0x4738fd VADDSD %XMM12,%XMM0,%XMM0 |
(654) 0x473902 VMOVSD %XMM2,(%R14) |
(654) 0x473907 MOV 0x178(%RSP),%R14 |
(654) 0x47390f CMP %R14,%RDX |
(654) 0x473912 JNE 473854 |
(652) 0x473918 MOV 0xf8(%RSP),%R14 |
(652) 0x473920 MOV (%R14,%RCX,8),%RDX |
(652) 0x473924 MOV 0x8(%R14,%R8,1),%R8 |
(652) 0x473929 CMP %R8,%RDX |
(652) 0x47392c JGE 4735ca |
(652) 0x473932 MOV %R8,%RCX |
(652) 0x473935 SUB %RDX,%RCX |
(652) 0x473938 AND $0x3,%ECX |
(652) 0x47393b JE 4739d9 |
(652) 0x473941 CMP $0x1,%RCX |
(652) 0x473945 JE 4739a3 |
(652) 0x473947 CMP $0x2,%RCX |
(652) 0x47394b JE 473978 |
(652) 0x47394d VMOVSD (%RAX),%XMM6 |
(652) 0x473951 MOV (%R10,%RDX,8),%R14 |
(652) 0x473955 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
(652) 0x47395b MOV (%RBX,%R14,8),%RCX |
(652) 0x47395f INC %RDX |
(652) 0x473962 LEA (%R11,%RCX,8),%R14 |
(652) 0x473966 VADDSD (%R14),%XMM7,%XMM5 |
(652) 0x47396b VADDSD %XMM7,%XMM1,%XMM1 |
(652) 0x47396f VADDSD %XMM7,%XMM0,%XMM0 |
(652) 0x473973 VMOVSD %XMM5,(%R14) |
(652) 0x473978 VMOVSD (%RAX),%XMM8 |
(652) 0x47397c MOV (%R10,%RDX,8),%RCX |
(652) 0x473980 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
(652) 0x473986 MOV (%RBX,%RCX,8),%R14 |
(652) 0x47398a INC %RDX |
(652) 0x47398d LEA (%R11,%R14,8),%RCX |
(652) 0x473991 VADDSD (%RCX),%XMM9,%XMM10 |
(652) 0x473995 VADDSD %XMM9,%XMM1,%XMM1 |
(652) 0x47399a VADDSD %XMM9,%XMM0,%XMM0 |
(652) 0x47399f VMOVSD %XMM10,(%RCX) |
(652) 0x4739a3 VMOVSD (%RAX),%XMM11 |
(652) 0x4739a7 MOV (%R10,%RDX,8),%R14 |
(652) 0x4739ab VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
(652) 0x4739b1 MOV (%RBX,%R14,8),%RCX |
(652) 0x4739b5 INC %RDX |
(652) 0x4739b8 LEA (%R11,%RCX,8),%R14 |
(652) 0x4739bc VADDSD (%R14),%XMM12,%XMM13 |
(652) 0x4739c1 VADDSD %XMM12,%XMM1,%XMM1 |
(652) 0x4739c6 VADDSD %XMM12,%XMM0,%XMM0 |
(652) 0x4739cb VMOVSD %XMM13,(%R14) |
(652) 0x4739d0 CMP %R8,%RDX |
(652) 0x4739d3 JE 4735ca |
(653) 0x4739d9 VMOVSD (%RAX),%XMM12 |
(653) 0x4739dd MOV (%R10,%RDX,8),%RCX |
(653) 0x4739e1 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(653) 0x4739e7 MOV (%RBX,%RCX,8),%R14 |
(653) 0x4739eb LEA (%R11,%R14,8),%RCX |
(653) 0x4739ef MOV 0x8(%R10,%RDX,8),%R14 |
(653) 0x4739f4 VADDSD (%RCX),%XMM14,%XMM15 |
(653) 0x4739f8 VADDSD %XMM14,%XMM1,%XMM1 |
(653) 0x4739fd VADDSD %XMM14,%XMM0,%XMM0 |
(653) 0x473a02 VMOVSD %XMM15,(%RCX) |
(653) 0x473a06 MOV (%RBX,%R14,8),%RCX |
(653) 0x473a0a VMOVSD (%RAX),%XMM2 |
(653) 0x473a0e LEA (%R11,%RCX,8),%R14 |
(653) 0x473a12 MOV 0x10(%R10,%RDX,8),%RCX |
(653) 0x473a17 VMULSD 0x8(%R11,%RDX,8),%XMM2,%XMM6 |
(653) 0x473a1e VADDSD (%R14),%XMM6,%XMM7 |
(653) 0x473a23 VADDSD %XMM6,%XMM1,%XMM8 |
(653) 0x473a27 VADDSD %XMM6,%XMM0,%XMM9 |
(653) 0x473a2b VMOVSD %XMM7,(%R14) |
(653) 0x473a30 MOV (%RBX,%RCX,8),%R14 |
(653) 0x473a34 VMOVSD (%RAX),%XMM5 |
(653) 0x473a38 LEA (%R11,%R14,8),%RCX |
(653) 0x473a3c MOV 0x18(%R10,%RDX,8),%R14 |
(653) 0x473a41 VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(653) 0x473a48 VADDSD (%RCX),%XMM10,%XMM11 |
(653) 0x473a4c VADDSD %XMM10,%XMM8,%XMM13 |
(653) 0x473a51 VADDSD %XMM10,%XMM9,%XMM14 |
(653) 0x473a56 VMOVSD %XMM11,(%RCX) |
(653) 0x473a5a MOV (%RBX,%R14,8),%RCX |
(653) 0x473a5e VMOVSD (%RAX),%XMM12 |
(653) 0x473a62 LEA (%R11,%RCX,8),%R14 |
(653) 0x473a66 VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(653) 0x473a6d ADD $0x4,%RDX |
(653) 0x473a71 VADDSD (%R14),%XMM12,%XMM15 |
(653) 0x473a76 VADDSD %XMM12,%XMM13,%XMM1 |
(653) 0x473a7b VADDSD %XMM12,%XMM14,%XMM0 |
(653) 0x473a80 VMOVSD %XMM15,(%R14) |
(653) 0x473a85 CMP %R8,%RDX |
(653) 0x473a88 JNE 4739d9 |
(652) 0x473a8e JMP 4735ca |
0x473a93 NOPL (%RAX,%RAX,1) |
(647) 0x473a98 MOV 0xc0(%RSP),%R10 |
(647) 0x473aa0 MOV 0xb8(%RSP),%R13 |
(647) 0x473aa8 MOV %RAX,%R8 |
(647) 0x473aab MOV 0xb0(%RSP),%R14 |
(647) 0x473ab3 MOV 0xe8(%RSP),%RDI |
(647) 0x473abb VMULSD (%RDI,%R8,8),%XMM1,%XMM9 |
(647) 0x473ac1 VCOMISD %XMM3,%XMM9 |
(647) 0x473ac5 JE 473ad0 |
(647) 0x473ac7 VXORPD %XMM4,%XMM0,%XMM10 |
(647) 0x473acb VDIVSD %XMM9,%XMM10,%XMM12 |
(647) 0x473ad0 MOV 0xd8(%RSP),%R8 |
(647) 0x473ad8 MOV 0xe0(%RSP),%R9 |
(647) 0x473ae0 MOV (%R8),%RCX |
(647) 0x473ae3 MOV (%R9),%RDI |
(647) 0x473ae6 CMP %RDI,%RCX |
(647) 0x473ae9 JGE 473cd1 |
(647) 0x473aef MOV %RDI,%RSI |
(647) 0x473af2 MOV %RCX,%R8 |
(647) 0x473af5 SUB %RCX,%RSI |
(647) 0x473af8 LEA -0x1(%RSI),%RAX |
(647) 0x473afc CMP $0x6,%RAX |
(647) 0x473b00 JBE 474264 |
(647) 0x473b06 MOV %RSI,%RDX |
(647) 0x473b09 LEA (%R12,%RCX,8),%RAX |
(647) 0x473b0d VBROADCASTSD %XMM12,%ZMM5 |
(647) 0x473b13 SHR $0x3,%RDX |
(647) 0x473b17 SAL $0x6,%RDX |
(647) 0x473b1b LEA (%RDX,%RAX,1),%R9 |
(647) 0x473b1f SUB $0x40,%RDX |
(647) 0x473b23 SHR $0x6,%RDX |
(647) 0x473b27 INC %RDX |
(647) 0x473b2a AND $0x7,%EDX |
(647) 0x473b2d JE 473bd7 |
(647) 0x473b33 CMP $0x1,%RDX |
(647) 0x473b37 JE 473bc1 |
(647) 0x473b3d CMP $0x2,%RDX |
(647) 0x473b41 JE 473bb0 |
(647) 0x473b43 CMP $0x3,%RDX |
(647) 0x473b47 JE 473b9f |
(647) 0x473b49 CMP $0x4,%RDX |
(647) 0x473b4d JE 473b8e |
(647) 0x473b4f CMP $0x5,%RDX |
(647) 0x473b53 JE 473b7d |
(647) 0x473b55 CMP $0x6,%RDX |
(647) 0x473b59 JE 473b6c |
(647) 0x473b5b VMULPD (%RAX),%ZMM5,%ZMM11 |
(647) 0x473b61 ADD $0x40,%RAX |
(647) 0x473b65 VMOVUPD %ZMM11,-0x40(%RAX) |
(647) 0x473b6c VMULPD (%RAX),%ZMM5,%ZMM13 |
(647) 0x473b72 ADD $0x40,%RAX |
(647) 0x473b76 VMOVUPD %ZMM13,-0x40(%RAX) |
(647) 0x473b7d VMULPD (%RAX),%ZMM5,%ZMM14 |
(647) 0x473b83 ADD $0x40,%RAX |
(647) 0x473b87 VMOVUPD %ZMM14,-0x40(%RAX) |
(647) 0x473b8e VMULPD (%RAX),%ZMM5,%ZMM15 |
(647) 0x473b94 ADD $0x40,%RAX |
(647) 0x473b98 VMOVUPD %ZMM15,-0x40(%RAX) |
(647) 0x473b9f VMULPD (%RAX),%ZMM5,%ZMM2 |
(647) 0x473ba5 ADD $0x40,%RAX |
(647) 0x473ba9 VMOVUPD %ZMM2,-0x40(%RAX) |
(647) 0x473bb0 VMULPD (%RAX),%ZMM5,%ZMM6 |
(647) 0x473bb6 ADD $0x40,%RAX |
(647) 0x473bba VMOVUPD %ZMM6,-0x40(%RAX) |
(647) 0x473bc1 VMULPD (%RAX),%ZMM5,%ZMM7 |
(647) 0x473bc7 ADD $0x40,%RAX |
(647) 0x473bcb VMOVUPD %ZMM7,-0x40(%RAX) |
(647) 0x473bd2 CMP %R9,%RAX |
(647) 0x473bd5 JE 473c51 |
(649) 0x473bd7 VMULPD (%RAX),%ZMM5,%ZMM1 |
(649) 0x473bdd ADD $0x200,%RAX |
(649) 0x473be3 VMULPD -0x1c0(%RAX),%ZMM5,%ZMM0 |
(649) 0x473bea VMULPD -0x180(%RAX),%ZMM5,%ZMM8 |
(649) 0x473bf1 VMULPD -0x140(%RAX),%ZMM5,%ZMM9 |
(649) 0x473bf8 VMULPD -0x100(%RAX),%ZMM5,%ZMM10 |
(649) 0x473bff VMULPD -0xc0(%RAX),%ZMM5,%ZMM11 |
(649) 0x473c06 VMOVUPD %ZMM1,-0x200(%RAX) |
(649) 0x473c0d VMULPD -0x80(%RAX),%ZMM5,%ZMM13 |
(649) 0x473c14 VMOVUPD %ZMM0,-0x1c0(%RAX) |
(649) 0x473c1b VMULPD -0x40(%RAX),%ZMM5,%ZMM14 |
(649) 0x473c22 VMOVUPD %ZMM8,-0x180(%RAX) |
(649) 0x473c29 VMOVUPD %ZMM9,-0x140(%RAX) |
(649) 0x473c30 VMOVUPD %ZMM10,-0x100(%RAX) |
(649) 0x473c37 VMOVUPD %ZMM11,-0xc0(%RAX) |
(649) 0x473c3e VMOVUPD %ZMM13,-0x80(%RAX) |
(649) 0x473c45 VMOVUPD %ZMM14,-0x40(%RAX) |
(649) 0x473c4c CMP %R9,%RAX |
(649) 0x473c4f JNE 473bd7 |
(647) 0x473c51 MOV %RSI,%R9 |
(647) 0x473c54 AND $-0x8,%R9 |
(647) 0x473c58 ADD %R9,%RCX |
(647) 0x473c5b TEST $0x7,%SIL |
(647) 0x473c5f JE 473cd1 |
(647) 0x473c61 SUB %R9,%RSI |
(647) 0x473c64 LEA -0x1(%RSI),%RAX |
(647) 0x473c68 CMP $0x2,%RAX |
(647) 0x473c6c JBE 473c91 |
(647) 0x473c6e ADD %R8,%R9 |
(647) 0x473c71 VBROADCASTSD %XMM12,%YMM5 |
(647) 0x473c76 LEA (%R12,%R9,8),%R8 |
(647) 0x473c7a VMULPD (%R8),%YMM5,%YMM15 |
(647) 0x473c7f VMOVUPD %YMM15,(%R8) |
(647) 0x473c84 TEST $0x3,%SIL |
(647) 0x473c88 JE 473cd1 |
(647) 0x473c8a AND $-0x4,%RSI |
(647) 0x473c8e ADD %RSI,%RCX |
(647) 0x473c91 LEA (,%RCX,8),%RSI |
(647) 0x473c99 LEA 0x1(%RCX),%R9 |
(647) 0x473c9d LEA (%R12,%RSI,1),%RDX |
(647) 0x473ca1 VMULSD (%RDX),%XMM12,%XMM2 |
(647) 0x473ca5 VMOVSD %XMM2,(%RDX) |
(647) 0x473ca9 CMP %RDI,%R9 |
(647) 0x473cac JGE 473cd1 |
(647) 0x473cae LEA 0x8(%R12,%RSI,1),%RAX |
(647) 0x473cb3 ADD $0x2,%RCX |
(647) 0x473cb7 VMULSD (%RAX),%XMM12,%XMM6 |
(647) 0x473cbb VMOVSD %XMM6,(%RAX) |
(647) 0x473cbf CMP %RCX,%RDI |
(647) 0x473cc2 JLE 473cd1 |
(647) 0x473cc4 LEA 0x10(%R12,%RSI,1),%RCX |
(647) 0x473cc9 VMULSD (%RCX),%XMM12,%XMM7 |
(647) 0x473ccd VMOVSD %XMM7,(%RCX) |
(647) 0x473cd1 MOV 0xc8(%RSP),%RDI |
(647) 0x473cd9 MOV 0xd0(%RSP),%R8 |
(647) 0x473ce1 MOV (%RDI),%RCX |
(647) 0x473ce4 MOV (%R8),%RDI |
(647) 0x473ce7 CMP %RCX,%RDI |
(647) 0x473cea JLE 473ed2 |
(647) 0x473cf0 MOV %RDI,%RSI |
(647) 0x473cf3 MOV %RCX,%R8 |
(647) 0x473cf6 SUB %RCX,%RSI |
(647) 0x473cf9 LEA -0x1(%RSI),%RDX |
(647) 0x473cfd CMP $0x6,%RDX |
(647) 0x473d01 JBE 47425c |
(647) 0x473d07 MOV %RSI,%RDX |
(647) 0x473d0a LEA (%R11,%RCX,8),%RAX |
(647) 0x473d0e VBROADCASTSD %XMM12,%ZMM0 |
(647) 0x473d14 SHR $0x3,%RDX |
(647) 0x473d18 SAL $0x6,%RDX |
(647) 0x473d1c LEA (%RDX,%RAX,1),%R9 |
(647) 0x473d20 SUB $0x40,%RDX |
(647) 0x473d24 SHR $0x6,%RDX |
(647) 0x473d28 INC %RDX |
(647) 0x473d2b AND $0x7,%EDX |
(647) 0x473d2e JE 473dd8 |
(647) 0x473d34 CMP $0x1,%RDX |
(647) 0x473d38 JE 473dc2 |
(647) 0x473d3e CMP $0x2,%RDX |
(647) 0x473d42 JE 473db1 |
(647) 0x473d44 CMP $0x3,%RDX |
(647) 0x473d48 JE 473da0 |
(647) 0x473d4a CMP $0x4,%RDX |
(647) 0x473d4e JE 473d8f |
(647) 0x473d50 CMP $0x5,%RDX |
(647) 0x473d54 JE 473d7e |
(647) 0x473d56 CMP $0x6,%RDX |
(647) 0x473d5a JE 473d6d |
(647) 0x473d5c VMULPD (%RAX),%ZMM0,%ZMM1 |
(647) 0x473d62 ADD $0x40,%RAX |
(647) 0x473d66 VMOVUPD %ZMM1,-0x40(%RAX) |
(647) 0x473d6d VMULPD (%RAX),%ZMM0,%ZMM8 |
(647) 0x473d73 ADD $0x40,%RAX |
(647) 0x473d77 VMOVUPD %ZMM8,-0x40(%RAX) |
(647) 0x473d7e VMULPD (%RAX),%ZMM0,%ZMM9 |
(647) 0x473d84 ADD $0x40,%RAX |
(647) 0x473d88 VMOVUPD %ZMM9,-0x40(%RAX) |
(647) 0x473d8f VMULPD (%RAX),%ZMM0,%ZMM10 |
(647) 0x473d95 ADD $0x40,%RAX |
(647) 0x473d99 VMOVUPD %ZMM10,-0x40(%RAX) |
(647) 0x473da0 VMULPD (%RAX),%ZMM0,%ZMM11 |
(647) 0x473da6 ADD $0x40,%RAX |
(647) 0x473daa VMOVUPD %ZMM11,-0x40(%RAX) |
(647) 0x473db1 VMULPD (%RAX),%ZMM0,%ZMM13 |
(647) 0x473db7 ADD $0x40,%RAX |
(647) 0x473dbb VMOVUPD %ZMM13,-0x40(%RAX) |
(647) 0x473dc2 VMULPD (%RAX),%ZMM0,%ZMM14 |
(647) 0x473dc8 ADD $0x40,%RAX |
(647) 0x473dcc VMOVUPD %ZMM14,-0x40(%RAX) |
(647) 0x473dd3 CMP %RAX,%R9 |
(647) 0x473dd6 JE 473e52 |
(648) 0x473dd8 VMULPD (%RAX),%ZMM0,%ZMM5 |
(648) 0x473dde ADD $0x200,%RAX |
(648) 0x473de4 VMULPD -0x1c0(%RAX),%ZMM0,%ZMM15 |
(648) 0x473deb VMULPD -0x180(%RAX),%ZMM0,%ZMM2 |
(648) 0x473df2 VMULPD -0x140(%RAX),%ZMM0,%ZMM6 |
(648) 0x473df9 VMULPD -0x100(%RAX),%ZMM0,%ZMM7 |
(648) 0x473e00 VMULPD -0xc0(%RAX),%ZMM0,%ZMM1 |
(648) 0x473e07 VMOVUPD %ZMM5,-0x200(%RAX) |
(648) 0x473e0e VMULPD -0x80(%RAX),%ZMM0,%ZMM8 |
(648) 0x473e15 VMOVUPD %ZMM15,-0x1c0(%RAX) |
(648) 0x473e1c VMULPD -0x40(%RAX),%ZMM0,%ZMM9 |
(648) 0x473e23 VMOVUPD %ZMM2,-0x180(%RAX) |
(648) 0x473e2a VMOVUPD %ZMM6,-0x140(%RAX) |
(648) 0x473e31 VMOVUPD %ZMM7,-0x100(%RAX) |
(648) 0x473e38 VMOVUPD %ZMM1,-0xc0(%RAX) |
(648) 0x473e3f VMOVUPD %ZMM8,-0x80(%RAX) |
(648) 0x473e46 VMOVUPD %ZMM9,-0x40(%RAX) |
(648) 0x473e4d CMP %RAX,%R9 |
(648) 0x473e50 JNE 473dd8 |
(647) 0x473e52 MOV %RSI,%R9 |
(647) 0x473e55 AND $-0x8,%R9 |
(647) 0x473e59 ADD %R9,%RCX |
(647) 0x473e5c TEST $0x7,%SIL |
(647) 0x473e60 JE 473ed2 |
(647) 0x473e62 SUB %R9,%RSI |
(647) 0x473e65 LEA -0x1(%RSI),%RAX |
(647) 0x473e69 CMP $0x2,%RAX |
(647) 0x473e6d JBE 473e92 |
(647) 0x473e6f ADD %R8,%R9 |
(647) 0x473e72 VBROADCASTSD %XMM12,%YMM0 |
(647) 0x473e77 LEA (%R11,%R9,8),%R8 |
(647) 0x473e7b VMULPD (%R8),%YMM0,%YMM10 |
(647) 0x473e80 VMOVUPD %YMM10,(%R8) |
(647) 0x473e85 TEST $0x3,%SIL |
(647) 0x473e89 JE 473ed2 |
(647) 0x473e8b AND $-0x4,%RSI |
(647) 0x473e8f ADD %RSI,%RCX |
(647) 0x473e92 LEA (,%RCX,8),%RSI |
(647) 0x473e9a LEA 0x1(%RCX),%R9 |
(647) 0x473e9e LEA (%R11,%RSI,1),%RDX |
(647) 0x473ea2 VMULSD (%RDX),%XMM12,%XMM11 |
(647) 0x473ea6 VMOVSD %XMM11,(%RDX) |
(647) 0x473eaa CMP %R9,%RDI |
(647) 0x473ead JLE 473ed2 |
(647) 0x473eaf LEA 0x8(%R11,%RSI,1),%RAX |
(647) 0x473eb4 ADD $0x2,%RCX |
(647) 0x473eb8 VMULSD (%RAX),%XMM12,%XMM13 |
(647) 0x473ebc VMOVSD %XMM13,(%RAX) |
(647) 0x473ec0 CMP %RCX,%RDI |
(647) 0x473ec3 JLE 473ed2 |
(647) 0x473ec5 LEA 0x10(%R11,%RSI,1),%RCX |
(647) 0x473eca VMULSD (%RCX),%XMM12,%XMM14 |
(647) 0x473ece VMOVSD %XMM14,(%RCX) |
(647) 0x473ed2 ADDQ $0x8,0x110(%RSP) |
(647) 0x473edb MOV 0x70(%RSP),%RDI |
(647) 0x473ee0 MOV 0x110(%RSP),%R8 |
(647) 0x473ee8 CMP %RDI,%R8 |
(647) 0x473eeb JNE 473008 |
0x473ef1 MOV 0x130(%RSP),%R15 |
0x473ef9 VZEROUPPER |
0x473efc MOV 0x170(%RSP),%RDI |
0x473f04 CALL 5b0950 <hypre_Free> |
0x473f09 MOV 0x138(%RSP),%RDI |
0x473f11 CALL 5b0950 <hypre_Free> |
0x473f16 MOV %R15,%RDI |
0x473f19 CALL 5b0950 <hypre_Free> |
0x473f1e LEA -0x28(%RBP),%RSP |
0x473f22 MOV %RBX,%RDI |
0x473f25 POP %RBX |
0x473f26 POP %R12 |
0x473f28 POP %R13 |
0x473f2a POP %R14 |
0x473f2c POP %R15 |
0x473f2e POP %RBP |
0x473f2f JMP 5b0950 |
0x473f34 NOPL (%RAX) |
(650) 0x473f38 MOV 0x30(%RSP),%RCX |
(650) 0x473f3d MOV 0x38(%RSP),%R10 |
(650) 0x473f42 MOV (%RCX,%R8,1),%RCX |
(650) 0x473f46 MOV 0x8(%R10,%R8,1),%R10 |
(650) 0x473f4b ADD %RCX,%R10 |
(650) 0x473f4e CMP %R10,%RCX |
(650) 0x473f51 JGE 4736c2 |
(650) 0x473f57 MOV 0x28(%RSP),%R8 |
(650) 0x473f5c MOV 0x100(%RSP),%R14 |
(650) 0x473f64 MOV %R10,%R9 |
(650) 0x473f67 SUB %RCX,%R9 |
(650) 0x473f6a MOV (%R8,%R14,1),%R8 |
(650) 0x473f6e AND $0x3,%R9D |
(650) 0x473f72 JE 474049 |
(650) 0x473f78 CMP $0x1,%R9 |
(650) 0x473f7c JE 474002 |
(650) 0x473f82 CMP $0x2,%R9 |
(650) 0x473f86 JE 473fc4 |
(650) 0x473f88 VMOVSD (%RDX),%XMM2 |
(650) 0x473f8c MOV 0xa8(%RSP),%R14 |
(650) 0x473f94 MOV (%R8,%RCX,8),%R9 |
(650) 0x473f98 VMULSD (%R14,%RCX,8),%XMM2,%XMM6 |
(650) 0x473f9e TEST %R9,%R9 |
(650) 0x473fa1 JS 47426c |
(650) 0x473fa7 MOV (%RBX,%R9,8),%R9 |
(650) 0x473fab LEA (%R11,%R9,8),%R14 |
(650) 0x473faf VADDSD (%R14),%XMM6,%XMM7 |
(650) 0x473fb4 VMOVSD %XMM7,(%R14) |
(650) 0x473fb9 VADDSD %XMM6,%XMM1,%XMM1 |
(650) 0x473fbd VADDSD %XMM6,%XMM0,%XMM0 |
(650) 0x473fc1 INC %RCX |
(650) 0x473fc4 VMOVSD (%RDX),%XMM9 |
(650) 0x473fc8 MOV 0xa8(%RSP),%R14 |
(650) 0x473fd0 MOV (%R8,%RCX,8),%R9 |
(650) 0x473fd4 VMULSD (%R14,%RCX,8),%XMM9,%XMM10 |
(650) 0x473fda TEST %R9,%R9 |
(650) 0x473fdd JS 474218 |
(650) 0x473fe3 MOV (%RBX,%R9,8),%R9 |
(650) 0x473fe7 LEA (%R11,%R9,8),%R14 |
(650) 0x473feb VADDSD (%R14),%XMM10,%XMM5 |
(650) 0x473ff0 VMOVSD %XMM5,(%R14) |
(650) 0x473ff5 VADDSD %XMM10,%XMM1,%XMM1 |
(650) 0x473ffa VADDSD %XMM10,%XMM0,%XMM0 |
(650) 0x473fff INC %RCX |
(650) 0x474002 VMOVSD (%RDX),%XMM13 |
(650) 0x474006 MOV 0xa8(%RSP),%R14 |
(650) 0x47400e MOV (%R8,%RCX,8),%R9 |
(650) 0x474012 VMULSD (%R14,%RCX,8),%XMM13,%XMM12 |
(650) 0x474018 TEST %R9,%R9 |
(650) 0x47401b JS 4741e0 |
(650) 0x474021 MOV (%RBX,%R9,8),%R9 |
(650) 0x474025 LEA (%R11,%R9,8),%R14 |
(650) 0x474029 VADDSD (%R14),%XMM12,%XMM14 |
(650) 0x47402e VMOVSD %XMM14,(%R14) |
(650) 0x474033 INC %RCX |
(650) 0x474036 VADDSD %XMM12,%XMM1,%XMM1 |
(650) 0x47403b VADDSD %XMM12,%XMM0,%XMM0 |
(650) 0x474040 CMP %RCX,%R10 |
(650) 0x474043 JE 4736c2 |
(650) 0x474049 MOV %R13,0x20(%RSP) |
(650) 0x47404e MOV 0xa8(%RSP),%R14 |
(650) 0x474056 JMP 4740f7 |
0x47405b NOPL (%RAX,%RAX,1) |
(651) 0x474060 MOV (%RBX,%R9,8),%R13 |
(651) 0x474064 LEA (%R11,%R13,8),%R9 |
(651) 0x474068 VADDSD (%R9),%XMM9,%XMM10 |
(651) 0x47406d VMOVSD %XMM10,(%R9) |
(651) 0x474072 LEA 0x1(%RCX),%R13 |
(651) 0x474076 VMOVSD (%RDX),%XMM14 |
(651) 0x47407a VADDSD %XMM9,%XMM1,%XMM11 |
(651) 0x47407f MOV (%R8,%R13,8),%R9 |
(651) 0x474083 VADDSD %XMM9,%XMM0,%XMM13 |
(651) 0x474088 VMULSD (%R14,%R13,8),%XMM14,%XMM15 |
(651) 0x47408e TEST %R9,%R9 |
(651) 0x474091 JS 4741b8 |
(651) 0x474097 MOV (%RBX,%R9,8),%R13 |
(651) 0x47409b LEA (%R11,%R13,8),%R9 |
(651) 0x47409f VADDSD (%R9),%XMM15,%XMM12 |
(651) 0x4740a4 VMOVSD %XMM12,(%R9) |
(651) 0x4740a9 LEA 0x2(%RCX),%R13 |
(651) 0x4740ad VMOVSD (%RDX),%XMM1 |
(651) 0x4740b1 VADDSD %XMM15,%XMM11,%XMM6 |
(651) 0x4740b6 MOV (%R8,%R13,8),%R9 |
(651) 0x4740ba VADDSD %XMM15,%XMM13,%XMM7 |
(651) 0x4740bf VMULSD (%R14,%R13,8),%XMM1,%XMM12 |
(651) 0x4740c5 TEST %R9,%R9 |
(651) 0x4740c8 JS 474190 |
(651) 0x4740ce MOV (%RBX,%R9,8),%R13 |
(651) 0x4740d2 LEA (%R11,%R13,8),%R9 |
(651) 0x4740d6 VADDSD (%R9),%XMM12,%XMM0 |
(651) 0x4740db VMOVSD %XMM0,(%R9) |
(651) 0x4740e0 ADD $0x3,%RCX |
(651) 0x4740e4 VADDSD %XMM12,%XMM6,%XMM1 |
(651) 0x4740e9 VADDSD %XMM12,%XMM7,%XMM0 |
(651) 0x4740ee CMP %RCX,%R10 |
(651) 0x4740f1 JE 474208 |
(651) 0x4740f7 VMOVSD (%RDX),%XMM12 |
(651) 0x4740fb MOV (%R8,%RCX,8),%R9 |
(651) 0x4740ff VMULSD (%R14,%RCX,8),%XMM12,%XMM2 |
(651) 0x474105 TEST %R9,%R9 |
(651) 0x474108 JS 474168 |
(651) 0x47410a MOV (%RBX,%R9,8),%R13 |
(651) 0x47410e LEA (%R11,%R13,8),%R9 |
(651) 0x474112 VADDSD (%R9),%XMM2,%XMM6 |
(651) 0x474117 VMOVSD %XMM6,(%R9) |
(651) 0x47411c INC %RCX |
(651) 0x47411f VMOVSD (%RDX),%XMM8 |
(651) 0x474123 VADDSD %XMM2,%XMM1,%XMM1 |
(651) 0x474127 VADDSD %XMM2,%XMM0,%XMM0 |
(651) 0x47412b MOV (%R8,%RCX,8),%R9 |
(651) 0x47412f VMULSD (%R14,%RCX,8),%XMM8,%XMM9 |
(651) 0x474135 TEST %R9,%R9 |
(651) 0x474138 JNS 474060 |
(651) 0x47413e MOV 0x130(%RSP),%R13 |
(651) 0x474146 NOT %R9 |
(651) 0x474149 MOV (%R13,%R9,8),%R9 |
(651) 0x47414e LEA (%R12,%R9,8),%R13 |
(651) 0x474152 VADDSD (%R13),%XMM9,%XMM5 |
(651) 0x474158 VMOVSD %XMM5,(%R13) |
(651) 0x47415e JMP 474072 |
0x474163 NOPL (%RAX,%RAX,1) |
(651) 0x474168 MOV 0x130(%RSP),%R13 |
(651) 0x474170 NOT %R9 |
(651) 0x474173 MOV (%R13,%R9,8),%R9 |
(651) 0x474178 LEA (%R12,%R9,8),%R13 |
(651) 0x47417c VADDSD (%R13),%XMM2,%XMM7 |
(651) 0x474182 VMOVSD %XMM7,(%R13) |
(651) 0x474188 JMP 47411c |
0x47418a NOPW (%RAX,%RAX,1) |
(651) 0x474190 MOV 0x130(%RSP),%R13 |
(651) 0x474198 NOT %R9 |
(651) 0x47419b MOV (%R13,%R9,8),%R9 |
(651) 0x4741a0 LEA (%R12,%R9,8),%R13 |
(651) 0x4741a4 VADDSD (%R13),%XMM12,%XMM8 |
(651) 0x4741aa VMOVSD %XMM8,(%R13) |
(651) 0x4741b0 JMP 4740e0 |
0x4741b5 NOPL (%RAX) |
(651) 0x4741b8 MOV 0x130(%RSP),%R13 |
(651) 0x4741c0 NOT %R9 |
(651) 0x4741c3 MOV (%R13,%R9,8),%R9 |
(651) 0x4741c8 LEA (%R12,%R9,8),%R13 |
(651) 0x4741cc VADDSD (%R13),%XMM15,%XMM2 |
(651) 0x4741d2 VMOVSD %XMM2,(%R13) |
(651) 0x4741d8 JMP 4740a9 |
0x4741dd NOPL (%RAX) |
(650) 0x4741e0 MOV 0x130(%RSP),%R14 |
(650) 0x4741e8 NOT %R9 |
(650) 0x4741eb MOV (%R14,%R9,8),%R9 |
(650) 0x4741ef LEA (%R12,%R9,8),%R14 |
(650) 0x4741f3 VADDSD (%R14),%XMM12,%XMM15 |
(650) 0x4741f8 VMOVSD %XMM15,(%R14) |
(650) 0x4741fd JMP 474033 |
0x474202 NOPW (%RAX,%RAX,1) |
(650) 0x474208 MOV 0x20(%RSP),%R13 |
(650) 0x47420d JMP 4736c2 |
0x474212 NOPW (%RAX,%RAX,1) |
(650) 0x474218 MOV 0x130(%RSP),%R14 |
(650) 0x474220 NOT %R9 |
(650) 0x474223 MOV (%R14,%R9,8),%R9 |
(650) 0x474227 LEA (%R12,%R9,8),%R14 |
(650) 0x47422b VADDSD (%R14),%XMM10,%XMM11 |
(650) 0x474230 VMOVSD %XMM11,(%R14) |
(650) 0x474235 JMP 473ff5 |
(647) 0x47423a MOV %RBX,0x178(%RSP) |
(647) 0x474242 MOV 0x130(%RSP),%R8 |
(647) 0x47424a JMP 4731bc |
(647) 0x47424f VXORPD %XMM0,%XMM0,%XMM0 |
(647) 0x474253 VMOVSD %XMM0,%XMM0,%XMM1 |
(647) 0x474257 JMP 473637 |
(647) 0x47425c XOR %R9D,%R9D |
(647) 0x47425f JMP 473e62 |
(647) 0x474264 XOR %R9D,%R9D |
(647) 0x474267 JMP 473c61 |
(650) 0x47426c MOV 0x130(%RSP),%R14 |
(650) 0x474274 NOT %R9 |
(650) 0x474277 MOV (%R14,%R9,8),%R9 |
(650) 0x47427b LEA (%R12,%R9,8),%R14 |
(650) 0x47427f VADDSD (%R14),%XMM6,%XMM8 |
(650) 0x474284 VMOVSD %XMM8,(%R14) |
(650) 0x474289 JMP 473fb9 |
0x47428e MOV %R11,0xd8(%RSP) |
0x474296 MOV $0x8,%ESI |
0x47429b MOV %RDX,%RDI |
0x47429e MOV %R10,0xe0(%RSP) |
0x4742a6 VMOVSD %XMM2,0x100(%RSP) |
0x4742af JMP 472e4f |
0x4742b4 MOV $0x8,%ESI |
0x4742b9 MOV %RCX,%RDI |
0x4742bc MOV %R11,0xb8(%RSP) |
0x4742c4 MOV %R10,0xc0(%RSP) |
0x4742cc MOV %RDX,0xd8(%RSP) |
0x4742d4 MOV %R8,0xe0(%RSP) |
0x4742dc VMOVSD %XMM2,0x100(%RSP) |
0x4742e5 CALL 5b0890 <hypre_CAlloc> |
0x4742ea VMOVSD 0x100(%RSP),%XMM2 |
0x4742f3 MOV 0xe0(%RSP),%R8 |
0x4742fb MOV 0xd8(%RSP),%RDX |
0x474303 MOV 0xc0(%RSP),%R10 |
0x47430b MOV %RAX,%R15 |
0x47430e MOV 0xb8(%RSP),%R11 |
0x474316 JMP 472e25 |
0x47431b MOV $0x8,%ESI |
0x474320 MOV %R14,%RDI |
0x474323 MOV %R11,0xb0(%RSP) |
0x47432b MOV %R10,0xb8(%RSP) |
0x474333 MOV %RCX,0xc0(%RSP) |
0x47433b MOV %RDX,0xd8(%RSP) |
0x474343 MOV %R8,0xe0(%RSP) |
0x47434b VMOVSD %XMM2,0x100(%RSP) |
0x474354 CALL 5b0890 <hypre_CAlloc> |
0x474359 VMOVSD 0x100(%RSP),%XMM2 |
0x474362 MOV 0xe0(%RSP),%R8 |
0x47436a MOV 0xd8(%RSP),%RDX |
0x474372 MOV 0xc0(%RSP),%RCX |
0x47437a MOV %RAX,0x138(%RSP) |
0x474382 MOV 0xb8(%RSP),%R10 |
0x47438a MOV 0xb0(%RSP),%R11 |
0x474392 JMP 472e19 |
0x474397 MOV %RSI,%RDI |
0x47439a MOV $0x8,%ESI |
0x47439f MOV %R11,0xb8(%RSP) |
0x4743a7 MOV %R10,0xc0(%RSP) |
0x4743af MOV %RCX,0xd8(%RSP) |
0x4743b7 MOV %RDX,0xe0(%RSP) |
0x4743bf MOV %R8,0x100(%RSP) |
0x4743c7 VMOVSD %XMM2,0x138(%RSP) |
0x4743d0 CALL 5b0890 <hypre_CAlloc> |
0x4743d5 VMOVSD 0x138(%RSP),%XMM2 |
0x4743de MOV 0x100(%RSP),%R8 |
0x4743e6 MOV 0xe0(%RSP),%RDX |
0x4743ee MOV 0xd8(%RSP),%RCX |
0x4743f6 MOV %RAX,0x170(%RSP) |
0x4743fe MOV 0xc0(%RSP),%R10 |
0x474406 MOV 0xb8(%RSP),%R11 |
0x47440e JMP 472e04 |
0x474413 NOPW %CS:(%RAX,%RAX,1) |
0x47441e XCHG %AX,%AX |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
○98.63 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
○1.37 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
Path / |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1581 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
cycles | 6.80 | 8.00 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.58 |
Stall cycles | 1.42 |
RS full (events) | 6.22 |
Front-end | 46.00 |
Dispatch | 45.50 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 13% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474397 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x17a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47431b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x172b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4742b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x16c4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47428e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x169e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x178(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 472ecb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 472f1c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x32c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x178(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b39b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x168(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x178(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 473efc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xd0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x146e6f(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0950 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 472e4f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x25f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e25 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x235> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e19 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x138(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_multi_interp.c:1737-1881 |
Module | exec |
nb instructions | 260 |
nb uops | 276 |
loop length | 1581 |
used x86 registers | 16 |
used mmx registers | 0 |
used xmm registers | 4 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 44 |
micro-operation queue | 46.00 cycles |
front end | 46.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 6.80 | 6.80 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
cycles | 6.80 | 8.00 | 31.00 | 31.00 | 45.50 | 6.80 | 6.80 | 45.50 | 45.50 | 45.50 | 6.80 | 31.00 |
Cycles executing div or sqrt instructions | 10.00 |
FE+BE cycles | 45.58 |
Stall cycles | 1.42 |
RS full (events) | 6.22 |
Front-end | 46.00 |
Dispatch | 45.50 |
DIV/SQRT | 10.00 |
Overall L1 | 46.00 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 6% |
all | 6% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 1% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 0% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 13% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 13% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 25% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | 12% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
AND $-0x40,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
SUB $0x180,%RSP | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0x148(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x138(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x130(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x128(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x108(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x168(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xf8(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xf0(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xe8(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x110(%RDI),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x140(%RDI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x150(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x120(%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x118(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x118(%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R11,0x38(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,0x28(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x68(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R14,0x60(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xd8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x68(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x80(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0xd0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x58(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x50(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x48(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R10,0x108(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R11,0x58(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa0(%RDI),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R12,0x30(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x90(%RDI),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R13,0xf8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x78(%RDI),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xf0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x88(%RDI),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x70(%RDI),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,0x140(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x50(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x40(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x38(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x30(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x28(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0x48(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x20(%RDI),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R9,0x40(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x10(%RDI),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RDI),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDI),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RBX,0xc8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x120(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R15,0x160(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x128(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 474397 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x17a7> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 47431b <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x172b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOVQ $0,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
TEST %RCX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JNE 4742b4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x16c4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %R15D,%R15D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 47428e <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x169e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R8,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
CMPQ $0,0x178(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JLE 472ecb <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x2db> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x178(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %R14,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 472f1c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x32c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (,%R14,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV $0xff,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 4110a0 <memset@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x178(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x178(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RAX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b39c0 <hypre_GetThreadNum> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b39b0 <hypre_NumActiveThreads> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x130(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x110(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x168(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x168(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RDX,%R8,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD 0x178(%RSP),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
MOV %RDI,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
IDIV %R9 | 5 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 10 |
ADD %RCX,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
DEC %R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xd8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
IMUL %RAX,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
ADD %R10,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RCX,%R10,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0xe0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMOVNE %RAX,%R8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 473efc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x130c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0xd0(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ 0x146e6f(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%RSI,8),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%R14,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R15,0x130(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R9,0x110(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDI,0x70(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
DEC %R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x130(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
MOV 0x170(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV 0x138(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
MOV %R15,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CALL 5b0950 <hypre_Free> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
LEA -0x28(%RBP),%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RBX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
JMP 5b0950 <hypre_Free> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R11,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R10,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 472e4f <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x25f> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RCX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e25 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x235> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R11,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x100(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xb8(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e19 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x229> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV $0x8,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %R11,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R10,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RCX,0xd8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,0xe0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x100(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM2,0x138(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CALL 5b0890 <hypre_CAlloc> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
VMOVSD 0x138(%RSP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x100(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0x170(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb8(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 472e04 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGBuildMultipass._omp_fn.10– | 2.67 | 0.71 |
▼Loop 647 - par_multi_interp.c:1774-1876 - exec– | 0.41 | 0.07 |
▼Loop 652 - par_multi_interp.c:1811-1837 - exec– | 1.48 | 0.26 |
○Loop 654 - par_multi_interp.c:1816-1822 - exec | 0 | 0 |
○Loop 653 - par_multi_interp.c:1824-1830 - exec | 0 | 0 |
○Loop 656 - par_multi_interp.c:1799-1803 - exec | 0.78 | 0.14 |
▼Loop 650 - par_multi_interp.c:1840-1867 - exec– | 0 | 0 |
○Loop 651 - par_multi_interp.c:1851-1860 - exec | 0 | 0 |
○Loop 657 - par_multi_interp.c:1792-1797 - exec | 0 | 0 |
○Loop 658 - par_multi_interp.c:1782-1787 - exec | 0 | 0 |
○Loop 655 - par_multi_interp.c:1805-1809 - exec | 0 | 0 |
○Loop 648 - par_multi_interp.c:1875-1876 - exec | 0 | 0 |
○Loop 649 - par_multi_interp.c:1873-1874 - exec | 0 | 0 |