Loop Id: 3372 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.05% |
---|
Loop Id: 3372 | Module: exec | Source: par_csr_matop.c:127-242 [...] | Coverage: 0.05% |
---|
0x4af630 MOV -0x80(%RBP),%RSI |
0x4af634 MOV -0x50(%RBP),%RDI |
0x4af638 MOV %RBX,(%RSI,%RDI,8) |
0x4af63c MOV -0x78(%RBP),%RSI |
0x4af640 MOV %R8,(%RSI,%RDI,8) |
0x4af644 MOV %RDX,%RDI |
0x4af647 MOV %R13,%R8 |
0x4af64a MOV %RAX,%RBX |
0x4af64d CMP -0x48(%RBP),%RDX |
0x4af651 JGE 4af818 |
0x4af657 MOV 0x78(%RBP),%RSI |
0x4af65b TEST %RSI,%RSI |
0x4af65e JE 4af668 |
0x4af660 MOV %RBX,(%R14,%RDI,8) |
0x4af664 LEA 0x1(%RBX),%RAX |
0x4af668 CMPQ $0,0x70(%RBP) |
0x4af66d MOV %RDI,-0x50(%RBP) |
0x4af671 JE 4af740 |
0x4af677 MOV 0x10(%RBP),%RSI |
0x4af67b MOV (%RSI,%RDI,8),%R10 |
0x4af67f LEA 0x1(%RDI),%RDX |
0x4af683 CMP 0x8(%RSI,%RDI,8),%R10 |
0x4af688 JGE 4af744 |
0x4af68e MOV %RDX,-0x70(%RBP) |
0x4af692 MOV %R8,%R13 |
0x4af695 JMP 4af6b6 |
(3376) 0x4af6a0 INC %R10 |
(3376) 0x4af6a3 MOV 0x10(%RBP),%RSI |
(3376) 0x4af6a7 MOV -0x50(%RBP),%RDI |
(3376) 0x4af6ab CMP 0x8(%RSI,%RDI,8),%R10 |
(3376) 0x4af6b0 JGE 4af750 |
(3376) 0x4af6b6 MOV 0x18(%RBP),%RSI |
(3376) 0x4af6ba MOV (%RSI,%R10,8),%R12 |
(3376) 0x4af6be MOV 0x50(%RBP),%RDI |
(3376) 0x4af6c2 MOV (%RDI,%R12,8),%RSI |
(3376) 0x4af6c6 MOV 0x8(%RDI,%R12,8),%RDI |
(3376) 0x4af6cb JMP 4af6d3 |
(3378) 0x4af6d0 INC %RSI |
(3378) 0x4af6d3 CMP %RDI,%RSI |
(3378) 0x4af6d6 JGE 4af700 |
(3378) 0x4af6d8 MOV (%R11,%RSI,8),%R9 |
(3378) 0x4af6dc ADD %R15,%R9 |
(3378) 0x4af6df CMP %R8,(%R14,%R9,8) |
(3378) 0x4af6e3 JGE 4af6d0 |
(3378) 0x4af6e5 MOV %R13,(%R14,%R9,8) |
(3378) 0x4af6e9 INC %R13 |
(3378) 0x4af6ec MOV 0x50(%RBP),%RDI |
(3378) 0x4af6f0 MOV 0x8(%RDI,%R12,8),%RDI |
(3378) 0x4af6f5 JMP 4af6d0 |
(3376) 0x4af700 MOV 0x40(%RBP),%RDI |
(3376) 0x4af704 MOV (%RDI,%R12,8),%RSI |
(3376) 0x4af708 MOV 0x8(%RDI,%R12,8),%RDI |
(3376) 0x4af70d JMP 4af713 |
(3377) 0x4af710 INC %RSI |
(3377) 0x4af713 CMP %RDI,%RSI |
(3377) 0x4af716 JGE 4af6a0 |
(3377) 0x4af718 MOV 0x48(%RBP),%R9 |
(3377) 0x4af71c MOV (%R9,%RSI,8),%R9 |
(3377) 0x4af720 CMP %RBX,(%R14,%R9,8) |
(3377) 0x4af724 JGE 4af710 |
(3377) 0x4af726 MOV %RAX,(%R14,%R9,8) |
(3377) 0x4af72a INC %RAX |
(3377) 0x4af72d MOV 0x40(%RBP),%RDI |
(3377) 0x4af731 MOV 0x8(%RDI,%R12,8),%RDI |
(3377) 0x4af736 JMP 4af710 |
0x4af740 LEA 0x1(%RDI),%RDX |
0x4af744 MOV %R8,%R13 |
0x4af747 JMP 4af754 |
0x4af750 MOV -0x70(%RBP),%RDX |
0x4af754 MOV -0x58(%RBP),%RSI |
0x4af758 MOV (%RSI,%RDI,8),%R10 |
0x4af75c CMP (%RSI,%RDX,8),%R10 |
0x4af760 JL 4af785 |
0x4af762 JMP 4af630 |
(3373) 0x4af770 INC %R10 |
(3373) 0x4af773 MOV -0x58(%RBP),%RSI |
(3373) 0x4af777 CMP (%RSI,%RDX,8),%R10 |
(3373) 0x4af77b MOV 0x58(%RBP),%R11 |
(3373) 0x4af77f JGE 4af630 |
(3373) 0x4af785 MOV -0x88(%RBP),%RSI |
(3373) 0x4af78c MOV (%RSI,%R10,8),%R12 |
(3373) 0x4af790 MOV 0x20(%RBP),%R11 |
(3373) 0x4af794 MOV (%R11,%R12,8),%RSI |
(3373) 0x4af798 MOV 0x8(%R11,%R12,8),%RDI |
(3373) 0x4af79d JMP 4af7a3 |
(3375) 0x4af7a0 INC %RSI |
(3375) 0x4af7a3 CMP %RDI,%RSI |
(3375) 0x4af7a6 JGE 4af7c0 |
(3375) 0x4af7a8 MOV (%RCX,%RSI,8),%R9 |
(3375) 0x4af7ac CMP %RBX,(%R14,%R9,8) |
(3375) 0x4af7b0 JGE 4af7a0 |
(3375) 0x4af7b2 MOV %RAX,(%R14,%R9,8) |
(3375) 0x4af7b6 INC %RAX |
(3375) 0x4af7b9 MOV 0x8(%R11,%R12,8),%RDI |
(3375) 0x4af7be JMP 4af7a0 |
(3373) 0x4af7c0 CMPQ $0,0x88(%RBP) |
(3373) 0x4af7c8 JE 4af770 |
(3373) 0x4af7ca MOV 0x30(%RBP),%RDI |
(3373) 0x4af7ce MOV (%RDI,%R12,8),%RSI |
(3373) 0x4af7d2 MOV 0x8(%RDI,%R12,8),%RDI |
(3373) 0x4af7d7 JMP 4af7e3 |
(3374) 0x4af7e0 INC %RSI |
(3374) 0x4af7e3 CMP %RDI,%RSI |
(3374) 0x4af7e6 JGE 4af770 |
(3374) 0x4af7e8 MOV 0x38(%RBP),%R9 |
(3374) 0x4af7ec MOV (%R9,%RSI,8),%R9 |
(3374) 0x4af7f0 MOV 0x60(%RBP),%R11 |
(3374) 0x4af7f4 MOV (%R11,%R9,8),%R9 |
(3374) 0x4af7f8 ADD %R15,%R9 |
(3374) 0x4af7fb CMP %R8,(%R14,%R9,8) |
(3374) 0x4af7ff JGE 4af7e0 |
(3374) 0x4af801 MOV %R13,(%R14,%R9,8) |
(3374) 0x4af805 INC %R13 |
(3374) 0x4af808 MOV 0x30(%RBP),%RDI |
(3374) 0x4af80c MOV 0x8(%RDI,%R12,8),%RDI |
(3374) 0x4af811 JMP 4af7e0 |
/scratch_na/users/xoserete/qaas_runs/171-415-3661/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242 |
-------------------------------------------------------------------------------- |
127: for (i1 = ns; i1 < ne; i1++) |
[...] |
135: if ( allsquare ) { |
136: B_marker[i1] = jj_count_diag; |
137: jj_count_diag++; |
[...] |
144: if (num_cols_offd_A) |
145: { |
146: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
147: { |
148: i2 = A_offd_j[jj2]; |
[...] |
154: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
155: { |
156: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
164: if (B_marker[i3] < jj_row_begin_offd) |
165: { |
166: B_marker[i3] = jj_count_offd; |
167: jj_count_offd++; |
168: } |
169: } |
170: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
171: { |
172: i3 = B_ext_diag_j[jj3]; |
173: |
174: if (B_marker[i3] < jj_row_begin_diag) |
175: { |
176: B_marker[i3] = jj_count_diag; |
177: jj_count_diag++; |
[...] |
187: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
188: { |
189: i2 = A_diag_j[jj2]; |
[...] |
195: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
196: { |
197: i3 = B_diag_j[jj3]; |
[...] |
205: if (B_marker[i3] < jj_row_begin_diag) |
206: { |
207: B_marker[i3] = jj_count_diag; |
208: jj_count_diag++; |
[...] |
216: if (num_cols_offd_B) |
217: { |
218: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
219: { |
220: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
228: if (B_marker[i3] < jj_row_begin_offd) |
229: { |
230: B_marker[i3] = jj_count_offd; |
231: jj_count_offd++; |
[...] |
241: (*C_diag_i)[i1] = jj_row_begin_diag; |
242: (*C_offd_i)[i1] = jj_row_begin_offd; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.77 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 2.50 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 2.50 |
P7 cycles | 2.50 |
P8 cycles | 2.50 |
P9 cycles | 1.60 |
P10 cycles | 4.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 13.00 |
Nb stores | 5.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 23.35 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 40.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 8.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.42 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul_RowSizes.extracted |
Source | par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.77 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 4.33 |
P2 cycles | 4.33 |
P3 cycles | 2.50 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 2.50 |
P7 cycles | 2.50 |
P8 cycles | 2.50 |
P9 cycles | 1.60 |
P10 cycles | 4.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 13.00 |
Nb stores | 5.00 |
Nb stack references | 9.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 23.35 |
Bytes prefetched | 0.00 |
Bytes loaded | 104.00 |
Bytes stored | 40.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 12.50 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 12.50 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 135 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 4.33 | 4.33 | 2.50 | 1.60 | 2.50 | 2.50 | 2.50 | 2.50 | 1.60 | 4.33 |
cycles | 2.50 | 1.80 | 4.33 | 4.33 | 2.50 | 1.60 | 2.50 | 2.50 | 2.50 | 2.50 | 1.60 | 4.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.31 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 4.33 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x48(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4af818 <hypre_ParMatmul_RowSizes.extracted+0x2d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4af668 <hypre_ParMatmul_RowSizes.extracted+0x128> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x70(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4af740 <hypre_ParMatmul_RowSizes.extracted+0x200> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4af744 <hypre_ParMatmul_RowSizes.extracted+0x204> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4af6b6 <hypre_ParMatmul_RowSizes.extracted+0x176> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4af754 <hypre_ParMatmul_RowSizes.extracted+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%RDX,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 4af785 <hypre_ParMatmul_RowSizes.extracted+0x245> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4af630 <hypre_ParMatmul_RowSizes.extracted+0xf0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_ParMatmul_RowSizes.extracted |
Source file and lines | par_csr_matop.c:127-242 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 135 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 9 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 4.33 | 4.33 | 2.50 | 1.60 | 2.50 | 2.50 | 2.50 | 2.50 | 1.60 | 4.33 |
cycles | 2.50 | 1.80 | 4.33 | 4.33 | 2.50 | 1.60 | 2.50 | 2.50 | 2.50 | 2.50 | 1.60 | 4.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.31 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 4.33 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | 12% |
store | 12% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x50(%RBP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RBX,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R8,(%RSI,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RDX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R13,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP -0x48(%RBP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4af818 <hypre_ParMatmul_RowSizes.extracted+0x2d8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x78(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4af668 <hypre_ParMatmul_RowSizes.extracted+0x128> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,(%R14,%RDI,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%RBX),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,0x70(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
MOV %RDI,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JE 4af740 <hypre_ParMatmul_RowSizes.extracted+0x200> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x10(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RSI,%RDI,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4af744 <hypre_ParMatmul_RowSizes.extracted+0x204> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RDX,-0x70(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4af6b6 <hypre_ParMatmul_RowSizes.extracted+0x176> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDI),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4af754 <hypre_ParMatmul_RowSizes.extracted+0x214> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV -0x70(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x58(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDI,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%RDX,8),%R10 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JL 4af785 <hypre_ParMatmul_RowSizes.extracted+0x245> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP 4af630 <hypre_ParMatmul_RowSizes.extracted+0xf0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |