Loop Id: 3393 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.04% |
---|
Loop Id: 3393 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.04% |
---|
0x4b05e0 MOV %RCX,%R12 |
0x4b05e3 MOV %RAX,%R14 |
0x4b05e6 MOV -0x48(%RBP),%RCX |
0x4b05ea CMP %RCX,%R8 |
0x4b05ed JGE 4b0936 |
0x4b05f3 MOV %R8,%RDX |
0x4b05f6 CMPQ $0,-0xc0(%RBP) |
0x4b05fe JE 4b0618 |
0x4b0600 MOV %R14,(%RDI,%RDX,8) |
0x4b0604 MOVQ $0,(%R15,%R14,8) |
0x4b060c MOV -0x58(%RBP),%RAX |
0x4b0610 MOV %RDX,(%RAX,%R14,8) |
0x4b0614 LEA 0x1(%R14),%RAX |
0x4b0618 CMPQ $0,-0xb8(%RBP) |
0x4b0620 JE 4b0790 |
0x4b0626 MOV -0x60(%RBP),%RCX |
0x4b062a MOV (%RCX,%RDX,8),%R9 |
0x4b062e LEA 0x1(%RDX),%R8 |
0x4b0632 CMP 0x8(%RCX,%RDX,8),%R9 |
0x4b0637 JGE 4b0794 |
0x4b063d MOV %R8,-0x30(%RBP) |
0x4b0641 MOV %R12,%RCX |
0x4b0644 MOV %RDX,-0xe0(%RBP) |
0x4b064b JMP 4b066d |
(3397) 0x4b0650 MOV -0x38(%RBP),%R9 |
(3397) 0x4b0654 INC %R9 |
(3397) 0x4b0657 MOV -0x60(%RBP),%RDX |
(3397) 0x4b065b MOV -0xe0(%RBP),%RSI |
(3397) 0x4b0662 CMP 0x8(%RDX,%RSI,8),%R9 |
(3397) 0x4b0667 JGE 4b07a0 |
(3397) 0x4b066d MOV -0xd0(%RBP),%RDX |
(3397) 0x4b0674 MOV (%RDX,%R9,8),%R8 |
(3397) 0x4b0678 MOV -0xd8(%RBP),%RDX |
(3397) 0x4b067f MOV %R9,-0x38(%RBP) |
(3397) 0x4b0683 VMOVSD (%RDX,%R9,8),%XMM0 |
(3397) 0x4b0689 MOV -0x80(%RBP),%RDX |
(3397) 0x4b068d MOV (%RDX,%R8,8),%R9 |
(3397) 0x4b0691 MOV 0x8(%RDX,%R8,8),%R10 |
(3397) 0x4b0696 CMP %R10,%R9 |
(3397) 0x4b0699 JL 4b06d5 |
(3397) 0x4b069b JMP 4b070b |
(3399) 0x4b06a0 MOV %RCX,(%RDI,%RSI,8) |
(3399) 0x4b06a4 MOV -0xa8(%RBP),%RDX |
(3399) 0x4b06ab VMULSD (%RDX,%R9,8),%XMM0,%XMM1 |
(3399) 0x4b06b1 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3399) 0x4b06b6 MOV -0x98(%RBP),%RDX |
(3399) 0x4b06bd MOV %R11,(%RDX,%RCX,8) |
(3399) 0x4b06c1 INC %RCX |
(3399) 0x4b06c4 MOV -0x80(%RBP),%RDX |
(3399) 0x4b06c8 MOV 0x8(%RDX,%R8,8),%R10 |
(3399) 0x4b06cd INC %R9 |
(3399) 0x4b06d0 CMP %R10,%R9 |
(3399) 0x4b06d3 JGE 4b070b |
(3399) 0x4b06d5 MOV (%R13,%R9,8),%R11 |
(3399) 0x4b06da MOV -0x40(%RBP),%RDX |
(3399) 0x4b06de LEA (%R11,%RDX,1),%RSI |
(3399) 0x4b06e2 MOV (%RDI,%RSI,8),%RDX |
(3399) 0x4b06e6 CMP %R12,%RDX |
(3399) 0x4b06e9 JL 4b06a0 |
(3399) 0x4b06eb MOV -0xa8(%RBP),%RSI |
(3399) 0x4b06f2 VMOVSD (%RSI,%R9,8),%XMM1 |
(3399) 0x4b06f8 VFMADD213SD (%RBX,%RDX,8),%XMM0,%XMM1 |
(3399) 0x4b06fe VMOVSD %XMM1,(%RBX,%RDX,8) |
(3399) 0x4b0703 INC %R9 |
(3399) 0x4b0706 CMP %R10,%R9 |
(3399) 0x4b0709 JL 4b06d5 |
(3397) 0x4b070b MOV -0x78(%RBP),%RDX |
(3397) 0x4b070f MOV (%RDX,%R8,8),%R9 |
(3397) 0x4b0713 MOV 0x8(%RDX,%R8,8),%R10 |
(3397) 0x4b0718 CMP %R10,%R9 |
(3397) 0x4b071b JGE 4b0650 |
(3397) 0x4b0721 MOV -0xc8(%RBP),%RSI |
(3397) 0x4b0728 JMP 4b0755 |
(3398) 0x4b0730 MOV -0xa0(%RBP),%R11 |
(3398) 0x4b0737 VMOVSD (%R11,%R9,8),%XMM1 |
(3398) 0x4b073d VFMADD213SD (%R15,%RDX,8),%XMM0,%XMM1 |
(3398) 0x4b0743 VMOVSD %XMM1,(%R15,%RDX,8) |
(3398) 0x4b0749 INC %R9 |
(3398) 0x4b074c CMP %R10,%R9 |
(3398) 0x4b074f JGE 4b0650 |
(3398) 0x4b0755 MOV (%RSI,%R9,8),%R11 |
(3398) 0x4b0759 MOV (%RDI,%R11,8),%RDX |
(3398) 0x4b075d CMP %R14,%RDX |
(3398) 0x4b0760 JGE 4b0730 |
(3398) 0x4b0762 MOV %RAX,(%RDI,%R11,8) |
(3398) 0x4b0766 MOV -0xa0(%RBP),%RDX |
(3398) 0x4b076d VMULSD (%RDX,%R9,8),%XMM0,%XMM1 |
(3398) 0x4b0773 VMOVSD %XMM1,(%R15,%RAX,8) |
(3398) 0x4b0779 MOV -0x58(%RBP),%RDX |
(3398) 0x4b077d MOV %R11,(%RDX,%RAX,8) |
(3398) 0x4b0781 INC %RAX |
(3398) 0x4b0784 MOV -0x78(%RBP),%RDX |
(3398) 0x4b0788 MOV 0x8(%RDX,%R8,8),%R10 |
(3398) 0x4b078d JMP 4b0749 |
0x4b0790 LEA 0x1(%RDX),%R8 |
0x4b0794 MOV %R12,%RCX |
0x4b0797 JMP 4b07a7 |
0x4b07a0 MOV %RSI,%RDX |
0x4b07a3 MOV -0x30(%RBP),%R8 |
0x4b07a7 MOV -0x68(%RBP),%RSI |
0x4b07ab MOV (%RSI,%RDX,8),%RDX |
0x4b07af CMP (%RSI,%R8,8),%RDX |
0x4b07b3 JGE 4b05e0 |
0x4b07b9 MOV %R8,-0x30(%RBP) |
0x4b07bd JMP 4b07d9 |
(3394) 0x4b07c0 INC %RDX |
(3394) 0x4b07c3 MOV -0x68(%RBP),%RSI |
(3394) 0x4b07c7 MOV -0x30(%RBP),%R8 |
(3394) 0x4b07cb CMP (%RSI,%R8,8),%RDX |
(3394) 0x4b07cf MOV -0x50(%RBP),%R13 |
(3394) 0x4b07d3 JGE 4b05e0 |
(3394) 0x4b07d9 MOV -0xf8(%RBP),%RSI |
(3394) 0x4b07e0 MOV (%RSI,%RDX,8),%RSI |
(3394) 0x4b07e4 MOV -0xf0(%RBP),%R8 |
(3394) 0x4b07eb VMOVSD (%R8,%RDX,8),%XMM0 |
(3394) 0x4b07f1 MOV -0x88(%RBP),%R9 |
(3394) 0x4b07f8 MOV (%R9,%RSI,8),%R8 |
(3394) 0x4b07fc MOV 0x8(%R9,%RSI,8),%R9 |
(3394) 0x4b0801 CMP %R9,%R8 |
(3394) 0x4b0804 JGE 4b0880 |
(3394) 0x4b0806 MOV -0x58(%RBP),%R13 |
(3394) 0x4b080a JMP 4b0831 |
(3396) 0x4b0810 MOV -0xb0(%RBP),%R10 |
(3396) 0x4b0817 VMOVSD (%R10,%R8,8),%XMM1 |
(3396) 0x4b081d VFMADD213SD (%R15,%R11,8),%XMM0,%XMM1 |
(3396) 0x4b0823 VMOVSD %XMM1,(%R15,%R11,8) |
(3396) 0x4b0829 INC %R8 |
(3396) 0x4b082c CMP %R9,%R8 |
(3396) 0x4b082f JGE 4b0880 |
(3396) 0x4b0831 MOV -0x110(%RBP),%R10 |
(3396) 0x4b0838 MOV (%R10,%R8,8),%R10 |
(3396) 0x4b083c MOV (%RDI,%R10,8),%R11 |
(3396) 0x4b0840 CMP %R14,%R11 |
(3396) 0x4b0843 JGE 4b0810 |
(3396) 0x4b0845 MOV %RAX,(%RDI,%R10,8) |
(3396) 0x4b0849 MOV -0xb0(%RBP),%R9 |
(3396) 0x4b0850 VMULSD (%R9,%R8,8),%XMM0,%XMM1 |
(3396) 0x4b0856 VMOVSD %XMM1,(%R15,%RAX,8) |
(3396) 0x4b085c MOV %R10,(%R13,%RAX,8) |
(3396) 0x4b0861 INC %RAX |
(3396) 0x4b0864 MOV -0x88(%RBP),%R9 |
(3396) 0x4b086b MOV 0x8(%R9,%RSI,8),%R9 |
(3396) 0x4b0870 JMP 4b0829 |
(3394) 0x4b0880 CMPQ $0,-0xe8(%RBP) |
(3394) 0x4b0888 JE 4b07c0 |
(3394) 0x4b088e MOV -0x70(%RBP),%R9 |
(3394) 0x4b0892 MOV (%R9,%RSI,8),%R8 |
(3394) 0x4b0896 MOV 0x8(%R9,%RSI,8),%R9 |
(3394) 0x4b089b CMP %R9,%R8 |
(3394) 0x4b089e JL 4b08e9 |
(3394) 0x4b08a0 JMP 4b07c0 |
(3395) 0x4b08b0 MOV %RCX,(%RDI,%R13,8) |
(3395) 0x4b08b4 MOV -0x90(%RBP),%R9 |
(3395) 0x4b08bb VMULSD (%R9,%R8,8),%XMM0,%XMM1 |
(3395) 0x4b08c1 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3395) 0x4b08c6 MOV -0x98(%RBP),%R9 |
(3395) 0x4b08cd MOV %R10,(%R9,%RCX,8) |
(3395) 0x4b08d1 INC %RCX |
(3395) 0x4b08d4 MOV -0x70(%RBP),%R9 |
(3395) 0x4b08d8 MOV 0x8(%R9,%RSI,8),%R9 |
(3395) 0x4b08dd INC %R8 |
(3395) 0x4b08e0 CMP %R9,%R8 |
(3395) 0x4b08e3 JGE 4b07c0 |
(3395) 0x4b08e9 MOV -0x100(%RBP),%R10 |
(3395) 0x4b08f0 MOV (%R10,%R8,8),%R10 |
(3395) 0x4b08f4 MOV -0x108(%RBP),%R11 |
(3395) 0x4b08fb MOV (%R11,%R10,8),%R10 |
(3395) 0x4b08ff MOV -0x40(%RBP),%R11 |
(3395) 0x4b0903 LEA (%R10,%R11,1),%R13 |
(3395) 0x4b0907 MOV (%RDI,%R13,8),%R11 |
(3395) 0x4b090b CMP %R12,%R11 |
(3395) 0x4b090e JL 4b08b0 |
(3395) 0x4b0910 MOV -0x90(%RBP),%R10 |
(3395) 0x4b0917 VMOVSD (%R10,%R8,8),%XMM1 |
(3395) 0x4b091d VFMADD213SD (%RBX,%R11,8),%XMM0,%XMM1 |
(3395) 0x4b0923 VMOVSD %XMM1,(%RBX,%R11,8) |
(3395) 0x4b0929 INC %R8 |
(3395) 0x4b092c CMP %R9,%R8 |
(3395) 0x4b092f JL 4b08e9 |
(3394) 0x4b0931 JMP 4b07c0 |
/scratch_na/users/xoserete/qaas_runs/171-415-3661/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
875: { |
876: B_marker[i1] = jj_count_diag; |
877: C_diag_data[jj_count_diag] = zero; |
878: C_diag_j[jj_count_diag] = i1; |
879: jj_count_diag++; |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.44 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.68 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 3.00 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 3.00 |
P9 cycles | 1.60 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 11.00 |
Nb stores | 6.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.05 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 48.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.98 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.46 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.00 |
CQA speedup if fully vectorized | 12.44 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.68 |
Bottlenecks | micro-operation queue, |
Function | hypre_ParMatmul.extracted.12 |
Source | par_csr_matop.c:865-865,par_csr_matop.c:874-879,par_csr_matop.c:886-888,par_csr_matop.c:937-937 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 6.17 |
CQA cycles if no scalar integer | 6.17 |
CQA cycles if FP arith vectorized | 6.17 |
CQA cycles if fully vectorized | 0.50 |
Front-end cycles | 6.17 |
DIV/SQRT cycles | 2.50 |
P0 cycles | 1.80 |
P1 cycles | 3.67 |
P2 cycles | 3.67 |
P3 cycles | 3.00 |
P4 cycles | 1.60 |
P5 cycles | 2.50 |
P6 cycles | 3.00 |
P7 cycles | 3.00 |
P8 cycles | 3.00 |
P9 cycles | 1.60 |
P10 cycles | 3.67 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 6.31 |
Stall cycles (UFS) | 0.00 |
Nb insns | 35.00 |
Nb uops | 35.00 |
Nb loads | 11.00 |
Nb stores | 6.00 |
Nb stack references | 8.00 |
FLOP/cycle | 0.00 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 22.05 |
Bytes prefetched | 0.00 |
Bytes loaded | 88.00 |
Bytes stored | 48.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 0.00 |
Vectorization ratio load | 0.00 |
Vectorization ratio store | 0.00 |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 0.00 |
Vector-efficiency ratio all | 11.98 |
Vector-efficiency ratio load | 12.50 |
Vector-efficiency ratio store | 11.46 |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 12.50 |
Path / |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 149 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 3.67 | 3.67 | 3.00 | 1.60 | 2.50 | 3.00 | 3.00 | 3.00 | 1.60 | 3.67 |
cycles | 2.50 | 1.80 | 3.67 | 3.67 | 3.00 | 1.60 | 2.50 | 3.00 | 3.00 | 3.00 | 1.60 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.31 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 3.67 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4b0936 <hypre_ParMatmul.extracted.12+0x586> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0xc0(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0618 <hypre_ParMatmul.extracted.12+0x268> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R15,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RAX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0xb8(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0790 <hypre_ParMatmul.extracted.12+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDX,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RDX,8),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0794 <hypre_ParMatmul.extracted.12+0x3e4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b066d <hypre_ParMatmul.extracted.12+0x2bd> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4b07a7 <hypre_ParMatmul.extracted.12+0x3f7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%R8,8),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b05e0 <hypre_ParMatmul.extracted.12+0x230> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b07d9 <hypre_ParMatmul.extracted.12+0x429> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
Function | hypre_ParMatmul.extracted.12 |
Source file and lines | par_csr_matop.c:865-989 |
Module | exec |
nb instructions | 35 |
nb uops | 35 |
loop length | 149 |
used x86 registers | 11 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 8 |
micro-operation queue | 6.17 cycles |
front end | 6.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.80 | 3.67 | 3.67 | 3.00 | 1.60 | 2.50 | 3.00 | 3.00 | 3.00 | 1.60 | 3.67 |
cycles | 2.50 | 1.80 | 3.67 | 3.67 | 3.00 | 1.60 | 2.50 | 3.00 | 3.00 | 3.00 | 1.60 | 3.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 6.31 |
Stall cycles | 0.00 |
Front-end | 6.17 |
Dispatch | 3.67 |
Overall L1 | 6.17 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV %RCX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x48(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4b0936 <hypre_ParMatmul.extracted.12+0x586> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMPQ $0,-0xc0(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0618 <hypre_ParMatmul.extracted.12+0x268> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R14,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R15,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV -0x58(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,(%RAX,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA 0x1(%R14),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMPQ $0,-0xb8(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JE 4b0790 <hypre_ParMatmul.extracted.12+0x3e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV -0x60(%RBP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDX,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%RDX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP 0x8(%RCX,%RDX,8),%R9 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b0794 <hypre_ParMatmul.extracted.12+0x3e4> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDX,-0xe0(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b066d <hypre_ParMatmul.extracted.12+0x2bd> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
LEA 0x1(%RDX),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R12,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4b07a7 <hypre_ParMatmul.extracted.12+0x3f7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV %RSI,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV -0x30(%RBP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV -0x68(%RBP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI,%RDX,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP (%RSI,%R8,8),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JGE 4b05e0 <hypre_ParMatmul.extracted.12+0x230> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R8,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 4b07d9 <hypre_ParMatmul.extracted.12+0x429> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |