Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
Function: hypre_qsort0 | Module: exec | Source: hypre_qsort.c:31-187 [...] | Coverage: 0.01% |
---|
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/utilities/hypre_qsort.c: 31 - 187 |
-------------------------------------------------------------------------------- |
31: temp = v[i]; |
32: v[i] = v[j]; |
33: v[j] = temp; |
[...] |
175: if (left >= right) |
176: return; |
177: hypre_swap( v, left, (left+right)/2); |
178: last = left; |
179: for (i = left+1; i <= right; i++) |
180: if (v[i] < v[left]) |
181: { |
182: hypre_swap(v, ++last, i); |
183: } |
184: hypre_swap(v, left, last); |
185: hypre_qsort0(v, left, last-1); |
186: hypre_qsort0(v, last+1, right); |
187: } |
0x4e7530 CMP %RDX,%RSI |
0x4e7533 JGE 4e76da |
0x4e7539 PUSH %RBP |
0x4e753a MOV %RSP,%RBP |
0x4e753d PUSH %R15 |
0x4e753f PUSH %R14 |
0x4e7541 PUSH %R12 |
0x4e7543 PUSH %RBX |
0x4e7544 MOV %RDX,%RBX |
0x4e7547 MOV %RDI,%R14 |
0x4e754a LEA 0x20(%RDI),%R15 |
0x4e754e MOV %RSI,%R12 |
0x4e7551 JMP 4e758c |
0x4e7553 NOPW %CS:(%RAX,%RAX,1) |
(4441) 0x4e7560 MOV (%R14,%RSI,8),%RAX |
(4441) 0x4e7564 MOV (%R14,%R12,8),%RCX |
(4441) 0x4e7568 MOV %RCX,(%R14,%RSI,8) |
(4441) 0x4e756c MOV %RAX,(%R14,%R12,8) |
(4441) 0x4e7570 LEA -0x1(%R12),%RDX |
(4441) 0x4e7575 MOV %R14,%RDI |
(4441) 0x4e7578 CALL 4e7530 <hypre_qsort0> |
(4441) 0x4e757d INC %R12 |
(4441) 0x4e7580 MOV %R12,%RSI |
(4441) 0x4e7583 CMP %RBX,%R12 |
(4441) 0x4e7586 JGE 4e76d2 |
(4441) 0x4e758c LEA (%RSI,%RBX,1),%RAX |
(4441) 0x4e7590 MOV %RAX,%RCX |
(4441) 0x4e7593 SHR $0x3f,%RCX |
(4441) 0x4e7597 ADD %RAX,%RCX |
(4441) 0x4e759a MOV (%R14,%RSI,8),%RAX |
(4441) 0x4e759e AND $-0x2,%RCX |
(4441) 0x4e75a2 MOV (%R14,%RCX,4),%RDX |
(4441) 0x4e75a6 MOV %RDX,(%R14,%RSI,8) |
(4441) 0x4e75aa MOV %RAX,(%R14,%RCX,4) |
(4441) 0x4e75ae LEA 0x1(%RSI),%RAX |
(4441) 0x4e75b2 CMP %RAX,%RBX |
(4441) 0x4e75b5 CMOVG %RBX,%RAX |
(4441) 0x4e75b9 MOV %RAX,%RCX |
(4441) 0x4e75bc SUB %RSI,%RCX |
(4441) 0x4e75bf CMP $0x4,%RCX |
(4441) 0x4e75c3 JAE 4e7610 |
(4441) 0x4e75c5 MOV %RCX,%RDX |
(4441) 0x4e75c8 AND $-0x4,%RDX |
(4441) 0x4e75cc CMP %RCX,%RDX |
(4441) 0x4e75cf JAE 4e7560 |
(4441) 0x4e75d1 ADD %RSI,%RDX |
(4441) 0x4e75d4 JMP 4e75ec |
0x4e75d6 NOPW %CS:(%RAX,%RAX,1) |
(4442) 0x4e75e0 INC %RDX |
(4442) 0x4e75e3 CMP %RDX,%RAX |
(4442) 0x4e75e6 JE 4e7560 |
(4442) 0x4e75ec MOV 0x8(%R14,%RDX,8),%RCX |
(4442) 0x4e75f1 CMP (%R14,%RSI,8),%RCX |
(4442) 0x4e75f5 JGE 4e75e0 |
(4442) 0x4e75f7 MOV 0x8(%R14,%R12,8),%RDI |
(4442) 0x4e75fc MOV %RCX,0x8(%R14,%R12,8) |
(4442) 0x4e7601 INC %R12 |
(4442) 0x4e7604 MOV %RDI,0x8(%R14,%RDX,8) |
(4442) 0x4e7609 JMP 4e75e0 |
0x4e760b NOPL (%RAX,%RAX,1) |
(4441) 0x4e7610 MOV %RCX,%RDX |
(4441) 0x4e7613 SHR $0x2,%RDX |
(4441) 0x4e7617 LEA (%R15,%RSI,8),%RDI |
(4441) 0x4e761b MOV %RSI,%R12 |
(4441) 0x4e761e JMP 4e7629 |
(4443) 0x4e7620 ADD $0x20,%RDI |
(4443) 0x4e7624 DEC %RDX |
(4443) 0x4e7627 JE 4e75c5 |
(4443) 0x4e7629 MOV -0x18(%RDI),%R9 |
(4443) 0x4e762d MOV (%R14,%RSI,8),%R8 |
(4443) 0x4e7631 CMP %R8,%R9 |
(4443) 0x4e7634 JL 4e7660 |
(4443) 0x4e7636 MOV -0x10(%RDI),%R9 |
(4443) 0x4e763a CMP %R8,%R9 |
(4443) 0x4e763d JL 4e767e |
(4443) 0x4e763f MOV -0x8(%RDI),%R9 |
(4443) 0x4e7643 CMP %R8,%R9 |
(4443) 0x4e7646 JL 4e769c |
(4443) 0x4e7648 MOV (%RDI),%R9 |
(4443) 0x4e764b CMP %R8,%R9 |
(4443) 0x4e764e JGE 4e7620 |
(4443) 0x4e7650 JMP 4e76bd |
0x4e7652 NOPW %CS:(%RAX,%RAX,1) |
(4443) 0x4e7660 MOV 0x8(%R14,%R12,8),%R8 |
(4443) 0x4e7665 MOV %R9,0x8(%R14,%R12,8) |
(4443) 0x4e766a INC %R12 |
(4443) 0x4e766d MOV %R8,-0x18(%RDI) |
(4443) 0x4e7671 MOV (%R14,%RSI,8),%R8 |
(4443) 0x4e7675 MOV -0x10(%RDI),%R9 |
(4443) 0x4e7679 CMP %R8,%R9 |
(4443) 0x4e767c JGE 4e763f |
(4443) 0x4e767e MOV 0x8(%R14,%R12,8),%R8 |
(4443) 0x4e7683 MOV %R9,0x8(%R14,%R12,8) |
(4443) 0x4e7688 INC %R12 |
(4443) 0x4e768b MOV %R8,-0x10(%RDI) |
(4443) 0x4e768f MOV (%R14,%RSI,8),%R8 |
(4443) 0x4e7693 MOV -0x8(%RDI),%R9 |
(4443) 0x4e7697 CMP %R8,%R9 |
(4443) 0x4e769a JGE 4e7648 |
(4443) 0x4e769c MOV 0x8(%R14,%R12,8),%R8 |
(4443) 0x4e76a1 MOV %R9,0x8(%R14,%R12,8) |
(4443) 0x4e76a6 INC %R12 |
(4443) 0x4e76a9 MOV %R8,-0x8(%RDI) |
(4443) 0x4e76ad MOV (%R14,%RSI,8),%R8 |
(4443) 0x4e76b1 MOV (%RDI),%R9 |
(4443) 0x4e76b4 CMP %R8,%R9 |
(4443) 0x4e76b7 JGE 4e7620 |
(4443) 0x4e76bd MOV 0x8(%R14,%R12,8),%R8 |
(4443) 0x4e76c2 MOV %R9,0x8(%R14,%R12,8) |
(4443) 0x4e76c7 INC %R12 |
(4443) 0x4e76ca MOV %R8,(%RDI) |
(4443) 0x4e76cd JMP 4e7620 |
0x4e76d2 POP %RBX |
0x4e76d3 POP %R12 |
0x4e76d5 POP %R14 |
0x4e76d7 POP %R15 |
0x4e76d9 POP %RBP |
0x4e76da RET |
0x4e76db NOPL (%RAX,%RAX,1) |
Path / |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 24 |
nb uops | 24 |
loop length | 91 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.10-4.12 |
Stall cycles | 0.00 |
Front-end | 4.00 |
Dispatch | 2.50 |
Overall L1 | 4.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4e76da <hypre_qsort0+0x1aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4e758c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | hypre_qsort.c:31-187 |
Module | exec |
nb instructions | 24 |
nb uops | 24 |
loop length | 91 |
used x86 registers | 10 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.00 cycles |
front end | 4.00 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
cycles | 1.00 | 0.40 | 2.00 | 2.00 | 2.50 | 0.40 | 1.00 | 2.50 | 2.50 | 2.50 | 0.20 | 2.00 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.10-4.12 |
Stall cycles | 0.00 |
Front-end | 4.00 |
Dispatch | 2.50 |
Overall L1 | 4.00 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
CMP %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 4e76da <hypre_qsort0+0x1aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RDX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RDI,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA 0x20(%RDI),%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
JMP 4e758c <hypre_qsort0+0x5c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_qsort0– | 0.01 | 0 |
▼Loop 4441 - hypre_qsort.c:31-186 - exec– | 0 | 0.01 |
○Loop 4443 - hypre_qsort.c:31-182 - exec | 0.01 | 0.05 |
○Loop 4442 - hypre_qsort.c:31-182 - exec | 0 | 0 |