Loop Id: 646 | Module: exec | Source: par_multi_interp.c:1774-1876 | Coverage: 0.32% |
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Loop Id: 646 | Module: exec | Source: par_multi_interp.c:1774-1876 | Coverage: 0.32% |
---|
0x46dcc8 MOV 0xf8(%RSP),%RCX |
0x46dcd0 MOV 0xd0(%RSP),%R8 |
0x46dcd8 MOV 0x78(%RSP),%RDX |
0x46dcdd MOV (%RCX),%RDI |
0x46dce0 LEA (,%RDI,8),%RAX |
0x46dce8 MOV (%RDX,%RDI,8),%RDX |
0x46dcec LEA 0x8(%RAX),%RCX |
0x46dcf0 MOV %RAX,0x148(%RSP) |
0x46dcf8 ADD %R8,%RAX |
0x46dcfb LEA (%R8,%RCX,1),%RSI |
0x46dcff MOV %RAX,0xb8(%RSP) |
0x46dd07 MOV (%RAX),%RAX |
0x46dd0a MOV (%RSI),%R8 |
0x46dd0d MOV %RSI,0xc0(%RSP) |
0x46dd15 ADD %RDX,%R8 |
0x46dd18 SUB %RAX,%R8 |
0x46dd1b CMP %R8,%RDX |
0x46dd1e JGE 46df23 |
0x46dd24 MOV %RAX,%RSI |
0x46dd27 SUB %RDX,%RSI |
0x46dd2a SUB %RAX,%RDX |
0x46dd2d MOV %RDX,0x158(%RSP) |
0x46dd35 ADD %R8,%RSI |
0x46dd38 MOV 0xe0(%RSP),%RDX |
0x46dd40 MOV 0x40(%RSP),%R8 |
0x46dd45 MOV (%R8,%RDX,1),%R8 |
0x46dd49 MOV 0x158(%RSP),%RDX |
0x46dd51 LEA (%R8,%RDX,8),%RDX |
0x46dd55 MOV %RSI,%R8 |
0x46dd58 SUB %RAX,%R8 |
0x46dd5b AND $0x7,%R8D |
0x46dd5f JE 46de42 |
0x46dd65 CMP $0x1,%R8 |
0x46dd69 JE 46de21 |
0x46dd6f CMP $0x2,%R8 |
0x46dd73 JE 46de09 |
0x46dd79 CMP $0x3,%R8 |
0x46dd7d JE 46ddf1 |
0x46dd7f CMP $0x4,%R8 |
0x46dd83 JE 46ddd9 |
0x46dd85 CMP $0x5,%R8 |
0x46dd89 JE 46ddc1 |
0x46dd8b CMP $0x6,%R8 |
0x46dd8f JE 46dda9 |
0x46dd91 MOV (%RDX,%RAX,8),%R8 |
0x46dd95 MOV %RAX,(%R9,%R8,8) |
0x46dd99 MOVQ $0,(%R12,%RAX,8) |
0x46dda1 INC %RAX |
0x46dda4 MOV %R8,-0x8(%R13,%RAX,8) |
0x46dda9 MOV (%RDX,%RAX,8),%R8 |
0x46ddad MOV %RAX,(%R9,%R8,8) |
0x46ddb1 MOVQ $0,(%R12,%RAX,8) |
0x46ddb9 INC %RAX |
0x46ddbc MOV %R8,-0x8(%R13,%RAX,8) |
0x46ddc1 MOV (%RDX,%RAX,8),%R8 |
0x46ddc5 MOV %RAX,(%R9,%R8,8) |
0x46ddc9 MOVQ $0,(%R12,%RAX,8) |
0x46ddd1 INC %RAX |
0x46ddd4 MOV %R8,-0x8(%R13,%RAX,8) |
0x46ddd9 MOV (%RDX,%RAX,8),%R8 |
0x46dddd MOV %RAX,(%R9,%R8,8) |
0x46dde1 MOVQ $0,(%R12,%RAX,8) |
0x46dde9 INC %RAX |
0x46ddec MOV %R8,-0x8(%R13,%RAX,8) |
0x46ddf1 MOV (%RDX,%RAX,8),%R8 |
0x46ddf5 MOV %RAX,(%R9,%R8,8) |
0x46ddf9 MOVQ $0,(%R12,%RAX,8) |
0x46de01 INC %RAX |
0x46de04 MOV %R8,-0x8(%R13,%RAX,8) |
0x46de09 MOV (%RDX,%RAX,8),%R8 |
0x46de0d MOV %RAX,(%R9,%R8,8) |
0x46de11 MOVQ $0,(%R12,%RAX,8) |
0x46de19 INC %RAX |
0x46de1c MOV %R8,-0x8(%R13,%RAX,8) |
0x46de21 MOV (%RDX,%RAX,8),%R8 |
0x46de25 MOV %RAX,(%R9,%R8,8) |
0x46de29 MOVQ $0,(%R12,%RAX,8) |
0x46de31 INC %RAX |
0x46de34 MOV %R8,-0x8(%R13,%RAX,8) |
0x46de39 CMP %RSI,%RAX |
0x46de3c JE 46df23 |
0x46de42 MOV %RBX,0x158(%RSP) |
(657) 0x46de4a MOV (%RDX,%RAX,8),%RBX |
(657) 0x46de4e LEA 0x1(%RAX),%R8 |
(657) 0x46de52 MOV %RAX,(%R9,%RBX,8) |
(657) 0x46de56 MOVQ $0,(%R12,%RAX,8) |
(657) 0x46de5e MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46de63 MOV (%RDX,%R8,8),%RBX |
(657) 0x46de67 MOV %R8,(%R9,%RBX,8) |
(657) 0x46de6b MOVQ $0,(%R12,%R8,8) |
(657) 0x46de73 LEA 0x2(%RAX),%R8 |
(657) 0x46de77 MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46de7c MOV (%RDX,%R8,8),%RBX |
(657) 0x46de80 MOV %R8,(%R9,%RBX,8) |
(657) 0x46de84 MOVQ $0,(%R12,%R8,8) |
(657) 0x46de8c LEA 0x3(%RAX),%R8 |
(657) 0x46de90 MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46de95 MOV (%RDX,%R8,8),%RBX |
(657) 0x46de99 MOV %R8,(%R9,%RBX,8) |
(657) 0x46de9d MOVQ $0,(%R12,%R8,8) |
(657) 0x46dea5 LEA 0x4(%RAX),%R8 |
(657) 0x46dea9 MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46deae MOV (%RDX,%R8,8),%RBX |
(657) 0x46deb2 MOV %R8,(%R9,%RBX,8) |
(657) 0x46deb6 MOVQ $0,(%R12,%R8,8) |
(657) 0x46debe LEA 0x5(%RAX),%R8 |
(657) 0x46dec2 MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46dec7 MOV (%RDX,%R8,8),%RBX |
(657) 0x46decb MOV %R8,(%R9,%RBX,8) |
(657) 0x46decf MOVQ $0,(%R12,%R8,8) |
(657) 0x46ded7 LEA 0x6(%RAX),%R8 |
(657) 0x46dedb MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46dee0 MOV (%RDX,%R8,8),%RBX |
(657) 0x46dee4 MOV %R8,(%R9,%RBX,8) |
(657) 0x46dee8 MOVQ $0,(%R12,%R8,8) |
(657) 0x46def0 LEA 0x7(%RAX),%R8 |
(657) 0x46def4 ADD $0x8,%RAX |
(657) 0x46def8 MOV %RBX,-0x8(%R13,%R8,8) |
(657) 0x46defd MOV (%RDX,%R8,8),%RBX |
(657) 0x46df01 MOV %R8,(%R9,%RBX,8) |
(657) 0x46df05 MOVQ $0,(%R12,%R8,8) |
(657) 0x46df0d MOV %RBX,-0x8(%R13,%RAX,8) |
(657) 0x46df12 CMP %RSI,%RAX |
(657) 0x46df15 JNE 46de4a |
0x46df1b MOV 0x158(%RSP),%RBX |
0x46df23 MOV 0x80(%RSP),%RAX |
0x46df2b MOV 0x148(%RSP),%R8 |
0x46df33 MOV (%RAX,%RDI,8),%RDX |
0x46df37 MOV 0xd8(%RSP),%RAX |
0x46df3f LEA (%RAX,%RCX,1),%RSI |
0x46df43 ADD %R8,%RAX |
0x46df46 MOV (%RSI),%R8 |
0x46df49 MOV %RAX,0xa8(%RSP) |
0x46df51 MOV (%RAX),%RAX |
0x46df54 MOV %RSI,0xb0(%RSP) |
0x46df5c ADD %RDX,%R8 |
0x46df5f SUB %RAX,%R8 |
0x46df62 CMP %R8,%RDX |
0x46df65 JGE 46e16a |
0x46df6b MOV %RAX,%RSI |
0x46df6e SUB %RDX,%RSI |
0x46df71 SUB %RAX,%RDX |
0x46df74 MOV %RDX,0x158(%RSP) |
0x46df7c ADD %R8,%RSI |
0x46df7f MOV 0xe0(%RSP),%RDX |
0x46df87 MOV 0x48(%RSP),%R8 |
0x46df8c MOV (%R8,%RDX,1),%R8 |
0x46df90 MOV 0x158(%RSP),%RDX |
0x46df98 LEA (%R8,%RDX,8),%RDX |
0x46df9c MOV %RSI,%R8 |
0x46df9f SUB %RAX,%R8 |
0x46dfa2 AND $0x7,%R8D |
0x46dfa6 JE 46e089 |
0x46dfac CMP $0x1,%R8 |
0x46dfb0 JE 46e068 |
0x46dfb6 CMP $0x2,%R8 |
0x46dfba JE 46e050 |
0x46dfc0 CMP $0x3,%R8 |
0x46dfc4 JE 46e038 |
0x46dfc6 CMP $0x4,%R8 |
0x46dfca JE 46e020 |
0x46dfcc CMP $0x5,%R8 |
0x46dfd0 JE 46e008 |
0x46dfd2 CMP $0x6,%R8 |
0x46dfd6 JE 46dff0 |
0x46dfd8 MOV (%RDX,%RAX,8),%R8 |
0x46dfdc MOV %RAX,(%RBX,%R8,8) |
0x46dfe0 MOVQ $0,(%R11,%RAX,8) |
0x46dfe8 INC %RAX |
0x46dfeb MOV %R8,-0x8(%R10,%RAX,8) |
0x46dff0 MOV (%RDX,%RAX,8),%R8 |
0x46dff4 MOV %RAX,(%RBX,%R8,8) |
0x46dff8 MOVQ $0,(%R11,%RAX,8) |
0x46e000 INC %RAX |
0x46e003 MOV %R8,-0x8(%R10,%RAX,8) |
0x46e008 MOV (%RDX,%RAX,8),%R8 |
0x46e00c MOV %RAX,(%RBX,%R8,8) |
0x46e010 MOVQ $0,(%R11,%RAX,8) |
0x46e018 INC %RAX |
0x46e01b MOV %R8,-0x8(%R10,%RAX,8) |
0x46e020 MOV (%RDX,%RAX,8),%R8 |
0x46e024 MOV %RAX,(%RBX,%R8,8) |
0x46e028 MOVQ $0,(%R11,%RAX,8) |
0x46e030 INC %RAX |
0x46e033 MOV %R8,-0x8(%R10,%RAX,8) |
0x46e038 MOV (%RDX,%RAX,8),%R8 |
0x46e03c MOV %RAX,(%RBX,%R8,8) |
0x46e040 MOVQ $0,(%R11,%RAX,8) |
0x46e048 INC %RAX |
0x46e04b MOV %R8,-0x8(%R10,%RAX,8) |
0x46e050 MOV (%RDX,%RAX,8),%R8 |
0x46e054 MOV %RAX,(%RBX,%R8,8) |
0x46e058 MOVQ $0,(%R11,%RAX,8) |
0x46e060 INC %RAX |
0x46e063 MOV %R8,-0x8(%R10,%RAX,8) |
0x46e068 MOV (%RDX,%RAX,8),%R8 |
0x46e06c MOV %RAX,(%RBX,%R8,8) |
0x46e070 MOVQ $0,(%R11,%RAX,8) |
0x46e078 INC %RAX |
0x46e07b MOV %R8,-0x8(%R10,%RAX,8) |
0x46e080 CMP %RSI,%RAX |
0x46e083 JE 46e16a |
0x46e089 MOV %R9,0x158(%RSP) |
(656) 0x46e091 MOV (%RDX,%RAX,8),%R9 |
(656) 0x46e095 LEA 0x1(%RAX),%R8 |
(656) 0x46e099 MOV %RAX,(%RBX,%R9,8) |
(656) 0x46e09d MOVQ $0,(%R11,%RAX,8) |
(656) 0x46e0a5 MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e0aa MOV (%RDX,%R8,8),%R9 |
(656) 0x46e0ae MOV %R8,(%RBX,%R9,8) |
(656) 0x46e0b2 MOVQ $0,(%R11,%R8,8) |
(656) 0x46e0ba LEA 0x2(%RAX),%R8 |
(656) 0x46e0be MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e0c3 MOV (%RDX,%R8,8),%R9 |
(656) 0x46e0c7 MOV %R8,(%RBX,%R9,8) |
(656) 0x46e0cb MOVQ $0,(%R11,%R8,8) |
(656) 0x46e0d3 LEA 0x3(%RAX),%R8 |
(656) 0x46e0d7 MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e0dc MOV (%RDX,%R8,8),%R9 |
(656) 0x46e0e0 MOV %R8,(%RBX,%R9,8) |
(656) 0x46e0e4 MOVQ $0,(%R11,%R8,8) |
(656) 0x46e0ec LEA 0x4(%RAX),%R8 |
(656) 0x46e0f0 MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e0f5 MOV (%RDX,%R8,8),%R9 |
(656) 0x46e0f9 MOV %R8,(%RBX,%R9,8) |
(656) 0x46e0fd MOVQ $0,(%R11,%R8,8) |
(656) 0x46e105 LEA 0x5(%RAX),%R8 |
(656) 0x46e109 MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e10e MOV (%RDX,%R8,8),%R9 |
(656) 0x46e112 MOV %R8,(%RBX,%R9,8) |
(656) 0x46e116 MOVQ $0,(%R11,%R8,8) |
(656) 0x46e11e LEA 0x6(%RAX),%R8 |
(656) 0x46e122 MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e127 MOV (%RDX,%R8,8),%R9 |
(656) 0x46e12b MOV %R8,(%RBX,%R9,8) |
(656) 0x46e12f MOVQ $0,(%R11,%R8,8) |
(656) 0x46e137 LEA 0x7(%RAX),%R8 |
(656) 0x46e13b ADD $0x8,%RAX |
(656) 0x46e13f MOV %R9,-0x8(%R10,%R8,8) |
(656) 0x46e144 MOV (%RDX,%R8,8),%R9 |
(656) 0x46e148 MOV %R8,(%RBX,%R9,8) |
(656) 0x46e14c MOVQ $0,(%R11,%R8,8) |
(656) 0x46e154 MOV %R9,-0x8(%R10,%RAX,8) |
(656) 0x46e159 CMP %RSI,%RAX |
(656) 0x46e15c JNE 46e091 |
0x46e162 MOV 0x158(%RSP),%R9 |
0x46e16a MOV 0x68(%RSP),%RSI |
0x46e16f LEA (%RSI,%RCX,1),%R8 |
0x46e173 MOV (%RSI,%RDI,8),%RAX |
0x46e177 MOV (%R8),%RSI |
0x46e17a CMP %RSI,%RAX |
0x46e17d JGE 46e1be |
0x46e17f MOV %RCX,0x158(%RSP) |
0x46e187 NOPW (%RAX,%RAX,1) |
(655) 0x46e190 MOV 0x120(%RSP),%RCX |
(655) 0x46e198 MOV (%RCX,%RAX,8),%RDX |
(655) 0x46e19c MOV 0x130(%RSP),%RCX |
(655) 0x46e1a4 CMP (%RCX,%RDX,8),%R14 |
(655) 0x46e1a8 JE 46e2f0 |
(655) 0x46e1ae INC %RAX |
(655) 0x46e1b1 CMP %RSI,%RAX |
(655) 0x46e1b4 JL 46e190 |
0x46e1b6 MOV 0x158(%RSP),%RCX |
0x46e1be MOV 0x70(%RSP),%R8 |
0x46e1c3 ADD %R8,%RCX |
0x46e1c6 MOV (%R8,%RDI,8),%RAX |
0x46e1ca MOV (%RCX),%RSI |
0x46e1cd CMP %RSI,%RAX |
0x46e1d0 JGE 46e1fe |
0x46e1d2 NOPW (%RAX,%RAX,1) |
(654) 0x46e1d8 MOV 0x128(%RSP),%RDX |
(654) 0x46e1e0 MOV 0x138(%RSP),%R8 |
(654) 0x46e1e8 MOV (%RDX,%RAX,8),%RDX |
(654) 0x46e1ec CMP (%R8,%RDX,8),%R14 |
(654) 0x46e1f0 JE 46e310 |
(654) 0x46e1f6 INC %RAX |
(654) 0x46e1f9 CMP %RSI,%RAX |
(654) 0x46e1fc JL 46e1d8 |
0x46e1fe MOV 0x58(%RSP),%RCX |
0x46e203 MOV 0x148(%RSP),%RDX |
0x46e20b MOV (%RCX,%RDI,8),%R8 |
0x46e20f MOV 0x8(%RCX,%RDX,1),%RDX |
0x46e214 LEA 0x1(%R8),%RAX |
0x46e218 CMP %RDX,%RAX |
0x46e21b JGE 46edfc |
0x46e221 MOV 0x20(%RSP),%RCX |
0x46e226 SAL $0x3,%RAX |
0x46e22a VXORPD %XMM0,%XMM0,%XMM0 |
0x46e22e MOV %R15,0xa0(%RSP) |
0x46e236 MOV %R8,0x98(%RSP) |
0x46e23e VMOVSD %XMM0,%XMM0,%XMM1 |
0x46e242 LEA (%RCX,%RAX,1),%RSI |
0x46e246 LEA (%RCX,%RDX,8),%RDX |
0x46e24a MOV %RSI,0xe8(%RSP) |
0x46e252 MOV 0xc8(%RSP),%RSI |
0x46e25a MOV %RDX,0x158(%RSP) |
0x46e262 ADD %RSI,%RAX |
0x46e265 MOV 0xe8(%RSP),%RSI |
0x46e26d MOV %R14,0xe8(%RSP) |
0x46e275 JMP 46e2b0 |
(651) 0x46e280 MOV 0x108(%RSP),%RDX |
(651) 0x46e288 MOV 0x148(%RSP),%R8 |
(651) 0x46e290 MOV (%RDX,%RCX,8),%RCX |
(651) 0x46e294 CMP %RCX,(%RDX,%R8,1) |
(651) 0x46e298 JE 46e2e3 |
(651) 0x46e29a ADD $0x8,%RSI |
(651) 0x46e29e ADD $0x8,%RAX |
(651) 0x46e2a2 CMP %RSI,0x158(%RSP) |
(651) 0x46e2aa JE 46e630 |
(651) 0x46e2b0 MOV (%RSI),%RCX |
(651) 0x46e2b3 MOV 0x150(%RSP),%R15 |
(651) 0x46e2bb LEA (,%RCX,8),%R8 |
(651) 0x46e2c3 CMP (%R15,%RCX,8),%RDI |
(651) 0x46e2c7 JE 46e330 |
(651) 0x46e2c9 MOV 0x110(%RSP),%R14 |
(651) 0x46e2d1 CMPQ $-0x3,(%R14,%RCX,8) |
(651) 0x46e2d6 JE 46e29a |
(651) 0x46e2d8 CMPQ $0x1,0x140(%RSP) |
(651) 0x46e2e1 JNE 46e280 |
(651) 0x46e2e3 VADDSD (%RAX),%XMM0,%XMM0 |
(651) 0x46e2e7 JMP 46e29a |
(655) 0x46e2f0 MOV 0x150(%RSP),%RSI |
(655) 0x46e2f8 INC %RAX |
(655) 0x46e2fb MOV %RDI,(%RSI,%RDX,8) |
(655) 0x46e2ff MOV (%R8),%RSI |
(655) 0x46e302 CMP %RAX,%RSI |
(655) 0x46e305 JG 46e190 |
0x46e30b JMP 46e1b6 |
(654) 0x46e310 MOV 0x118(%RSP),%RSI |
(654) 0x46e318 INC %RAX |
(654) 0x46e31b MOV %RDI,(%RSI,%RDX,8) |
(654) 0x46e31f MOV (%RCX),%RSI |
(654) 0x46e322 CMP %RAX,%RSI |
(654) 0x46e325 JG 46e1d8 |
0x46e32b JMP 46e1fe |
(651) 0x46e330 MOV 0xd0(%RSP),%R15 |
(651) 0x46e338 MOV (%R15,%RCX,8),%RDX |
(651) 0x46e33c MOV 0x8(%R15,%R8,1),%R15 |
(651) 0x46e341 CMP %R15,%RDX |
(651) 0x46e344 JGE 46e4b3 |
(651) 0x46e34a MOV %R15,%R14 |
(651) 0x46e34d SUB %RDX,%R14 |
(651) 0x46e350 AND $0x3,%R14D |
(651) 0x46e354 JE 46e3f7 |
(651) 0x46e35a CMP $0x1,%R14 |
(651) 0x46e35e JE 46e3c0 |
(651) 0x46e360 CMP $0x2,%R14 |
(651) 0x46e364 JE 46e392 |
(651) 0x46e366 MOV (%R13,%RDX,8),%R14 |
(651) 0x46e36b VMOVSD (%RAX),%XMM5 |
(651) 0x46e36f VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
(651) 0x46e375 INC %RDX |
(651) 0x46e378 MOV (%R9,%R14,8),%R14 |
(651) 0x46e37c LEA (%R12,%R14,8),%R14 |
(651) 0x46e380 VADDSD (%R14),%XMM6,%XMM7 |
(651) 0x46e385 VADDSD %XMM6,%XMM1,%XMM1 |
(651) 0x46e389 VADDSD %XMM6,%XMM0,%XMM0 |
(651) 0x46e38d VMOVSD %XMM7,(%R14) |
(651) 0x46e392 MOV (%R13,%RDX,8),%R14 |
(651) 0x46e397 VMOVSD (%RAX),%XMM8 |
(651) 0x46e39b VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
(651) 0x46e3a1 INC %RDX |
(651) 0x46e3a4 MOV (%R9,%R14,8),%R14 |
(651) 0x46e3a8 LEA (%R12,%R14,8),%R14 |
(651) 0x46e3ac VADDSD (%R14),%XMM9,%XMM10 |
(651) 0x46e3b1 VADDSD %XMM9,%XMM1,%XMM1 |
(651) 0x46e3b6 VADDSD %XMM9,%XMM0,%XMM0 |
(651) 0x46e3bb VMOVSD %XMM10,(%R14) |
(651) 0x46e3c0 MOV (%R13,%RDX,8),%R14 |
(651) 0x46e3c5 VMOVSD (%RAX),%XMM11 |
(651) 0x46e3c9 VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
(651) 0x46e3cf INC %RDX |
(651) 0x46e3d2 MOV (%R9,%R14,8),%R14 |
(651) 0x46e3d6 LEA (%R12,%R14,8),%R14 |
(651) 0x46e3da VADDSD (%R14),%XMM12,%XMM13 |
(651) 0x46e3df VADDSD %XMM12,%XMM1,%XMM1 |
(651) 0x46e3e4 VADDSD %XMM12,%XMM0,%XMM0 |
(651) 0x46e3e9 VMOVSD %XMM13,(%R14) |
(651) 0x46e3ee CMP %R15,%RDX |
(651) 0x46e3f1 JE 46e4b3 |
(653) 0x46e3f7 MOV (%R13,%RDX,8),%R14 |
(653) 0x46e3fc VMOVSD (%RAX),%XMM14 |
(653) 0x46e400 VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(653) 0x46e406 MOV (%R9,%R14,8),%R14 |
(653) 0x46e40a LEA (%R12,%R14,8),%R14 |
(653) 0x46e40e VADDSD (%R14),%XMM15,%XMM2 |
(653) 0x46e413 VADDSD %XMM15,%XMM1,%XMM6 |
(653) 0x46e418 VADDSD %XMM15,%XMM0,%XMM7 |
(653) 0x46e41d VMOVSD %XMM2,(%R14) |
(653) 0x46e422 MOV 0x8(%R13,%RDX,8),%R14 |
(653) 0x46e427 VMOVSD (%RAX),%XMM5 |
(653) 0x46e42b VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(653) 0x46e432 MOV (%R9,%R14,8),%R14 |
(653) 0x46e436 LEA (%R12,%R14,8),%R14 |
(653) 0x46e43a VADDSD (%R14),%XMM8,%XMM9 |
(653) 0x46e43f VADDSD %XMM8,%XMM6,%XMM10 |
(653) 0x46e444 VADDSD %XMM8,%XMM7,%XMM11 |
(653) 0x46e449 VMOVSD %XMM9,(%R14) |
(653) 0x46e44e MOV 0x10(%R13,%RDX,8),%R14 |
(653) 0x46e453 VMOVSD (%RAX),%XMM12 |
(653) 0x46e457 VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(653) 0x46e45e MOV (%R9,%R14,8),%R14 |
(653) 0x46e462 LEA (%R12,%R14,8),%R14 |
(653) 0x46e466 VADDSD (%R14),%XMM13,%XMM1 |
(653) 0x46e46b VADDSD %XMM13,%XMM10,%XMM14 |
(653) 0x46e470 VADDSD %XMM13,%XMM11,%XMM0 |
(653) 0x46e475 VMOVSD %XMM1,(%R14) |
(653) 0x46e47a MOV 0x18(%R13,%RDX,8),%R14 |
(653) 0x46e47f VMOVSD (%RAX),%XMM15 |
(653) 0x46e483 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(653) 0x46e48a ADD $0x4,%RDX |
(653) 0x46e48e MOV (%R9,%R14,8),%R14 |
(653) 0x46e492 LEA (%R12,%R14,8),%R14 |
(653) 0x46e496 VADDSD (%R14),%XMM12,%XMM2 |
(653) 0x46e49b VADDSD %XMM12,%XMM14,%XMM1 |
(653) 0x46e4a0 VADDSD %XMM12,%XMM0,%XMM0 |
(653) 0x46e4a5 VMOVSD %XMM2,(%R14) |
(653) 0x46e4aa CMP %R15,%RDX |
(653) 0x46e4ad JNE 46e3f7 |
(651) 0x46e4b3 MOV 0xd8(%RSP),%R15 |
(651) 0x46e4bb MOV (%R15,%RCX,8),%RDX |
(651) 0x46e4bf MOV 0x8(%R15,%R8,1),%R8 |
(651) 0x46e4c4 CMP %R8,%RDX |
(651) 0x46e4c7 JGE 46e29a |
(651) 0x46e4cd MOV %R8,%RCX |
(651) 0x46e4d0 SUB %RDX,%RCX |
(651) 0x46e4d3 AND $0x3,%ECX |
(651) 0x46e4d6 JE 46e570 |
(651) 0x46e4dc CMP $0x1,%RCX |
(651) 0x46e4e0 JE 46e53c |
(651) 0x46e4e2 CMP $0x2,%RCX |
(651) 0x46e4e6 JE 46e511 |
(651) 0x46e4e8 MOV (%R10,%RDX,8),%R14 |
(651) 0x46e4ec VMOVSD (%RAX),%XMM6 |
(651) 0x46e4f0 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
(651) 0x46e4f6 INC %RDX |
(651) 0x46e4f9 MOV (%RBX,%R14,8),%R15 |
(651) 0x46e4fd LEA (%R11,%R15,8),%RCX |
(651) 0x46e501 VADDSD (%RCX),%XMM7,%XMM5 |
(651) 0x46e505 VADDSD %XMM7,%XMM1,%XMM1 |
(651) 0x46e509 VADDSD %XMM7,%XMM0,%XMM0 |
(651) 0x46e50d VMOVSD %XMM5,(%RCX) |
(651) 0x46e511 MOV (%R10,%RDX,8),%R14 |
(651) 0x46e515 VMOVSD (%RAX),%XMM8 |
(651) 0x46e519 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
(651) 0x46e51f INC %RDX |
(651) 0x46e522 MOV (%RBX,%R14,8),%R15 |
(651) 0x46e526 LEA (%R11,%R15,8),%RCX |
(651) 0x46e52a VADDSD (%RCX),%XMM9,%XMM10 |
(651) 0x46e52e VADDSD %XMM9,%XMM1,%XMM1 |
(651) 0x46e533 VADDSD %XMM9,%XMM0,%XMM0 |
(651) 0x46e538 VMOVSD %XMM10,(%RCX) |
(651) 0x46e53c MOV (%R10,%RDX,8),%R14 |
(651) 0x46e540 VMOVSD (%RAX),%XMM11 |
(651) 0x46e544 VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
(651) 0x46e54a INC %RDX |
(651) 0x46e54d MOV (%RBX,%R14,8),%R15 |
(651) 0x46e551 LEA (%R11,%R15,8),%RCX |
(651) 0x46e555 VADDSD (%RCX),%XMM12,%XMM13 |
(651) 0x46e559 VADDSD %XMM12,%XMM1,%XMM1 |
(651) 0x46e55e VADDSD %XMM12,%XMM0,%XMM0 |
(651) 0x46e563 VMOVSD %XMM13,(%RCX) |
(651) 0x46e567 CMP %R8,%RDX |
(651) 0x46e56a JE 46e29a |
(652) 0x46e570 MOV (%R10,%RDX,8),%R14 |
(652) 0x46e574 VMOVSD (%RAX),%XMM12 |
(652) 0x46e578 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(652) 0x46e57e MOV (%RBX,%R14,8),%R15 |
(652) 0x46e582 MOV 0x8(%R10,%RDX,8),%R14 |
(652) 0x46e587 LEA (%R11,%R15,8),%RCX |
(652) 0x46e58b MOV (%RBX,%R14,8),%R15 |
(652) 0x46e58f MOV 0x10(%R10,%RDX,8),%R14 |
(652) 0x46e594 VADDSD (%RCX),%XMM14,%XMM15 |
(652) 0x46e598 VADDSD %XMM14,%XMM1,%XMM1 |
(652) 0x46e59d VADDSD %XMM14,%XMM0,%XMM0 |
(652) 0x46e5a2 VMOVSD %XMM15,(%RCX) |
(652) 0x46e5a6 LEA (%R11,%R15,8),%RCX |
(652) 0x46e5aa VMOVSD (%RAX),%XMM2 |
(652) 0x46e5ae MOV (%RBX,%R14,8),%R15 |
(652) 0x46e5b2 VMULSD 0x8(%R11,%RDX,8),%XMM2,%XMM6 |
(652) 0x46e5b9 MOV 0x18(%R10,%RDX,8),%R14 |
(652) 0x46e5be VADDSD (%RCX),%XMM6,%XMM7 |
(652) 0x46e5c2 VMOVSD %XMM7,(%RCX) |
(652) 0x46e5c6 LEA (%R11,%R15,8),%RCX |
(652) 0x46e5ca VMOVSD (%RAX),%XMM5 |
(652) 0x46e5ce MOV (%RBX,%R14,8),%R15 |
(652) 0x46e5d2 VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(652) 0x46e5d9 VADDSD %XMM6,%XMM1,%XMM8 |
(652) 0x46e5dd VADDSD %XMM6,%XMM0,%XMM9 |
(652) 0x46e5e1 VADDSD (%RCX),%XMM10,%XMM11 |
(652) 0x46e5e5 VMOVSD %XMM11,(%RCX) |
(652) 0x46e5e9 VMOVSD (%RAX),%XMM12 |
(652) 0x46e5ed VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(652) 0x46e5f4 LEA (%R11,%R15,8),%RCX |
(652) 0x46e5f8 VADDSD %XMM10,%XMM8,%XMM13 |
(652) 0x46e5fd VADDSD %XMM10,%XMM9,%XMM14 |
(652) 0x46e602 ADD $0x4,%RDX |
(652) 0x46e606 VADDSD (%RCX),%XMM12,%XMM15 |
(652) 0x46e60a VADDSD %XMM12,%XMM13,%XMM1 |
(652) 0x46e60f VADDSD %XMM12,%XMM14,%XMM0 |
(652) 0x46e614 VMOVSD %XMM15,(%RCX) |
(652) 0x46e618 CMP %R8,%RDX |
(652) 0x46e61b JNE 46e570 |
(651) 0x46e621 JMP 46e29a |
0x46e630 MOV 0xa0(%RSP),%R15 |
0x46e638 MOV 0x98(%RSP),%R8 |
0x46e640 MOV 0xe8(%RSP),%R14 |
0x46e648 MOV 0x60(%RSP),%RCX |
0x46e64d MOV 0x148(%RSP),%RAX |
0x46e655 MOV (%RCX,%RDI,8),%RDX |
0x46e659 MOV 0x8(%RCX,%RAX,1),%RCX |
0x46e65e CMP %RCX,%RDX |
0x46e661 JGE 46e763 |
0x46e667 MOV 0x30(%RSP),%RAX |
0x46e66c SAL $0x3,%RDX |
0x46e670 MOV %R10,0xa0(%RSP) |
0x46e678 MOV %R13,0x98(%RSP) |
0x46e680 LEA (%RAX,%RDX,1),%RSI |
0x46e684 MOV %R8,0x90(%RSP) |
0x46e68c MOV %RSI,0x158(%RSP) |
0x46e694 MOV 0x28(%RSP),%RSI |
0x46e699 ADD %RSI,%RDX |
0x46e69c LEA (%RAX,%RCX,8),%RSI |
0x46e6a0 MOV %R14,%RAX |
0x46e6a3 MOV 0x38(%RSP),%R14 |
0x46e6a8 JMP 46e6ec |
(649) 0x46e6b0 MOV 0x108(%RSP),%R10 |
(649) 0x46e6b8 MOV 0x148(%RSP),%R13 |
(649) 0x46e6c0 MOV 0xf0(%RSP),%RCX |
(649) 0x46e6c8 MOV (%R10,%R13,1),%R10 |
(649) 0x46e6cc CMP %R10,(%RCX,%R8,1) |
(649) 0x46e6d0 JE 46e73f |
(649) 0x46e6d2 ADDQ $0x8,0x158(%RSP) |
(649) 0x46e6db ADD $0x8,%RDX |
(649) 0x46e6df MOV 0x158(%RSP),%RCX |
(649) 0x46e6e7 CMP %RSI,%RCX |
(649) 0x46e6ea JE 46e748 |
(649) 0x46e6ec MOV 0x158(%RSP),%R13 |
(649) 0x46e6f4 MOV (%R13),%RCX |
(649) 0x46e6f8 TEST %R15,%R15 |
(649) 0x46e6fb JE 46e709 |
(649) 0x46e6fd MOV 0x100(%RSP),%R10 |
(649) 0x46e705 MOV (%R10,%RCX,8),%RCX |
(649) 0x46e709 LEA (,%RCX,8),%R8 |
(649) 0x46e711 TEST %RCX,%RCX |
(649) 0x46e714 JS 46e729 |
(649) 0x46e716 MOV 0x118(%RSP),%R13 |
(649) 0x46e71e CMP (%R13,%RCX,8),%RDI |
(649) 0x46e723 JE 46eb10 |
(649) 0x46e729 CMPQ $-0x3,(%R14,%R8,1) |
(649) 0x46e72e JE 46e6d2 |
(649) 0x46e730 CMPQ $0x1,0x140(%RSP) |
(649) 0x46e739 JNE 46e6b0 |
(649) 0x46e73f VADDSD (%RDX),%XMM0,%XMM0 |
(649) 0x46e743 JMP 46e6d2 |
0x46e748 MOV 0xa0(%RSP),%R10 |
0x46e750 MOV 0x98(%RSP),%R13 |
0x46e758 MOV %RAX,%R14 |
0x46e75b MOV 0x90(%RSP),%R8 |
0x46e763 MOV 0xc8(%RSP),%RDI |
0x46e76b VMULSD (%RDI,%R8,8),%XMM1,%XMM9 |
0x46e771 VCOMISD %XMM3,%XMM9 |
0x46e775 JE 46e780 |
0x46e777 VXORPD %XMM4,%XMM0,%XMM10 |
0x46e77b VDIVSD %XMM9,%XMM10,%XMM12 |
0x46e780 MOV 0xb8(%RSP),%R8 |
0x46e788 MOV 0xc0(%RSP),%RAX |
0x46e790 MOV (%R8),%RSI |
0x46e793 MOV (%RAX),%RCX |
0x46e796 CMP %RCX,%RSI |
0x46e799 JGE 46e916 |
0x46e79f SUB %RSI,%RCX |
0x46e7a2 MOV %RSI,%RDI |
0x46e7a5 LEA -0x1(%RCX),%RDX |
0x46e7a9 CMP $0x2,%RDX |
0x46e7ad JBE 46ee09 |
0x46e7b3 MOV %RCX,%RDX |
0x46e7b6 LEA (%R12,%RSI,8),%RAX |
0x46e7ba VBROADCASTSD %XMM12,%YMM5 |
0x46e7bf SHR $0x2,%RDX |
0x46e7c3 SAL $0x5,%RDX |
0x46e7c7 LEA (%RDX,%RAX,1),%R8 |
0x46e7cb SUB $0x20,%RDX |
0x46e7cf SHR $0x5,%RDX |
0x46e7d3 INC %RDX |
0x46e7d6 AND $0x7,%EDX |
0x46e7d9 JE 46e863 |
0x46e7df CMP $0x1,%RDX |
0x46e7e3 JE 46e851 |
0x46e7e5 CMP $0x2,%RDX |
0x46e7e9 JE 46e844 |
0x46e7eb CMP $0x3,%RDX |
0x46e7ef JE 46e837 |
0x46e7f1 CMP $0x4,%RDX |
0x46e7f5 JE 46e82a |
0x46e7f7 CMP $0x5,%RDX |
0x46e7fb JE 46e81d |
0x46e7fd CMP $0x6,%RDX |
0x46e801 JE 46e810 |
0x46e803 VMULPD (%RAX),%YMM5,%YMM11 |
0x46e807 ADD $0x20,%RAX |
0x46e80b VMOVUPD %YMM11,-0x20(%RAX) |
0x46e810 VMULPD (%RAX),%YMM5,%YMM13 |
0x46e814 ADD $0x20,%RAX |
0x46e818 VMOVUPD %YMM13,-0x20(%RAX) |
0x46e81d VMULPD (%RAX),%YMM5,%YMM14 |
0x46e821 ADD $0x20,%RAX |
0x46e825 VMOVUPD %YMM14,-0x20(%RAX) |
0x46e82a VMULPD (%RAX),%YMM5,%YMM15 |
0x46e82e ADD $0x20,%RAX |
0x46e832 VMOVUPD %YMM15,-0x20(%RAX) |
0x46e837 VMULPD (%RAX),%YMM5,%YMM2 |
0x46e83b ADD $0x20,%RAX |
0x46e83f VMOVUPD %YMM2,-0x20(%RAX) |
0x46e844 VMULPD (%RAX),%YMM5,%YMM6 |
0x46e848 ADD $0x20,%RAX |
0x46e84c VMOVUPD %YMM6,-0x20(%RAX) |
0x46e851 VMULPD (%RAX),%YMM5,%YMM7 |
0x46e855 ADD $0x20,%RAX |
0x46e859 VMOVUPD %YMM7,-0x20(%RAX) |
0x46e85e CMP %R8,%RAX |
0x46e861 JE 46e8d2 |
(648) 0x46e863 VMULPD (%RAX),%YMM5,%YMM1 |
(648) 0x46e867 ADD $0x100,%RAX |
(648) 0x46e86d VMULPD -0xe0(%RAX),%YMM5,%YMM0 |
(648) 0x46e875 VMULPD -0xc0(%RAX),%YMM5,%YMM8 |
(648) 0x46e87d VMULPD -0xa0(%RAX),%YMM5,%YMM9 |
(648) 0x46e885 VMULPD -0x80(%RAX),%YMM5,%YMM10 |
(648) 0x46e88a VMULPD -0x60(%RAX),%YMM5,%YMM11 |
(648) 0x46e88f VMOVUPD %YMM1,-0x100(%RAX) |
(648) 0x46e897 VMULPD -0x40(%RAX),%YMM5,%YMM13 |
(648) 0x46e89c VMOVUPD %YMM0,-0xe0(%RAX) |
(648) 0x46e8a4 VMULPD -0x20(%RAX),%YMM5,%YMM14 |
(648) 0x46e8a9 VMOVUPD %YMM8,-0xc0(%RAX) |
(648) 0x46e8b1 VMOVUPD %YMM9,-0xa0(%RAX) |
(648) 0x46e8b9 VMOVUPD %YMM10,-0x80(%RAX) |
(648) 0x46e8be VMOVUPD %YMM11,-0x60(%RAX) |
(648) 0x46e8c3 VMOVUPD %YMM13,-0x40(%RAX) |
(648) 0x46e8c8 VMOVUPD %YMM14,-0x20(%RAX) |
(648) 0x46e8cd CMP %R8,%RAX |
(648) 0x46e8d0 JNE 46e863 |
0x46e8d2 MOV %RCX,%R8 |
0x46e8d5 AND $-0x4,%R8 |
0x46e8d9 ADD %R8,%RSI |
0x46e8dc TEST $0x3,%CL |
0x46e8df JE 46e916 |
0x46e8e1 SUB %R8,%RCX |
0x46e8e4 CMP $0x1,%RCX |
0x46e8e8 JE 46e90a |
0x46e8ea ADD %RDI,%R8 |
0x46e8ed VMOVDDUP %XMM12,%XMM5 |
0x46e8f2 LEA (%R12,%R8,8),%RDI |
0x46e8f6 VMULPD (%RDI),%XMM5,%XMM15 |
0x46e8fa VMOVUPD %XMM15,(%RDI) |
0x46e8fe TEST $0x1,%CL |
0x46e901 JE 46e916 |
0x46e903 AND $-0x2,%RCX |
0x46e907 ADD %RCX,%RSI |
0x46e90a LEA (%R12,%RSI,8),%RSI |
0x46e90e VMULSD (%RSI),%XMM12,%XMM2 |
0x46e912 VMOVSD %XMM2,(%RSI) |
0x46e916 MOV 0xa8(%RSP),%RCX |
0x46e91e MOV 0xb0(%RSP),%RAX |
0x46e926 MOV (%RCX),%RSI |
0x46e929 MOV (%RAX),%RCX |
0x46e92c CMP %RSI,%RCX |
0x46e92f JLE 46eaac |
0x46e935 SUB %RSI,%RCX |
0x46e938 MOV %RSI,%RDI |
0x46e93b LEA -0x1(%RCX),%RDX |
0x46e93f CMP $0x2,%RDX |
0x46e943 JBE 46ee11 |
0x46e949 MOV %RCX,%RDX |
0x46e94c LEA (%R11,%RSI,8),%RAX |
0x46e950 VBROADCASTSD %XMM12,%YMM6 |
0x46e955 SHR $0x2,%RDX |
0x46e959 SAL $0x5,%RDX |
0x46e95d LEA (%RDX,%RAX,1),%R8 |
0x46e961 SUB $0x20,%RDX |
0x46e965 SHR $0x5,%RDX |
0x46e969 INC %RDX |
0x46e96c AND $0x7,%EDX |
0x46e96f JE 46e9f9 |
0x46e975 CMP $0x1,%RDX |
0x46e979 JE 46e9e7 |
0x46e97b CMP $0x2,%RDX |
0x46e97f JE 46e9da |
0x46e981 CMP $0x3,%RDX |
0x46e985 JE 46e9cd |
0x46e987 CMP $0x4,%RDX |
0x46e98b JE 46e9c0 |
0x46e98d CMP $0x5,%RDX |
0x46e991 JE 46e9b3 |
0x46e993 CMP $0x6,%RDX |
0x46e997 JE 46e9a6 |
0x46e999 VMULPD (%RAX),%YMM6,%YMM7 |
0x46e99d ADD $0x20,%RAX |
0x46e9a1 VMOVUPD %YMM7,-0x20(%RAX) |
0x46e9a6 VMULPD (%RAX),%YMM6,%YMM1 |
0x46e9aa ADD $0x20,%RAX |
0x46e9ae VMOVUPD %YMM1,-0x20(%RAX) |
0x46e9b3 VMULPD (%RAX),%YMM6,%YMM0 |
0x46e9b7 ADD $0x20,%RAX |
0x46e9bb VMOVUPD %YMM0,-0x20(%RAX) |
0x46e9c0 VMULPD (%RAX),%YMM6,%YMM8 |
0x46e9c4 ADD $0x20,%RAX |
0x46e9c8 VMOVUPD %YMM8,-0x20(%RAX) |
0x46e9cd VMULPD (%RAX),%YMM6,%YMM9 |
0x46e9d1 ADD $0x20,%RAX |
0x46e9d5 VMOVUPD %YMM9,-0x20(%RAX) |
0x46e9da VMULPD (%RAX),%YMM6,%YMM10 |
0x46e9de ADD $0x20,%RAX |
0x46e9e2 VMOVUPD %YMM10,-0x20(%RAX) |
0x46e9e7 VMULPD (%RAX),%YMM6,%YMM11 |
0x46e9eb ADD $0x20,%RAX |
0x46e9ef VMOVUPD %YMM11,-0x20(%RAX) |
0x46e9f4 CMP %R8,%RAX |
0x46e9f7 JE 46ea68 |
(647) 0x46e9f9 VMULPD (%RAX),%YMM6,%YMM13 |
(647) 0x46e9fd ADD $0x100,%RAX |
(647) 0x46ea03 VMULPD -0xe0(%RAX),%YMM6,%YMM14 |
(647) 0x46ea0b VMULPD -0xc0(%RAX),%YMM6,%YMM5 |
(647) 0x46ea13 VMULPD -0xa0(%RAX),%YMM6,%YMM15 |
(647) 0x46ea1b VMULPD -0x80(%RAX),%YMM6,%YMM2 |
(647) 0x46ea20 VMULPD -0x60(%RAX),%YMM6,%YMM7 |
(647) 0x46ea25 VMOVUPD %YMM13,-0x100(%RAX) |
(647) 0x46ea2d VMULPD -0x40(%RAX),%YMM6,%YMM1 |
(647) 0x46ea32 VMOVUPD %YMM14,-0xe0(%RAX) |
(647) 0x46ea3a VMULPD -0x20(%RAX),%YMM6,%YMM0 |
(647) 0x46ea3f VMOVUPD %YMM5,-0xc0(%RAX) |
(647) 0x46ea47 VMOVUPD %YMM15,-0xa0(%RAX) |
(647) 0x46ea4f VMOVUPD %YMM2,-0x80(%RAX) |
(647) 0x46ea54 VMOVUPD %YMM7,-0x60(%RAX) |
(647) 0x46ea59 VMOVUPD %YMM1,-0x40(%RAX) |
(647) 0x46ea5e VMOVUPD %YMM0,-0x20(%RAX) |
(647) 0x46ea63 CMP %R8,%RAX |
(647) 0x46ea66 JNE 46e9f9 |
0x46ea68 MOV %RCX,%R8 |
0x46ea6b AND $-0x4,%R8 |
0x46ea6f ADD %R8,%RSI |
0x46ea72 TEST $0x3,%CL |
0x46ea75 JE 46eaac |
0x46ea77 SUB %R8,%RCX |
0x46ea7a CMP $0x1,%RCX |
0x46ea7e JE 46eaa0 |
0x46ea80 ADD %RDI,%R8 |
0x46ea83 VMOVDDUP %XMM12,%XMM6 |
0x46ea88 LEA (%R11,%R8,8),%RDI |
0x46ea8c VMULPD (%RDI),%XMM6,%XMM8 |
0x46ea90 VMOVUPD %XMM8,(%RDI) |
0x46ea94 TEST $0x1,%CL |
0x46ea97 JE 46eaac |
0x46ea99 AND $-0x2,%RCX |
0x46ea9d ADD %RCX,%RSI |
0x46eaa0 LEA (%R11,%RSI,8),%RSI |
0x46eaa4 VMULSD (%RSI),%XMM12,%XMM9 |
0x46eaa8 VMOVSD %XMM9,(%RSI) |
0x46eaac ADDQ $0x8,0xf8(%RSP) |
0x46eab5 MOV 0xf8(%RSP),%RCX |
0x46eabd CMP %RCX,0x50(%RSP) |
0x46eac2 JNE 46dcc8 |
(649) 0x46eb10 MOV 0x10(%RSP),%RCX |
(649) 0x46eb15 MOV 0x18(%RSP),%R13 |
(649) 0x46eb1a MOV (%RCX,%R8,1),%RCX |
(649) 0x46eb1e MOV 0x8(%R13,%R8,1),%R10 |
(649) 0x46eb23 ADD %RCX,%R10 |
(649) 0x46eb26 MOV %R10,0xe8(%RSP) |
(649) 0x46eb2e CMP %R10,%RCX |
(649) 0x46eb31 JGE 46e6d2 |
(649) 0x46eb37 MOV 0x8(%RSP),%R8 |
(649) 0x46eb3c MOV 0xe0(%RSP),%R13 |
(649) 0x46eb44 SUB %RCX,%R10 |
(649) 0x46eb47 MOV (%R8,%R13,1),%R8 |
(649) 0x46eb4b AND $0x3,%R10D |
(649) 0x46eb4f JE 46ec34 |
(649) 0x46eb55 CMP $0x1,%R10 |
(649) 0x46eb59 JE 46ebe5 |
(649) 0x46eb5f CMP $0x2,%R10 |
(649) 0x46eb63 JE 46eba4 |
(649) 0x46eb65 MOV 0x88(%RSP),%R13 |
(649) 0x46eb6d MOV (%R8,%RCX,8),%R10 |
(649) 0x46eb71 VMOVSD (%RDX),%XMM2 |
(649) 0x46eb75 VMULSD (%R13,%RCX,8),%XMM2,%XMM6 |
(649) 0x46eb7c TEST %R10,%R10 |
(649) 0x46eb7f JS 46ee19 |
(649) 0x46eb85 MOV (%RBX,%R10,8),%R10 |
(649) 0x46eb89 LEA (%R11,%R10,8),%R13 |
(649) 0x46eb8d VADDSD (%R13),%XMM6,%XMM7 |
(649) 0x46eb93 VMOVSD %XMM7,(%R13) |
(649) 0x46eb99 VADDSD %XMM6,%XMM1,%XMM1 |
(649) 0x46eb9d VADDSD %XMM6,%XMM0,%XMM0 |
(649) 0x46eba1 INC %RCX |
(649) 0x46eba4 MOV 0x88(%RSP),%R13 |
(649) 0x46ebac MOV (%R8,%RCX,8),%R10 |
(649) 0x46ebb0 VMOVSD (%RDX),%XMM9 |
(649) 0x46ebb4 VMULSD (%R13,%RCX,8),%XMM9,%XMM10 |
(649) 0x46ebbb TEST %R10,%R10 |
(649) 0x46ebbe JS 46ede0 |
(649) 0x46ebc4 MOV (%RBX,%R10,8),%R10 |
(649) 0x46ebc8 LEA (%R11,%R10,8),%R13 |
(649) 0x46ebcc VADDSD (%R13),%XMM10,%XMM5 |
(649) 0x46ebd2 VMOVSD %XMM5,(%R13) |
(649) 0x46ebd8 VADDSD %XMM10,%XMM1,%XMM1 |
(649) 0x46ebdd VADDSD %XMM10,%XMM0,%XMM0 |
(649) 0x46ebe2 INC %RCX |
(649) 0x46ebe5 MOV 0x88(%RSP),%R13 |
(649) 0x46ebed MOV (%R8,%RCX,8),%R10 |
(649) 0x46ebf1 VMOVSD (%RDX),%XMM13 |
(649) 0x46ebf5 VMULSD (%R13,%RCX,8),%XMM13,%XMM12 |
(649) 0x46ebfc TEST %R10,%R10 |
(649) 0x46ebff JS 46edb0 |
(649) 0x46ec05 MOV (%RBX,%R10,8),%R10 |
(649) 0x46ec09 LEA (%R11,%R10,8),%R13 |
(649) 0x46ec0d VADDSD (%R13),%XMM12,%XMM14 |
(649) 0x46ec13 VMOVSD %XMM14,(%R13) |
(649) 0x46ec19 VADDSD %XMM12,%XMM1,%XMM1 |
(649) 0x46ec1e VADDSD %XMM12,%XMM0,%XMM0 |
(649) 0x46ec23 INC %RCX |
(649) 0x46ec26 CMP %RCX,0xe8(%RSP) |
(649) 0x46ec2e JE 46e6d2 |
(649) 0x46ec34 MOV %R14,(%RSP) |
(649) 0x46ec38 MOV 0x88(%RSP),%R13 |
(649) 0x46ec40 JMP 46ece6 |
(650) 0x46ec48 MOV (%RBX,%R10,8),%R14 |
(650) 0x46ec4c LEA (%R11,%R14,8),%R10 |
(650) 0x46ec50 VADDSD (%R10),%XMM9,%XMM10 |
(650) 0x46ec55 VMOVSD %XMM10,(%R10) |
(650) 0x46ec5a LEA 0x1(%RCX),%R14 |
(650) 0x46ec5e VMOVSD (%RDX),%XMM14 |
(650) 0x46ec62 VADDSD %XMM9,%XMM1,%XMM11 |
(650) 0x46ec67 MOV (%R8,%R14,8),%R10 |
(650) 0x46ec6b VMULSD (%R13,%R14,8),%XMM14,%XMM15 |
(650) 0x46ec72 VADDSD %XMM9,%XMM0,%XMM13 |
(650) 0x46ec77 TEST %R10,%R10 |
(650) 0x46ec7a JS 46ed90 |
(650) 0x46ec80 MOV (%RBX,%R10,8),%R14 |
(650) 0x46ec84 LEA (%R11,%R14,8),%R10 |
(650) 0x46ec88 VADDSD (%R10),%XMM15,%XMM12 |
(650) 0x46ec8d VMOVSD %XMM12,(%R10) |
(650) 0x46ec92 LEA 0x2(%RCX),%R14 |
(650) 0x46ec96 VMOVSD (%RDX),%XMM1 |
(650) 0x46ec9a VADDSD %XMM15,%XMM11,%XMM6 |
(650) 0x46ec9f MOV (%R8,%R14,8),%R10 |
(650) 0x46eca3 VMULSD (%R13,%R14,8),%XMM1,%XMM12 |
(650) 0x46ecaa VADDSD %XMM15,%XMM13,%XMM7 |
(650) 0x46ecaf TEST %R10,%R10 |
(650) 0x46ecb2 JS 46ed70 |
(650) 0x46ecb8 MOV (%RBX,%R10,8),%R14 |
(650) 0x46ecbc LEA (%R11,%R14,8),%R10 |
(650) 0x46ecc0 VADDSD (%R10),%XMM12,%XMM0 |
(650) 0x46ecc5 VMOVSD %XMM0,(%R10) |
(650) 0x46ecca VADDSD %XMM12,%XMM6,%XMM1 |
(650) 0x46eccf VADDSD %XMM12,%XMM7,%XMM0 |
(650) 0x46ecd4 ADD $0x3,%RCX |
(650) 0x46ecd8 CMP %RCX,0xe8(%RSP) |
(650) 0x46ece0 JE 46edd0 |
(650) 0x46ece6 MOV (%R8,%RCX,8),%R14 |
(650) 0x46ecea VMOVSD (%RDX),%XMM12 |
(650) 0x46ecee VMULSD (%R13,%RCX,8),%XMM12,%XMM2 |
(650) 0x46ecf5 TEST %R14,%R14 |
(650) 0x46ecf8 JS 46ed50 |
(650) 0x46ecfa MOV (%RBX,%R14,8),%R10 |
(650) 0x46ecfe LEA (%R11,%R10,8),%R14 |
(650) 0x46ed02 VADDSD (%R14),%XMM2,%XMM6 |
(650) 0x46ed07 VMOVSD %XMM6,(%R14) |
(650) 0x46ed0c INC %RCX |
(650) 0x46ed0f VMOVSD (%RDX),%XMM8 |
(650) 0x46ed13 VADDSD %XMM2,%XMM1,%XMM1 |
(650) 0x46ed17 VADDSD %XMM2,%XMM0,%XMM0 |
(650) 0x46ed1b MOV (%R8,%RCX,8),%R10 |
(650) 0x46ed1f VMULSD (%R13,%RCX,8),%XMM8,%XMM9 |
(650) 0x46ed26 TEST %R10,%R10 |
(650) 0x46ed29 JNS 46ec48 |
(650) 0x46ed2f NOT %R10 |
(650) 0x46ed32 MOV (%R9,%R10,8),%R14 |
(650) 0x46ed36 LEA (%R12,%R14,8),%R10 |
(650) 0x46ed3a VADDSD (%R10),%XMM9,%XMM5 |
(650) 0x46ed3f VMOVSD %XMM5,(%R10) |
(650) 0x46ed44 JMP 46ec5a |
(650) 0x46ed50 NOT %R14 |
(650) 0x46ed53 MOV (%R9,%R14,8),%R10 |
(650) 0x46ed57 LEA (%R12,%R10,8),%R14 |
(650) 0x46ed5b VADDSD (%R14),%XMM2,%XMM7 |
(650) 0x46ed60 VMOVSD %XMM7,(%R14) |
(650) 0x46ed65 JMP 46ed0c |
(650) 0x46ed70 NOT %R10 |
(650) 0x46ed73 MOV (%R9,%R10,8),%R14 |
(650) 0x46ed77 LEA (%R12,%R14,8),%R10 |
(650) 0x46ed7b VADDSD (%R10),%XMM12,%XMM8 |
(650) 0x46ed80 VMOVSD %XMM8,(%R10) |
(650) 0x46ed85 JMP 46ecca |
(650) 0x46ed90 NOT %R10 |
(650) 0x46ed93 MOV (%R9,%R10,8),%R14 |
(650) 0x46ed97 LEA (%R12,%R14,8),%R10 |
(650) 0x46ed9b VADDSD (%R10),%XMM15,%XMM2 |
(650) 0x46eda0 VMOVSD %XMM2,(%R10) |
(650) 0x46eda5 JMP 46ec92 |
(649) 0x46edb0 NOT %R10 |
(649) 0x46edb3 MOV (%R9,%R10,8),%R10 |
(649) 0x46edb7 LEA (%R12,%R10,8),%R13 |
(649) 0x46edbb VADDSD (%R13),%XMM12,%XMM15 |
(649) 0x46edc1 VMOVSD %XMM15,(%R13) |
(649) 0x46edc7 JMP 46ec19 |
(649) 0x46edd0 MOV (%RSP),%R14 |
(649) 0x46edd4 JMP 46e6d2 |
(649) 0x46ede0 NOT %R10 |
(649) 0x46ede3 MOV (%R9,%R10,8),%R10 |
(649) 0x46ede7 LEA (%R12,%R10,8),%R13 |
(649) 0x46edeb VADDSD (%R13),%XMM10,%XMM11 |
(649) 0x46edf1 VMOVSD %XMM11,(%R13) |
(649) 0x46edf7 JMP 46ebd8 |
0x46edfc VXORPD %XMM0,%XMM0,%XMM0 |
0x46ee00 VMOVSD %XMM0,%XMM0,%XMM1 |
0x46ee04 JMP 46e648 |
0x46ee09 XOR %R8D,%R8D |
0x46ee0c JMP 46e8e1 |
0x46ee11 XOR %R8D,%R8D |
0x46ee14 JMP 46ea77 |
(649) 0x46ee19 NOT %R10 |
(649) 0x46ee1c MOV (%R9,%R10,8),%R10 |
(649) 0x46ee20 LEA (%R12,%R10,8),%R13 |
(649) 0x46ee24 VADDSD (%R13),%XMM6,%XMM8 |
(649) 0x46ee2a VMOVSD %XMM8,(%R13) |
(649) 0x46ee30 JMP 46eb99 |
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876 |
-------------------------------------------------------------------------------- |
1774: for (i=thread_start; i < thread_stop; i++) |
1775: { |
1776: i1 = pass_array[i]; |
1777: sum_C = 0; |
1778: sum_N = 0; |
1779: j_start = P_diag_start[i1]; |
1780: j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1]; |
1781: cnt = P_diag_i[i1]; |
1782: for (j=j_start; j < j_end; j++) |
1783: { |
1784: k1 = P_diag_pass[pass][j]; |
1785: tmp_array[k1] = cnt; |
1786: P_diag_data[cnt] = 0; |
1787: P_diag_j[cnt++] = k1; |
1788: } |
1789: j_start = P_offd_start[i1]; |
1790: j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1]; |
1791: cnt_offd = P_offd_i[i1]; |
1792: for (j=j_start; j < j_end; j++) |
1793: { |
1794: k1 = P_offd_pass[pass][j]; |
1795: tmp_array_offd[k1] = cnt_offd; |
1796: P_offd_data[cnt_offd] = 0; |
1797: P_offd_j[cnt_offd++] = k1; |
1798: } |
1799: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
1800: { |
1801: j1 = S_diag_j[j]; |
1802: if (assigned[j1] == pass-1) |
1803: tmp_marker[j1] = i1; |
1804: } |
1805: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
1806: { |
1807: j1 = S_offd_j[j]; |
1808: if (assigned_offd[j1] == pass-1) |
1809: tmp_marker_offd[j1] = i1; |
1810: } |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
1838: } |
1839: } |
1840: for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++) |
1841: { |
1842: if (col_offd_S_to_A) |
1843: j1 = map_A_to_S[A_offd_j[j]]; |
1844: else |
1845: j1 = A_offd_j[j]; |
1846: |
1847: if (j1 > -1 && tmp_marker_offd[j1] == i1) |
1848: { |
1849: j_start = Pext_start[j1]; |
1850: j_end = j_start+Pext_i[j1+1]; |
1851: for (k=j_start; k < j_end; k++) |
1852: { |
1853: k1 = Pext_pass[pass][k]; |
1854: alfa = A_offd_data[j]*Pext_data[k]; |
1855: if (k1 < 0) |
1856: P_diag_data[tmp_array[-k1-1]] += alfa; |
1857: else |
1858: P_offd_data[tmp_array_offd[k1]] += alfa; |
1859: sum_C += alfa; |
1860: sum_N += alfa; |
1861: } |
1862: } |
1863: else |
1864: { |
1865: if (CF_marker_offd[j1] != -3 && |
1866: (num_functions == 1 || dof_func_offd[j1] == dof_func[i1])) |
1867: sum_N += A_offd_data[j]; |
1868: } |
1869: } |
1870: diagonal = A_diag_data[A_diag_i[i1]]; |
1871: if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal); |
1872: |
1873: for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++) |
1874: P_diag_data[j] *= alfa; |
1875: for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++) |
1876: P_offd_data[j] *= alfa; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.57 |
CQA speedup if FP arith vectorized | 1.67 |
CQA speedup if fully vectorized | 9.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.67 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
Source | par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1867-1867,par_multi_interp.c:1871-1876 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 66.83 |
CQA cycles if no scalar integer | 26.00 |
CQA cycles if FP arith vectorized | 40.00 |
CQA cycles if fully vectorized | 7.40 |
Front-end cycles | 66.83 |
DIV/SQRT cycles | 33.40 |
P0 cycles | 33.40 |
P1 cycles | 31.67 |
P2 cycles | 31.67 |
P3 cycles | 40.00 |
P4 cycles | 33.40 |
P5 cycles | 33.40 |
P6 cycles | 40.00 |
P7 cycles | 40.00 |
P8 cycles | 40.00 |
P9 cycles | 33.40 |
P10 cycles | 31.67 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 67.33 - 67.35 |
Stall cycles (UFS) | 0.00 |
Nb insns | 399.00 |
Nb uops | 400.00 |
Nb loads | 95.00 |
Nb stores | 80.00 |
Nb stack references | 28.00 |
FLOP/cycle | 0.96 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 63.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 31.48 |
Bytes prefetched | 0.00 |
Bytes loaded | 1112.00 |
Bytes stored | 992.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 22.73 |
Vectorization ratio load | 69.57 |
Vectorization ratio store | 20.00 |
Vectorization ratio mul | 84.21 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 5.88 |
Vector-efficiency ratio all | 19.32 |
Vector-efficiency ratio load | 36.41 |
Vector-efficiency ratio store | 18.28 |
Vector-efficiency ratio mul | 41.45 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 13.24 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 2.57 |
CQA speedup if FP arith vectorized | 1.67 |
CQA speedup if fully vectorized | 9.03 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.67 |
Bottlenecks | micro-operation queue, |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
Source | par_multi_interp.c:1774-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1867-1867,par_multi_interp.c:1871-1876 |
Source loop unroll info | NA |
Source loop unroll confidence level | NA |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 66.83 |
CQA cycles if no scalar integer | 26.00 |
CQA cycles if FP arith vectorized | 40.00 |
CQA cycles if fully vectorized | 7.40 |
Front-end cycles | 66.83 |
DIV/SQRT cycles | 33.40 |
P0 cycles | 33.40 |
P1 cycles | 31.67 |
P2 cycles | 31.67 |
P3 cycles | 40.00 |
P4 cycles | 33.40 |
P5 cycles | 33.40 |
P6 cycles | 40.00 |
P7 cycles | 40.00 |
P8 cycles | 40.00 |
P9 cycles | 33.40 |
P10 cycles | 31.67 |
P11 cycles | 4.00 |
Inter-iter dependencies cycles | NA |
FE+BE cycles (UFS) | 67.33 - 67.35 |
Stall cycles (UFS) | 0.00 |
Nb insns | 399.00 |
Nb uops | 400.00 |
Nb loads | 95.00 |
Nb stores | 80.00 |
Nb stack references | 28.00 |
FLOP/cycle | 0.96 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 63.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 1.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 31.48 |
Bytes prefetched | 0.00 |
Bytes loaded | 1112.00 |
Bytes stored | 992.00 |
Stride 0 | NA |
Stride 1 | NA |
Stride n | NA |
Stride unknown | NA |
Stride indirect | NA |
Vectorization ratio all | 22.73 |
Vectorization ratio load | 69.57 |
Vectorization ratio store | 20.00 |
Vectorization ratio mul | 84.21 |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | 0.00 |
Vectorization ratio other | 5.88 |
Vector-efficiency ratio all | 19.32 |
Vector-efficiency ratio load | 36.41 |
Vector-efficiency ratio store | 18.28 |
Vector-efficiency ratio mul | 41.45 |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | 12.50 |
Vector-efficiency ratio other | 13.24 |
Path / |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
Source file and lines | par_multi_interp.c:1774-1876 |
Module | exec |
nb instructions | 399 |
nb uops | 400 |
loop length | 1796 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 12 |
used ymm registers | 13 |
used zmm registers | 0 |
nb stack references | 28 |
micro-operation queue | 66.83 cycles |
front end | 66.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.40 | 33.40 | 31.67 | 31.67 | 40.00 | 33.40 | 33.40 | 40.00 | 40.00 | 40.00 | 33.40 | 31.67 |
cycles | 33.40 | 33.40 | 31.67 | 31.67 | 40.00 | 33.40 | 33.40 | 40.00 | 40.00 | 40.00 | 33.40 | 31.67 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 67.33-67.35 |
Stall cycles | 0.00 |
Front-end | 66.83 |
Dispatch | 40.00 |
DIV/SQRT | 4.00 |
Overall L1 | 66.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 72% |
load | 84% |
store | 88% |
mul | 84% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 30% |
all | 22% |
load | 69% |
store | 20% |
mul | 84% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 5% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 36% |
load | 41% |
store | 43% |
mul | 41% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 16% |
all | 19% |
load | 36% |
store | 18% |
mul | 41% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R8,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46df23 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x663> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RDX,1),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46de42 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x582> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46de21 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x561> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46de09 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x549> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddf1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x531> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddd9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x519> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddc1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x501> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46dda9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4e9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46df23 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x663> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e16a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RDX,1),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e089 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7c9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e068 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e050 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x790> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e038 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x778> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e020 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x760> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e008 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x748> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46dff0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e16a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RSI,%RDI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e1be <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x158(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R8,%RDI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e1fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RCX,%RDX,1),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46edfc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x153c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e2b0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x9f0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
JMP 46e1b6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8f6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 46e1fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xa0(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RCX,%RAX,1),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e763 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%RCX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e6ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe2c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDI,%R8,8),%XMM1,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JE 46e780 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xec0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM4,%XMM0,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VDIVSD %XMM9,%XMM10,%XMM12 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0xb8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x1(%RCX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 46ee09 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1549> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R12,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSD %XMM12,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x20,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e863 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xfa3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e851 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf91> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e844 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf84> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e837 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf77> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e82a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf6a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e81d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf5d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e810 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf50> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM11,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM13,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM14,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM15,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM2,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM6,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM7,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e8d2 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1012> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x3,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e90a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP %XMM12,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LEA (%R12,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULPD (%RDI),%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD %XMM15,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x1,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
AND $-0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R12,%RSI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD (%RSI),%XMM12,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM2,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x1(%RCX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 46ee11 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1551> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R11,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSD %XMM12,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x20,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e9f9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1139> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9e7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1127> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9da <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x111a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9cd <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x110d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9c0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1100> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9b3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x10f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9a6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x10e6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM7,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM1,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM0,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM8,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM9,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM10,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM11,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ea68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x3,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46eaa0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP %XMM12,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LEA (%R11,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULPD (%RDI),%XMM6,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD %XMM8,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x1,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
AND $-0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R11,%RSI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD (%RSI),%XMM12,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM9,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADDQ $0x8,0xf8(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,0x50(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 46dcc8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x408> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JMP 46e648 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd88> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 46e8e1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1021> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 46ea77 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11b7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
Source file and lines | par_multi_interp.c:1774-1876 |
Module | exec |
nb instructions | 399 |
nb uops | 400 |
loop length | 1796 |
used x86 registers | 15 |
used mmx registers | 0 |
used xmm registers | 12 |
used ymm registers | 13 |
used zmm registers | 0 |
nb stack references | 28 |
micro-operation queue | 66.83 cycles |
front end | 66.83 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 33.40 | 33.40 | 31.67 | 31.67 | 40.00 | 33.40 | 33.40 | 40.00 | 40.00 | 40.00 | 33.40 | 31.67 |
cycles | 33.40 | 33.40 | 31.67 | 31.67 | 40.00 | 33.40 | 33.40 | 40.00 | 40.00 | 40.00 | 33.40 | 31.67 |
Cycles executing div or sqrt instructions | 4.00 |
FE+BE cycles | 67.33-67.35 |
Stall cycles | 0.00 |
Front-end | 66.83 |
Dispatch | 40.00 |
DIV/SQRT | 4.00 |
Overall L1 | 66.83 |
all | 0% |
load | 0% |
store | 0% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 0% |
all | 72% |
load | 84% |
store | 88% |
mul | 84% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 30% |
all | 22% |
load | 69% |
store | 20% |
mul | 84% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 0% |
other | 5% |
all | 11% |
load | 12% |
store | 11% |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 12% |
all | 36% |
load | 41% |
store | 43% |
mul | 41% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 16% |
all | 19% |
load | 36% |
store | 18% |
mul | 41% |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | 12% |
other | 13% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd0(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x78(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (,%RDI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RDX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x8(%RAX),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0x148(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R8,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RAX,0xb8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xc0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46df23 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x663> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x40(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RDX,1),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46de42 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x582> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46de21 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x561> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46de09 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x549> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddf1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x531> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddd9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x519> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ddc1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x501> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46dda9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x4e9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%R9,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R12,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R13,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46df23 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x663> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RBX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x80(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RAX,%RCX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
ADD %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%RSI),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,0xa8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RAX),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RSI,0xb0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RDX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %R8,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e16a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RAX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
SUB %RAX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x48(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8,%RDX,1),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x158(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%R8,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SUB %RAX,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
AND $0x7,%R8D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e089 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7c9> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e068 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x7a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e050 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x790> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e038 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x778> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e020 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x760> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e008 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x748> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46dff0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x730> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV (%RDX,%RAX,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,(%RBX,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOVQ $0,(%R11,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
INC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %R8,-0x8(%R10,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e16a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8aa> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %R9,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x158(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x68(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA (%RSI,%RCX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV (%RSI,%RDI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e1be <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8fe> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x158(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x70(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV (%R8,%RDI,8),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e1fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93e> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV 0x58(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDI,8),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RCX,%RDX,1),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
LEA 0x1(%R8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46edfc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x153c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R15,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R8,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
LEA (%RCX,%RAX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
LEA (%RCX,%RDX,8),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %RSI,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xc8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RDX,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADD %RSI,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV 0xe8(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %R14,0xe8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
JMP 46e2b0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x9f0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
JMP 46e1b6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x8f6> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
JMP 46e1fe <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x93e> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
MOV 0xa0(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xe8(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x60(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x148(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX,%RDI,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RCX,%RAX,1),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e763 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV 0x30(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
SAL $0x3,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
MOV %R10,0xa0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %R13,0x98(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
LEA (%RAX,%RDX,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R8,0x90(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV %RSI,0x158(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0x28(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
ADD %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%RAX,%RCX,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
MOV %R14,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x38(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
JMP 46e6ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe2c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
MOV 0xa0(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x98(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV %RAX,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV 0x90(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc8(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMULSD (%RDI,%R8,8),%XMM1,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VCOMISD %XMM3,%XMM9 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
JE 46e780 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xec0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM4,%XMM0,%XMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VDIVSD %XMM9,%XMM10,%XMM12 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
MOV 0xb8(%RSP),%R8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xc0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%R8),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JGE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x1(%RCX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 46ee09 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1549> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R12,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSD %XMM12,%YMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x20,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e863 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xfa3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e851 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf91> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e844 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf84> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e837 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf77> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e82a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf6a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e81d <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf5d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e810 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xf50> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM11,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM13,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM14,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM15,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM2,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM6,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM5,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM7,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e8d2 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1012> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x3,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e90a <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP %XMM12,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LEA (%R12,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULPD (%RDI),%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD %XMM15,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x1,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46e916 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1056> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
AND $-0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R12,%RSI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD (%RSI),%XMM12,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM2,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
MOV 0xa8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0xb0(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RCX),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV (%RAX),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JLE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
MOV %RSI,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA -0x1(%RCX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 46ee11 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1551> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
LEA (%R11,%RSI,8),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VBROADCASTSD %XMM12,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
SHR $0x2,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
SAL $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA (%RDX,%RAX,1),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
SUB $0x20,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x5,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
INC %RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $0x7,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
JE 46e9f9 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1139> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x1,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9e7 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1127> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x2,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9da <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x111a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x3,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9cd <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x110d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9c0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1100> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x5,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9b3 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x10f3> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x6,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46e9a6 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x10e6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM7,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM1,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM0,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM8,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM9,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM10,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
VMULPD (%RAX),%YMM6,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x20,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
VMOVUPD %YMM11,-0x20(%RAX) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
CMP %R8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46ea68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11a8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
MOV %RCX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %R8,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
TEST $0x3,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
SUB %R8,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP $0x1,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JE 46eaa0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11e0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
ADD %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
VMOVDDUP %XMM12,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
LEA (%R11,%R8,8),%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULPD (%RDI),%XMM6,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVUPD %XMM8,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
TEST $0x1,%CL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 46eaac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11ec> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
AND $-0x2,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
ADD %RCX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
LEA (%R11,%RSI,8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMULSD (%RSI),%XMM12,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVSD %XMM9,(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
ADDQ $0x8,0xf8(%RSP) | 2 | 0.20 | 0.20 | 0.33 | 0.33 | 0.50 | 0.20 | 0.20 | 0.50 | 0.50 | 0.50 | 0.20 | 0.33 | 1 | 0.50 |
MOV 0xf8(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
CMP %RCX,0x50(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
JNE 46dcc8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x408> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
VMOVSD %XMM0,%XMM0,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
JMP 46e648 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd88> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 46e8e1 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1021> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
XOR %R8D,%R8D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 46ea77 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x11b7> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |