Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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Function: hypre_BoomerAMGCorrectCFMarker | Module: exec | Source: par_strength.c:2311-2320 | Coverage: 0.01% |
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/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2311 - 2320 |
-------------------------------------------------------------------------------- |
2311: for (i=0; i < num_var; i++) |
2312: { |
2313: if (CF_marker[i] > 0 ) |
2314: { |
2315: if (CF_marker[i] == 1) CF_marker[i] = new_CF_marker[cnt++]; |
2316: else { CF_marker[i] = 1; cnt++;} |
2317: } |
2318: } |
2319: |
2320: return 0; |
0x4839b0 TEST %RSI,%RSI |
0x4839b3 JLE 483abd |
0x4839b9 CMP $0x4,%RSI |
0x4839bd JAE 4839c6 |
0x4839bf XOR %EAX,%EAX |
0x4839c1 JMP 483ab1 |
0x4839c6 PUSH %RBP |
0x4839c7 MOV %RSP,%RBP |
0x4839ca MOV %RSI,%RCX |
0x4839cd SHR $0x2,%RCX |
0x4839d1 LEA 0x18(%RDI),%R8 |
0x4839d5 XOR %EAX,%EAX |
0x4839d7 JMP 4839f7 |
0x4839d9 NOPL (%RAX) |
(2308) 0x4839e0 MOVQ $0x1,(%R8) |
(2308) 0x4839e7 INC %RAX |
(2308) 0x4839ea ADD $0x20,%R8 |
(2308) 0x4839ee DEC %RCX |
(2308) 0x4839f1 JE 483ab0 |
(2308) 0x4839f7 MOV -0x18(%R8),%R9 |
(2308) 0x4839fb TEST %R9,%R9 |
(2308) 0x4839fe JLE 483a2b |
(2308) 0x483a00 CMP $0x1,%R9 |
(2308) 0x483a04 JNE 483a20 |
(2308) 0x483a06 MOV (%RDX,%RAX,8),%R9 |
(2308) 0x483a0a INC %RAX |
(2308) 0x483a0d MOV %R9,-0x18(%R8) |
(2308) 0x483a11 JMP 483a2b |
0x483a13 NOPW %CS:(%RAX,%RAX,1) |
(2308) 0x483a20 MOVQ $0x1,-0x18(%R8) |
(2308) 0x483a28 INC %RAX |
(2308) 0x483a2b MOV -0x10(%R8),%R9 |
(2308) 0x483a2f TEST %R9,%R9 |
(2308) 0x483a32 JLE 483a5b |
(2308) 0x483a34 CMP $0x1,%R9 |
(2308) 0x483a38 JNE 483a50 |
(2308) 0x483a3a MOV (%RDX,%RAX,8),%R9 |
(2308) 0x483a3e INC %RAX |
(2308) 0x483a41 MOV %R9,-0x10(%R8) |
(2308) 0x483a45 JMP 483a5b |
0x483a47 NOPW (%RAX,%RAX,1) |
(2308) 0x483a50 MOVQ $0x1,-0x10(%R8) |
(2308) 0x483a58 INC %RAX |
(2308) 0x483a5b MOV -0x8(%R8),%R9 |
(2308) 0x483a5f TEST %R9,%R9 |
(2308) 0x483a62 JLE 483a8b |
(2308) 0x483a64 CMP $0x1,%R9 |
(2308) 0x483a68 JNE 483a80 |
(2308) 0x483a6a MOV (%RDX,%RAX,8),%R9 |
(2308) 0x483a6e INC %RAX |
(2308) 0x483a71 MOV %R9,-0x8(%R8) |
(2308) 0x483a75 JMP 483a8b |
0x483a77 NOPW (%RAX,%RAX,1) |
(2308) 0x483a80 MOVQ $0x1,-0x8(%R8) |
(2308) 0x483a88 INC %RAX |
(2308) 0x483a8b MOV (%R8),%R9 |
(2308) 0x483a8e TEST %R9,%R9 |
(2308) 0x483a91 JLE 4839ea |
(2308) 0x483a97 CMP $0x1,%R9 |
(2308) 0x483a9b JNE 4839e0 |
(2308) 0x483aa1 MOV (%RDX,%RAX,8),%R9 |
(2308) 0x483aa5 INC %RAX |
(2308) 0x483aa8 MOV %R9,(%R8) |
(2308) 0x483aab JMP 4839ea |
0x483ab0 POP %RBP |
0x483ab1 MOV %RSI,%RCX |
0x483ab4 AND $-0x4,%RCX |
0x483ab8 CMP %RSI,%RCX |
0x483abb JB 483ad3 |
0x483abd XOR %EAX,%EAX |
0x483abf RET |
(2307) 0x483ac0 MOVQ $0x1,(%RDI,%RCX,8) |
(2307) 0x483ac8 INC %RAX |
(2307) 0x483acb INC %RCX |
(2307) 0x483ace CMP %RCX,%RSI |
(2307) 0x483ad1 JE 483abd |
(2307) 0x483ad3 MOV (%RDI,%RCX,8),%R8 |
(2307) 0x483ad7 TEST %R8,%R8 |
(2307) 0x483ada JLE 483acb |
(2307) 0x483adc CMP $0x1,%R8 |
(2307) 0x483ae0 JNE 483ac0 |
(2307) 0x483ae2 MOV (%RDX,%RAX,8),%R8 |
(2307) 0x483ae6 INC %RAX |
(2307) 0x483ae9 MOV %R8,(%RDI,%RCX,8) |
(2307) 0x483aed JMP 483acb |
0x483aef NOP |
Path / |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 25 |
nb uops | 25 |
loop length | 96 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.17 cycles |
front end | 4.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
cycles | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.26 |
Stall cycles | 0.00 |
Front-end | 4.17 |
Dispatch | 2.50 |
Overall L1 | 4.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 483abd <hypre_BoomerAMGCorrectCFMarker+0x10d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4839c6 <hypre_BoomerAMGCorrectCFMarker+0x16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 483ab1 <hypre_BoomerAMGCorrectCFMarker+0x101> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4839f7 <hypre_BoomerAMGCorrectCFMarker+0x47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 483ad3 <hypre_BoomerAMGCorrectCFMarker+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Source file and lines | par_strength.c:2311-2320 |
Module | exec |
nb instructions | 25 |
nb uops | 25 |
loop length | 96 |
used x86 registers | 7 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 4.17 cycles |
front end | 4.17 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
cycles | 2.50 | 1.40 | 0.67 | 0.67 | 0.50 | 1.40 | 2.50 | 0.50 | 0.50 | 0.50 | 1.20 | 0.67 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 4.26 |
Stall cycles | 0.00 |
Front-end | 4.17 |
Dispatch | 2.50 |
Overall L1 | 4.17 |
all | 0% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 0% |
all | 12% |
load | NA (no load vectorizable/vectorized instructions) |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 12% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
TEST %RSI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JLE 483abd <hypre_BoomerAMGCorrectCFMarker+0x10d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
CMP $0x4,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JAE 4839c6 <hypre_BoomerAMGCorrectCFMarker+0x16> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 483ab1 <hypre_BoomerAMGCorrectCFMarker+0x101> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
SHR $0x2,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
LEA 0x18(%RDI),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
JMP 4839f7 <hypre_BoomerAMGCorrectCFMarker+0x47> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
MOV %RSI,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
AND $-0x4,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
CMP %RSI,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JB 483ad3 <hypre_BoomerAMGCorrectCFMarker+0x123> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
XOR %EAX,%EAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
Name | Coverage (%) | Time (s) |
---|---|---|
▼hypre_BoomerAMGCorrectCFMarker– | 0.01 | 0 |
○Loop 2308 - par_strength.c:2311-2316 - exec | 0.01 | 0.07 |
○Loop 2307 - par_strength.c:2311-2316 - exec | 0 | 0 |