Loop Id: 2112 | Module: exec | Source: ams.c:3672-3675 | Coverage: 0.2% |
---|
Loop Id: 2112 | Module: exec | Source: ams.c:3672-3675 | Coverage: 0.2% |
---|
0x51375b VMOVDQU (%RSI,%RCX,1),%YMM10 [2] |
0x513760 VMOVDQU 0x20(%RSI,%RCX,1),%YMM12 [2] |
0x513766 VMOVAPD %YMM2,%YMM11 |
0x51376a VMOVAPD %YMM2,%YMM1 |
0x51376e VMOVDQU 0x40(%RSI,%RCX,1),%YMM13 [2] |
0x513774 VMOVDQU 0x60(%RSI,%RCX,1),%YMM8 [2] |
0x51377a VMOVAPD %YMM2,%YMM14 |
0x51377e VMOVAPD %YMM2,%YMM7 |
0x513782 VGATHERQPD %YMM11,(%R8,%YMM10,8),%YMM9 [6] |
0x513788 VFNMADD132PD (%RDI,%RCX,1),%YMM0,%YMM9 [7] |
0x51378e VGATHERQPD %YMM1,(%R8,%YMM12,8),%YMM0 [5] |
0x513794 VMOVDQU 0x80(%RSI,%RCX,1),%YMM10 [2] |
0x51379d VFNMADD132PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 [7] |
0x5137a4 VMOVAPD %YMM2,%YMM9 |
0x5137a8 VMOVAPD %YMM2,%YMM12 |
0x5137ac VGATHERQPD %YMM14,(%R8,%YMM13,8),%YMM15 [4] |
0x5137b2 VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM15 [7] |
0x5137b9 VGATHERQPD %YMM7,(%R8,%YMM8,8),%YMM11 [3] |
0x5137bf VMOVDQU 0xa0(%RSI,%RCX,1),%YMM14 [2] |
0x5137c8 VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM15,%YMM11 [7] |
0x5137cf VMOVAPD %YMM2,%YMM15 |
0x5137d3 VMOVAPD %YMM2,%YMM7 |
0x5137d7 VMOVDQU 0xc0(%RSI,%RCX,1),%YMM13 [2] |
0x5137e0 VGATHERQPD %YMM9,(%R8,%YMM10,8),%YMM1 [10] |
0x5137e6 VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM11,%YMM1 [7] |
0x5137f0 VGATHERQPD %YMM12,(%R8,%YMM14,8),%YMM0 [1] |
0x5137f6 VMOVDQU 0xe0(%RSI,%RCX,1),%YMM11 [2] |
0x5137ff VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM1,%YMM0 [7] |
0x513809 VGATHERQPD %YMM15,(%R8,%YMM13,8),%YMM8 [9] |
0x51380f VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM0,%YMM8 [7] |
0x513819 VGATHERQPD %YMM7,(%R8,%YMM11,8),%YMM0 [8] |
0x51381f VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM8,%YMM0 [7] |
0x513829 ADD $0x100,%RCX |
0x513830 CMP %RCX,%R15 |
0x513833 JNE 51375b |
/scratch_na/users/xoserete/qaas_runs/171-172-8217/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3672 - 3675 |
-------------------------------------------------------------------------------- |
3672: for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++) |
3673: { |
3674: ii = A_diag_j[jj]; |
3675: res -= A_diag_data[jj] * Vtemp_data[ii]; |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 6.19 |
Bottlenecks | |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source | ams.c:3672-3675 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 99.00 |
CQA cycles if no scalar integer | 32.00 - 99.00 |
CQA cycles if FP arith vectorized | 25.14 - 77.79 |
CQA cycles if fully vectorized | 16.00 - 49.50 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 13.33 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 13.17 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 99 |
FE+BE cycles (UFS) | 32.87 - 362.22 |
Stall cycles (UFS) | 20.02 - 349.37 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.65 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.76 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 6.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.27 |
CQA speedup if fully vectorized | 2.00 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 2.00 - 6.19 |
Bottlenecks | |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source | ams.c:3672-3675 |
Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
Source loop unroll confidence level | max |
Unroll/vectorization loop type | NA |
Unroll factor | NA |
CQA cycles | 32.00 - 99.00 |
CQA cycles if no scalar integer | 32.00 - 99.00 |
CQA cycles if FP arith vectorized | 25.14 - 77.79 |
CQA cycles if fully vectorized | 16.00 - 49.50 |
Front-end cycles | 12.33 |
DIV/SQRT cycles | 13.33 |
P0 cycles | 13.50 |
P1 cycles | 16.00 |
P2 cycles | 16.00 |
P3 cycles | 0.00 |
P4 cycles | 13.17 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 1.00 |
P10 cycles | 16.00 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 32 - 99 |
FE+BE cycles (UFS) | 32.87 - 362.22 |
Stall cycles (UFS) | 20.02 - 349.37 |
Nb insns | 35.00 |
Nb uops | 66.00 |
Nb loads | 24.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 2.00 - 0.65 |
Nb FLOP add-sub | 0.00 |
Nb FLOP mul | 0.00 |
Nb FLOP fma | 32.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 7.76 - 24.00 |
Bytes prefetched | 0.00 |
Bytes loaded | 768.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 2.00 |
Stride n | 0.00 |
Stride unknown | 0.00 |
Stride indirect | 6.00 |
Vectorization ratio all | 100.00 |
Vectorization ratio load | 100.00 |
Vectorization ratio store | NA |
Vectorization ratio mul | NA |
Vectorization ratio add_sub | NA |
Vectorization ratio fma | 100.00 |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 100.00 |
Vector-efficiency ratio all | 50.00 |
Vector-efficiency ratio load | 50.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | NA |
Vector-efficiency ratio add_sub | NA |
Vector-efficiency ratio fma | 50.00 |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 50.00 |
Path / |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source file and lines | ams.c:3672-3675 |
Module | exec |
nb instructions | 35 |
nb uops | 66 |
loop length | 222 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 12 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 13.33 | 13.50 | 16.00 | 16.00 | 0.00 | 13.17 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 13.33 | 13.50 | 16.00 | 16.00 | 0.00 | 13.17 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-99.00 |
FE+BE cycles | 32.87-362.22 |
Stall cycles | 20.02-349.37 |
PRF_FLOAT full (events) | 24.82-356.75 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-99.00 |
Overall L1 | 32.00-99.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x20(%RSI,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVAPD %YMM2,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQU 0x40(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVAPD %YMM2,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VGATHERQPD %YMM11,(%R8,%YMM10,8),%YMM9 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD (%RDI,%RCX,1),%YMM0,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM1,(%R8,%YMM12,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM2,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VGATHERQPD %YMM14,(%R8,%YMM13,8),%YMM15 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM7,(%R8,%YMM8,8),%YMM11 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xa0(%RSI,%RCX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM15,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM2,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQU 0xc0(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD %YMM9,(%R8,%YMM10,8),%YMM1 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM11,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM12,(%R8,%YMM14,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RCX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM15,(%R8,%YMM13,8),%YMM8 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM0,%YMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM7,(%R8,%YMM11,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 51375b <hypre_ParCSRRelaxThreads._omp_fn.1+0x20b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_ParCSRRelaxThreads._omp_fn.1 |
Source file and lines | ams.c:3672-3675 |
Module | exec |
nb instructions | 35 |
nb uops | 66 |
loop length | 222 |
used x86 registers | 5 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 12 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 12.33 cycles |
front end | 12.33 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 13.33 | 13.50 | 16.00 | 16.00 | 0.00 | 13.17 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
cycles | 13.33 | 13.50 | 16.00 | 16.00 | 0.00 | 13.17 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 16.00 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 32.00-99.00 |
FE+BE cycles | 32.87-362.22 |
Stall cycles | 20.02-349.37 |
PRF_FLOAT full (events) | 24.82-356.75 |
Front-end | 12.33 |
Dispatch | 16.00 |
Data deps. | 32.00-99.00 |
Overall L1 | 32.00-99.00 |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 100% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | NA (no other vectorizable/vectorized instructions) |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | 50% |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VMOVDQU (%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x20(%RSI,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVAPD %YMM2,%YMM11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQU 0x40(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVDQU 0x60(%RSI,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VMOVAPD %YMM2,%YMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VGATHERQPD %YMM11,(%R8,%YMM10,8),%YMM9 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD (%RDI,%RCX,1),%YMM0,%YMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM1,(%R8,%YMM12,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0x80(%RSI,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0x20(%RDI,%RCX,1),%YMM9,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM2,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VGATHERQPD %YMM14,(%R8,%YMM13,8),%YMM15 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x40(%RDI,%RCX,1),%YMM0,%YMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM7,(%R8,%YMM8,8),%YMM11 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xa0(%RSI,%RCX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0x60(%RDI,%RCX,1),%YMM15,%YMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VMOVAPD %YMM2,%YMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVAPD %YMM2,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
VMOVDQU 0xc0(%RSI,%RCX,1),%YMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VGATHERQPD %YMM9,(%R8,%YMM10,8),%YMM1 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0x80(%RDI,%RCX,1),%YMM11,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM12,(%R8,%YMM14,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VMOVDQU 0xe0(%RSI,%RCX,1),%YMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
VFNMADD132PD 0xa0(%RDI,%RCX,1),%YMM1,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM15,(%R8,%YMM13,8),%YMM8 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xc0(%RDI,%RCX,1),%YMM0,%YMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
VGATHERQPD %YMM7,(%R8,%YMM11,8),%YMM0 | 5 | 1.33 | 1.33 | 1.33 | 1.33 | 0 | 1.33 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
VFNMADD132PD 0xe0(%RDI,%RCX,1),%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
CMP %RCX,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JNE 51375b <hypre_ParCSRRelaxThreads._omp_fn.1+0x20b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |