Loop Id: 1496 | Module: libparcsr_ls.so | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.06% |
---|
Loop Id: 1496 | Module: libparcsr_ls.so | Source: par_lr_interp.c:1221-1627 [...] | Coverage: 0.06% |
---|
0x57c40 MOV (%RBX,%R8,8),%R10 [2] |
0x57c44 MOV 0x8(%RBX,%R8,8),%RDX [2] |
0x57c49 MOV 0x10(%RBX,%R8,8),%R9 [2] |
0x57c4e MOV 0x18(%RBX,%R8,8),%R15 [2] |
0x57c53 VMOVQ (%R13,%R15,8),%XMM13 [4] |
0x57c5a VMOVQ (%R13,%R9,8),%XMM14 [5] |
0x57c61 VPUNPCKLQDQ %XMM13,%XMM14,%XMM13 |
0x57c66 VMOVQ (%R13,%RDX,8),%XMM14 [3] |
0x57c6d VMOVQ (%R13,%R10,8),%XMM15 [1] |
0x57c74 VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 |
0x57c79 VINSERTI128 $0x1,%XMM13,%YMM14,%YMM13 |
0x57c7f VPCMPGTQ %YMM13,%YMM8,%YMM13 |
0x57c84 VPXOR %YMM2,%YMM13,%YMM13 |
0x57c88 VPCMPEQQ (%RBX,%R8,8),%YMM9,%YMM14 [2] |
0x57c8e VPOR %YMM14,%YMM13,%YMM13 |
0x57c93 VMASKMOVPD (%R14,%R8,8),%YMM13,%YMM14 [6] |
0x57c99 VMULPD %YMM12,%YMM14,%YMM15 |
0x57c9e VCMPPD $0x1,%YMM3,%YMM15,%YMM15 |
0x57ca3 VANDPD %YMM15,%YMM13,%YMM13 |
0x57ca8 VBLENDVPD %YMM13,%YMM14,%YMM4,%YMM13 |
0x57cae VADDPD %YMM13,%YMM10,%YMM10 |
0x57cb3 ADD $0x4,%R8 |
0x57cb7 CMP %RDI,%R8 |
0x57cba JBE 57c40 |
/scratch_na/users/xoserete/qaas_runs/171-587-0005/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1221 - 1627 |
-------------------------------------------------------------------------------- |
1221: if (n_fine) |
[...] |
1624: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1625: { |
1626: i2 = A_diag_j[jj1]; |
1627: if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0) |
Coverage (%) | Name | Source Location | Module |
---|---|---|---|
►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
○ | __kmp_invoke_task_func | libiomp5.so |
Path / |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.17 |
CQA speedup if fully vectorized | 2.70 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.03 |
Bottlenecks | P0, |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1221,par_lr_interp.c:1624-1627 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | medium |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 5.17 |
CQA cycles if no scalar integer | 5.17 |
CQA cycles if FP arith vectorized | 4.42 |
CQA cycles if fully vectorized | 1.92 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 5.17 |
P0 cycles | 5.00 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 0.00 |
P4 cycles | 4.83 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 5.55 - 5.61 |
Stall cycles (UFS) | 0.29 - 0.36 |
Nb insns | 24.00 |
Nb uops | 26.00 |
Nb loads | 10.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.55 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.77 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 64.71 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 80.00 |
Vector-efficiency ratio all | 35.29 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 40.00 |
Metric | Value |
---|---|
CQA speedup if no scalar integer | 1.00 |
CQA speedup if FP arith vectorized | 1.17 |
CQA speedup if fully vectorized | 2.70 |
CQA speedup if no inter-iteration dependency | NA |
CQA speedup if next bottleneck killed | 1.03 |
Bottlenecks | P0, |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source | par_lr_interp.c:1221-1221,par_lr_interp.c:1624-1627 |
Source loop unroll info | unrolled by 8 |
Source loop unroll confidence level | medium |
Unroll/vectorization loop type | main |
Unroll factor | 8 |
CQA cycles | 5.17 |
CQA cycles if no scalar integer | 5.17 |
CQA cycles if FP arith vectorized | 4.42 |
CQA cycles if fully vectorized | 1.92 |
Front-end cycles | 4.50 |
DIV/SQRT cycles | 5.17 |
P0 cycles | 5.00 |
P1 cycles | 3.33 |
P2 cycles | 3.33 |
P3 cycles | 0.00 |
P4 cycles | 4.83 |
P5 cycles | 1.00 |
P6 cycles | 0.00 |
P7 cycles | 0.00 |
P8 cycles | 0.00 |
P9 cycles | 0.00 |
P10 cycles | 3.33 |
P11 cycles | 0.00 |
Inter-iter dependencies cycles | 3 |
FE+BE cycles (UFS) | 5.55 - 5.61 |
Stall cycles (UFS) | 0.29 - 0.36 |
Nb insns | 24.00 |
Nb uops | 26.00 |
Nb loads | 10.00 |
Nb stores | 0.00 |
Nb stack references | 0.00 |
FLOP/cycle | 1.55 |
Nb FLOP add-sub | 4.00 |
Nb FLOP mul | 4.00 |
Nb FLOP fma | 0.00 |
Nb FLOP div | 0.00 |
Nb FLOP rcp | 0.00 |
Nb FLOP sqrt | 0.00 |
Nb FLOP rsqrt | 0.00 |
Bytes/cycle | 24.77 |
Bytes prefetched | 0.00 |
Bytes loaded | 128.00 |
Bytes stored | 0.00 |
Stride 0 | 0.00 |
Stride 1 | 1.00 |
Stride n | 1.00 |
Stride unknown | 0.00 |
Stride indirect | 4.00 |
Vectorization ratio all | 64.71 |
Vectorization ratio load | 33.33 |
Vectorization ratio store | NA |
Vectorization ratio mul | 100.00 |
Vectorization ratio add_sub | 100.00 |
Vectorization ratio fma | NA |
Vectorization ratio div_sqrt | NA |
Vectorization ratio other | 80.00 |
Vector-efficiency ratio all | 35.29 |
Vector-efficiency ratio load | 25.00 |
Vector-efficiency ratio store | NA |
Vector-efficiency ratio mul | 50.00 |
Vector-efficiency ratio add_sub | 50.00 |
Vector-efficiency ratio fma | NA |
Vector-efficiency ratio div_sqrt | NA |
Vector-efficiency ratio other | 40.00 |
Path / |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | libparcsr_ls.so |
nb instructions | 24 |
nb uops | 26 |
loop length | 124 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.17 | 5.00 | 3.33 | 3.33 | 0.00 | 4.83 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
cycles | 5.17 | 5.00 | 3.33 | 3.33 | 0.00 | 4.83 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 5.55-5.61 |
Stall cycles | 0.29-0.36 |
RS full (events) | 0.01-0.00 |
PRF_FLOAT full (events) | 0.40-0.50 |
Front-end | 4.50 |
Dispatch | 5.17 |
Data deps. | 3.00 |
Overall L1 | 5.17 |
all | 45% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 71% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 64% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 80% |
all | 27% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 35% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 35% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RBX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX,%R8,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX,%R8,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX,%R8,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R15,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R9,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM13,%XMM14,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ (%R13,%RDX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R10,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI128 $0x1,%XMM13,%YMM14,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM13,%YMM8,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPXOR %YMM2,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ (%RBX,%R8,8),%YMM9,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VPOR %YMM14,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMASKMOVPD (%R14,%R8,8),%YMM13,%YMM14 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 8-9 | 0.40 |
VMULPD %YMM12,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM3,%YMM15,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VANDPD %YMM15,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM13,%YMM14,%YMM4,%YMM13 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VADDPD %YMM13,%YMM10,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 57c40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1560> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
Source file and lines | par_lr_interp.c:1221-1627 |
Module | libparcsr_ls.so |
nb instructions | 24 |
nb uops | 26 |
loop length | 124 |
used x86 registers | 9 |
used mmx registers | 0 |
used xmm registers | 3 |
used ymm registers | 10 |
used zmm registers | 0 |
nb stack references | 0 |
ADD-SUB / MUL ratio | 1.00 |
micro-operation queue | 4.50 cycles |
front end | 4.50 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 5.17 | 5.00 | 3.33 | 3.33 | 0.00 | 4.83 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
cycles | 5.17 | 5.00 | 3.33 | 3.33 | 0.00 | 4.83 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.33 |
Cycles executing div or sqrt instructions | NA |
Longest recurrence chain latency (RecMII) | 3.00 |
FE+BE cycles | 5.55-5.61 |
Stall cycles | 0.29-0.36 |
RS full (events) | 0.01-0.00 |
PRF_FLOAT full (events) | 0.40-0.50 |
Front-end | 4.50 |
Dispatch | 5.17 |
Data deps. | 3.00 |
Overall L1 | 5.17 |
all | 45% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 71% |
all | 100% |
load | 100% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 100% |
all | 64% |
load | 33% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 100% |
add-sub | 100% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 80% |
all | 27% |
load | 20% |
store | NA (no store vectorizable/vectorized instructions) |
mul | NA (no mul vectorizable/vectorized instructions) |
add-sub | NA (no add-sub vectorizable/vectorized instructions) |
fma | NA (no fma vectorizable/vectorized instructions) |
other | 35% |
all | 50% |
load | 50% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 50% |
all | 35% |
load | 25% |
store | NA (no store vectorizable/vectorized instructions) |
mul | 50% |
add-sub | 50% |
fma | NA (no fma vectorizable/vectorized instructions) |
div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
other | 40% |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
MOV (%RBX,%R8,8),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x8(%RBX,%R8,8),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x10(%RBX,%R8,8),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
MOV 0x18(%RBX,%R8,8),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R15,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R9,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM13,%XMM14,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VMOVQ (%R13,%RDX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VMOVQ (%R13,%R10,8),%XMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
VPUNPCKLQDQ %XMM14,%XMM15,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
VINSERTI128 $0x1,%XMM13,%YMM14,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
VPCMPGTQ %YMM13,%YMM8,%YMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0-3 | 1 |
VPXOR %YMM2,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
VPCMPEQQ (%RBX,%R8,8),%YMM9,%YMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
VPOR %YMM14,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VMASKMOVPD (%R14,%R8,8),%YMM13,%YMM14 | 2 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 8-9 | 0.40 |
VMULPD %YMM12,%YMM14,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VCMPPD $0x1,%YMM3,%YMM15,%YMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
VANDPD %YMM15,%YMM13,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
VBLENDVPD %YMM13,%YMM14,%YMM4,%YMM13 | 3 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2-3 | 1 |
VADDPD %YMM13,%YMM10,%YMM10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
ADD $0x4,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
CMP %RDI,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
JBE 57c40 <hypre_BoomerAMGBuildExtPIInterp.extracted+0x1560> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |